coreboot July 2007

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[LinuxBIOS] r431 - in LinuxBIOSv3: . include include/arch/x86/arch
by svn＠openbios.org 03 Jul '07

03 Jul '07

Author: uwe Date: 2007-07-03 18:58:16 +0200 (Tue, 03 Jul 2007) New Revision: 431 Modified: LinuxBIOSv3/HACKING LinuxBIOSv3/include/arch/x86/arch/spinlock.h LinuxBIOSv3/include/spinlock.h Log: Document origin of include/arch/x86/arch/spinlock.h and use proper header. Some other minor fixes (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: LinuxBIOSv3/HACKING =================================================================== --- LinuxBIOSv3/HACKING 2007-07-02 20:57:45 UTC (rev 430) +++ LinuxBIOSv3/HACKING 2007-07-03 16:58:16 UTC (rev 431) @@ -95,6 +95,11 @@ Files: include/asm-i386/processor.h, arch/i386/kernel/cpu/mtrr/state.c Current version we use: 297d9c035edd04327fedc0d1da27c2b112b66fcc (06/2007) +* include/arch/x86/arch/spinlock.h: GPLv2 + Source: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6 + Files: include/asm-i386/spinlock.h, include/asm-i386/spinlock_types.h + Current version we use: 139ec7c416248b9ea227d21839235344edfee1e0 (12/2006) + * include/arch/x86/swab.h: GPLv2 Source: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6 Current version we use: ? Modified: LinuxBIOSv3/include/arch/x86/arch/spinlock.h =================================================================== --- LinuxBIOSv3/include/arch/x86/arch/spinlock.h 2007-07-02 20:57:45 UTC (rev 430) +++ LinuxBIOSv3/include/arch/x86/arch/spinlock.h 2007-07-03 16:58:16 UTC (rev 431) @@ -1,35 +1,26 @@ /* * This file is part of the LinuxBIOS project. * + * It is based on the Linux kernel file include/asm-i386/spinlock.h. + * + * Modifications are: * Copyright (C) 2001 Linux Networx + * (Written by Eric Biederman <ebiederman(a)lnxi.com> for Linux Networx) * Copyright (C) 2007 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) */ #ifndef ARCH_SPINLOCK_H #define ARCH_SPINLOCK_H /* - * Your basic SMP spinlocks, allowing only a single CPU anywhere + * Your basic SMP spinlocks, allowing only a single CPU anywhere. */ struct spinlock { volatile unsigned int lock; }; - #define SPIN_LOCK_UNLOCKED (struct spinlock) { 1 } /* @@ -38,7 +29,7 @@ * * We make no fairness assumptions. They have a cost. */ -#define barrier() __asm__ __volatile__("": : :"memory") +#define barrier() __asm__ __volatile__("": : :"memory") #define spin_is_locked(x) (*(volatile char *)(&(x)->lock) <= 0) #define spin_unlock_wait(x) do { barrier(); } while(spin_is_locked(x)) @@ -76,5 +67,4 @@ #define spin_define(spin) static struct spinlock spin = SPIN_LOCK_UNLOCKED - #endif /* ARCH_SPINLOCK_H */ Modified: LinuxBIOSv3/include/spinlock.h =================================================================== --- LinuxBIOSv3/include/spinlock.h 2007-07-02 20:57:45 UTC (rev 430) +++ LinuxBIOSv3/include/spinlock.h 2007-07-03 16:58:16 UTC (rev 431) @@ -2,20 +2,22 @@ * This file is part of the LinuxBIOS project. * * Copyright (C) 2001 Linux Networx + * (Written by Eric Biederman <ebiederman(a)lnxi.com> for Linux Networx) * Copyright (C) 2007 coresystems GmbH + * (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef SPINLOCK_H @@ -32,7 +34,8 @@ #define spin_unlock_wait(lock) do {} while(0) #define spin_lock(lock) do {} while(0) #define spin_unlock(lock) do {} while(0) -#define spin_define(lock) /* empty */ +#define spin_define(lock) /* empty */ + #endif #endif /* SPINLOCK_H */

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[LinuxBIOS] Gigabyte contact
by Alan Carvalho de Assis 03 Jul '07

03 Jul '07

Hi guys, I am looking for gigabyte contacts to request a mainboard donation because I want add support to it on LBdistro. I contacted Gigabyte Brazil (Digitrom) but they don't manufacture this board here in Brazil and don't make efforts to contact Gigabyte international do request one. Then if someone has a channel of communication with Gigabyte let me know. Cheers, Alan

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[LinuxBIOS] Porting Linux BIOS to MSI ms7250 (k9n platinum) motherboard
by George V. Adamov 03 Jul '07

03 Jul '07

Porting LinuxBios on MSI ms7250 motherbord I have a problem - after memory initialization, it goes to soft reset... So far have no idea why... LinuxBIOS-2.0.0_Fallback Thu Jun 28 12:26:54 UTC 2007 starting... core0 started: SBLink=00 NC node|link=00 mcp55_num:01 Ram1.00 Ram2.00 Unbuffered 333Mhz Interleaved RAM: 0x00100000 KB Ram3 Initializing memory: done Setting variable MTRR 02, base: 0000MB, range: 0400MB, type WB DQS Training:RcvrEn:Pass1: 00 CTLRMaxDelay=aeDQS Training:tsc[00]=000000000ee58519 DQS Training:tsc[01]=000ceea800001000 DQS Training:tsc[02]=000ceea48000c298 DQS Training:tsc[03]=000ceeb0ffff03da DQS Training:tsc[04]=000000001065ffaf Ram4 v_esp=000cefe4 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: INIT detected from ---- {APICID = 00 NODEID = 00 COREID = 00} --- Issuing SOFT_RESET...

2 1

[LinuxBIOS] [RFC] v3: dts fixes and questions
by Uwe Hermann 03 Jul '07

03 Jul '07

Here's a patch which streamlines the dts contents a bit: - Every "thing" should have an "enable;" line (or am I missing some reason why they shouldn't?) - Every "thing" should have the "enable;" as first entry, if it has one. - Constructors should come before other stuff, but after the "enable;". Comments? Does the order in which variables are defined (e.g. ide0_enable) and in which the constructors are called matter? I.e. is there a semantic difference between { ide0_enable = "0"; ide1_enable = "0"; constructor = "i82371eb_constructors"; }; and { constructor = "i82371eb_constructors"; ide0_enable = "0"; ide1_enable = "0"; }; ? See patch for my proposal, but please note that it may be incorrent, that's why I'm asking... Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[LinuxBIOS] SDD byte 31
by Joseph Smith 03 Jul '07

03 Jul '07

Hello, Corey or Uwe, maybe you can help me. Where did you get the SDD byte 31 values? Is there a chart somewhere? Can you point me in the right direction? Thanks - Joe

2 1

Re: [LinuxBIOS] r387 - in LinuxBIOSv3/arch/x86: . geodelx
by Peter Stuge 03 Jul '07

03 Jul '07

On Wed, Jun 27, 2007 at 11:07:10PM +0200, svn(a)openbios.org wrote: > +++ LinuxBIOSv3/arch/x86/Makefile 2007-06-27 21:07:10 UTC (rev 387) .. > +$(obj)/arch/x86/geodelx/stage0.o: $(src)/arch/x86/geodelx/stage0.S > + $(Q)mkdir -p $(obj)/arch/x86/geodelx Uh? The rule depends on a file in a directory created in the rule? > + $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" > + $(Q)$(CC) -E $(LINUXBIOSINCLUDE) $< \ > + -o $(obj)/arch/x86/stage0_asm.s -DBOOTBLK=0x1f00 \ > + -DRESRVED=0xf0 -DDATE=\"`date +%Y/%m/%d`\" Maybe even the svn rev date? > + /* Setup access to the cache for under 640K. Note MC not setup yet. */ > + msr.hi = 0x20000000; > + msr.lo = 0xfff80; > + wrmsr(MSR_GLIU0 + 0x20, msr); > + > + msr.hi = 0x20000000; > + msr.lo = 0x80fffe0; > + wrmsr(MSR_GLIU0 + 0x21, msr); > + > + msr.hi = 0x20000000; > + msr.lo = 0xfff80; > + wrmsr(MSR_GLIU1 + 0x20, msr); > + > + msr.hi = 0x20000000; > + msr.lo = 0x80fffe0; > + wrmsr(MSR_GLIU1 + 0x21, msr); No nice #defines around for these? > +/** > + * start_time1 Starts Timer 1 for port 61 use. FIXME try to figure > + * out what these values mean. > + */ > +void start_timer1(void) > +{ > + outb(0x56, 0x43); > + outb(0x12, 0x41); > +} 0x43 is PIT command/control. 0x41 is PIT counter 1. 0x56 means write counter 1 lower 8 bits in next IO, set the counter mode to square wave generator (count down to 0 from programmed value twice in a row, alternating the output signal) counting in 16-bit binary mode. 0x12 is written to the counter. Used for RAM refresh on XT/AT but the port 61 reference indicates it has to do with the (emulated?) keyboard controller. > + msr_t msrGlcpSysRstpll; This guy could use a better name. At least no caps. > + msrGlcpSysRstpll.lo &= > + ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT); > + msrGlcpSysRstpll.lo |= > + (0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT); Why 0xDE ? > + /* You should never get here..... The chip has reset. */ > + printk(BIOS_EMERG,"CONFIGURING PLL FAILURE -- HALT\n"); > + post_code(POST_PLL_RESET_FAIL); > + __asm__ __volatile__("hlt\n"); How about that hlt() function? Remember we want to put panic room code there when we have too much spare time. > +/** > + * Return the CPU clock rate. Rates in this system are always returned > + * as multkiples of 33 Mhz. > + * > + */ > +u32 cpu_speed(void) Is there a doxygen syntax for the return value? Also please say which unit the value is in. MHz? > +/** > + * Return the Geode Link clock rate. Rates in this system are always > + * returned as multkiples of 33 Mhz. > + * > + */ > +u32 geode_link_speed(void) Ditto. > + speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) / 10; > + if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) { Maybe that 0x1F is a #define? > +/** > + * Return the PCI bus clock rate. Rates in this system are always > + * returned as multkiples of 33 Mhz. > + * > + */ > +u32 pci_speed(void) Doxygen return value comment here too? > + msrnum = GLCP_DELAY_CONTROLS; > + msr = rdmsr(msrnum); > + if (msr.lo & ~(0x7C0)) { > + return; > + } The juju must stay but 0x7c0 seems like a #define? > + if (spdbyte0 == 0 || spdbyte1 == 0) { > + /* one dimm solution */ > + if (spdbyte1 == 0) { > + msr.hi |= 0x000800000; > + } > + spdbyte0 += spdbyte1; > + if (spdbyte0 > 8) { > + /* large dimm */ > + if (glspeed < 334) { > + msr.hi |= 0x0837100AA; > + msr.lo |= 0x056960004; > + } else { > + msr.hi |= 0x082710055; > + msr.lo |= 0x056960004; > + } > + } else if (spdbyte0 > 4) { > + /* medium dimm */ > + if (glspeed < 334) { > + msr.hi |= 0x0837100AA; > + msr.lo |= 0x056960004; > + } else { > + msr.hi |= 0x0827100AA; > + msr.lo |= 0x056960004; > + } > + } else { > + /* small dimm */ > + if (glspeed < 334) { > + msr.hi |= 0x0837100FF; > + msr.lo |= 0x056960004; > + } else { > + msr.hi |= 0x0827100FF; > + msr.lo |= 0x056960004; > + } > + } > + } else { > + /* two dimm solution */ > + spdbyte0 += spdbyte1; > + if (spdbyte0 > 24) { > + /* huge dimms */ > + if (glspeed < 334) { > + msr.hi |= 0x0B37100A5; > + msr.lo |= 0x056960004; > + } else { > + msr.hi |= 0x0B2710000; > + msr.lo |= 0x056960004; > + } > + } else if (spdbyte0 > 16) { > + /* large dimms */ > + if (glspeed < 334) { > + msr.hi |= 0x0B37100A5; > + msr.lo |= 0x056960004; > + } else { > + msr.hi |= 0x0B27100A5; > + msr.lo |= 0x056960004; > + } > + } else if (spdbyte0 >= 8) { > + /* medium dimms */ > + if (glspeed < 334) { > + msr.hi |= 0x0937100A5; > + msr.lo |= 0x056960004; > + } else { > + msr.hi |= 0x0C27100A5; > + msr.lo |= 0x056960004; > + } > + } else { > + /* small dimms */ > + if (glspeed < 334) { > + msr.hi |= 0x0837100A5; > + msr.lo |= 0x056960004; > + } else { > + msr.hi |= 0x082710000; > + msr.lo |= 0x056960004; > + } > + } Each if statements just changes a few bits. Couldn't this be made more readable? > +DCacheSetupBad: > + hlt /* Issues */ > + jmp DCacheSetupBad Hehe, yes, we have issues. Should we aim for panic room code in assembly? > +lout: > + /* Restore the BIST result. */ > + movl %ebp, %eax > + /* We need to set ebp? No need. */ > + movl %esp, %ebp > + pushl %eax /* BIST */ > + call stage1_main > + /* We will not go back. */ I remember commenting on this before; please handle a return or change it to a jmp. (I like the latter.) > +fixed_mtrr_msr: > + .long 0x250, 0x258, 0x259 > + .long 0x268, 0x269, 0x26A > + .long 0x26B, 0x26C, 0x26D > + .long 0x26E, 0x26F > +var_mtrr_msr: > + .long 0x200, 0x201, 0x202, 0x203 > + .long 0x204, 0x205, 0x206, 0x207 ..or this would be executed on return.. //Peter

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[LinuxBIOS] [PATCH][v3] small fix for nrv2b
by Patrick Georgi 03 Jul '07

03 Jul '07

Hi, this is actually a brown paper bag patch, as my last patch managed to break the build of nrv2b. It's basically some reordering and an additional preprocessor define on the command line. I'm sorry that this issue slipped through (I didn't notice that my build didn't cover nrv2b anymore) Regards, Patrick Georgi Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Index: util/nrv2b/nrv2b.c =================================================================== --- util/nrv2b/nrv2b.c (revision 367) +++ util/nrv2b/nrv2b.c (working copy) @@ -1309,9 +1309,47 @@ out = malloc(*out_len); ucl_nrv2b_99_compress(in, in_len, out, out_len, 0 ); } +#endif +#ifdef DECODE + +#define GETBIT_8(bb, src, ilen) \ + (((bb = bb & 0x7f ? bb*2 : ((unsigned)src[ilen++]*2+1)) >> 8) & 1) + +#define GETBIT_LE16(bb, src, ilen) \ + (bb*=2,bb&0xffff ? (bb>>16)&1 : (ilen+=2,((bb=(src[ilen-2]+src[ilen-1]*256u)*2+1)>>16)&1)) + +#define GETBIT_LE32(bb, src, ilen) \ + (bc > 0 ? ((bb>>--bc)&1) : (bc=31,\ + bb=*(const uint32_t *)((src)+ilen),ilen+=4,(bb>>31)&1)) + +#if ENDIAN == 0 && BITSIZE == 8 +#define GETBIT(bb, src, ilen) GETBIT_8(bb, src, ilen) +#endif +#if ENDIAN == 0 && BITSIZE == 16 +#define GETBIT(bb, src, ilen) GETBIT_LE16(bb, src, ilen) +#endif +#if ENDIAN == 0 && BITSIZE == 32 +#define GETBIT(bb, src, ilen) GETBIT_LE32(bb, src, ilen) +#endif + +#ifndef GETBIT +#error "Bad Combination of ENDIAN and BITSIZE values specified" +#endif + +#undef SAFE + +#ifdef SAFE +#define FAIL(x,r) if (x) { Error(r); } +#else +#define FAIL(x,r) +#endif + +#ifdef COMPACT void do_nrv2b_uncompress(char* dst, char* src, unsigned long len) { unsigned long ilen = 0, olen = 0, last_m_off = 1; + uint32_t bb = 0; + unsigned bc = 0; for (;;) { unsigned int m_off, m_len; while (GETBIT(bb, src, ilen)) { @@ -1359,42 +1397,7 @@ } FAIL(ilen < src_len, "input not consumed"); } -#endif - -#ifdef DECODE - -#define GETBIT_8(bb, src, ilen) \ - (((bb = bb & 0x7f ? bb*2 : ((unsigned)src[ilen++]*2+1)) >> 8) & 1) - -#define GETBIT_LE16(bb, src, ilen) \ - (bb*=2,bb&0xffff ? (bb>>16)&1 : (ilen+=2,((bb=(src[ilen-2]+src[ilen-1]*256u)*2+1)>>16)&1)) - -#define GETBIT_LE32(bb, src, ilen) \ - (bc > 0 ? ((bb>>--bc)&1) : (bc=31,\ - bb=*(const uint32_t *)((src)+ilen),ilen+=4,(bb>>31)&1)) - -#if ENDIAN == 0 && BITSIZE == 8 -#define GETBIT(bb, src, ilen) GETBIT_8(bb, src, ilen) -#endif -#if ENDIAN == 0 && BITSIZE == 16 -#define GETBIT(bb, src, ilen) GETBIT_LE16(bb, src, ilen) -#endif -#if ENDIAN == 0 && BITSIZE == 32 -#define GETBIT(bb, src, ilen) GETBIT_LE32(bb, src, ilen) -#endif - -#ifndef GETBIT -#error "Bad Combination of ENDIAN and BITSIZE values specified" -#endif - -#undef SAFE - -#ifdef SAFE -#define FAIL(x,r) if (x) { Error(r); } #else -#define FAIL(x,r) -#endif - void Decode(void) /* recover */ { uint32_t tw; @@ -1494,6 +1497,7 @@ free(dst); } #endif +#endif #ifdef MAIN int main(int argc, char *argv[]) Index: util/nrv2b/Makefile =================================================================== --- util/nrv2b/Makefile (revision 367) +++ util/nrv2b/Makefile (working copy) @@ -25,7 +25,7 @@ $(obj)/util/nrv2b/nrv2b-compress.o: nrv2bdir $(src)/util/nrv2b/nrv2b.c $(Q)printf " HOSTCC $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(HOSTCC) $(HOSTCFLAGS) -DENCODE -DVERBOSE -DCOMPACT -DNDEBUG -DBITSIZE=32 -DENDIAN=0 -c -o $@ $(src)/util/nrv2b/nrv2b.c + $(Q)$(HOSTCC) $(HOSTCFLAGS) -DENCODE -DDECODE -DVERBOSE -DCOMPACT -DNDEBUG -DBITSIZE=32 -DENDIAN=0 -c -o $@ $(src)/util/nrv2b/nrv2b.c nrv2bdir: $(Q)printf " BUILD NRV2B\n"

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Re: [LinuxBIOS] r413 - in LinuxBIOSv3: arch/x86 include mainboard/artecgroup/dbe61 southbridge/amd/cs5536 superio/winbond/w83627hf
by Peter Stuge 03 Jul '07

03 Jul '07

On Fri, Jun 29, 2007 at 04:36:03PM +0200, svn(a)openbios.org wrote: > +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) Need extra () around a or no? sizeof((a)) / sizeof(((a))[0])) ? //Peter

2 1

[LinuxBIOS] [PATCH] v3 - spinlock cleanup
by Stefan Reinauer 03 Jul '07

03 Jul '07

* fix copyright headers to v2 only as suggested by Uwe * drop silly code when not using SMP * fix device/device.c * drop spinlock_t, use struct spinlock instead. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Index: include/spinlock.h =================================================================== --- include/spinlock.h (revision 427) +++ include/spinlock.h (working copy) @@ -2,11 +2,11 @@ * This file is part of the LinuxBIOS project. * * Copyright (C) 2001 Linux Networx + * Copyright (C) 2007 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -22,23 +22,17 @@ #define SPINLOCK_H #if defined(CONFIG_SMP) && CONFIG_SMP == 1 + #include <arch/spinlock.h> + #else /* !CONFIG_SMP */ -/* Most GCC versions have a nasty bug with empty initializers */ -#if (__GNUC__ > 2) -typedef struct { } spinlock_t; -#define SPIN_LOCK_UNLOCKED (spinlock_t) { } -#else -typedef struct { int gcc_is_buggy; } spinlock_t; -#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 } -#endif - #define barrier() do {} while(0) #define spin_is_locked(lock) 0 #define spin_unlock_wait(lock) do {} while(0) #define spin_lock(lock) do {} while(0) #define spin_unlock(lock) do {} while(0) +#define spin_define(lock) /* empty */ #endif #endif /* SPINLOCK_H */ Index: include/arch/x86/arch/spinlock.h =================================================================== --- include/arch/x86/arch/spinlock.h (revision 427) +++ include/arch/x86/arch/spinlock.h (working copy) @@ -2,11 +2,11 @@ * This file is part of the LinuxBIOS project. * * Copyright (C) 2001 Linux Networx + * Copyright (C) 2007 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -25,12 +25,12 @@ * Your basic SMP spinlocks, allowing only a single CPU anywhere */ -typedef struct { +struct spinlock { volatile unsigned int lock; -} spinlock_t; +}; -#define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 } +#define SPIN_LOCK_UNLOCKED (struct spinlock) { 1 } /* * Simple spin lock operations. There are two variants, one clears IRQ's @@ -60,18 +60,21 @@ #define spin_unlock_string \ "movb $1,%0" -static inline __attribute__((always_inline)) void spin_lock(spinlock_t *lock) +static inline __attribute__((always_inline)) void spin_lock(struct spinlock *lock) { __asm__ __volatile__( spin_lock_string :"=m" (lock->lock) : : "memory"); } -static inline __attribute__((always_inline)) void spin_unlock(spinlock_t *lock) +static inline __attribute__((always_inline)) void spin_unlock(struct spinlock *lock) { __asm__ __volatile__( spin_unlock_string :"=m" (lock->lock) : : "memory"); } +#define spin_define(spin) static struct spinlock spin = SPIN_LOCK_UNLOCKED + + #endif /* ARCH_SPINLOCK_H */ Index: device/device.c =================================================================== --- device/device.c (revision 427) +++ device/device.c (working copy) @@ -183,7 +183,9 @@ * @return Pointer to the newly created device structure. * @see device_path */ -// static spinlock_t dev_lock = SPIN_LOCK_UNLOCKED; + +spin_define(dev_lock); + struct device *alloc_dev(struct bus *parent, struct device_path *path, struct device_id *devid) { -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

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[LinuxBIOS] [PATCH] v3 - put lar size in the bootblock
by Stefan Reinauer 03 Jul '07

03 Jul '07

Hi, this patch puts the lar size in the bootblock and reads it from there. Why? This way we don't need to recompile the image when the size of the LinuxBIOS image changes. This alows building images for 50 motherboards and equipping each with 10 payloads, resulting in 500 images while you only have to build each payload once and each motherboard, too. There's also a small "fix" allowing the compression type to be case insensitive. Not really relevant I guess. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Index: util/lar/bootblock.c =================================================================== --- util/lar/bootblock.c (revision 426) +++ util/lar/bootblock.c (working copy) @@ -74,16 +74,16 @@ int fixup_bootblock(void) { - /* Per definition the bootblock starts with 256 empty bytes. - * These are utilized to make the bootblock part of a lar file, - * and store the image size. - * - * We will also calculate a checksum here. - */ + int i; + uint32_t *size_pos; - /* first try. Clear out ugly left-over from ld hack */ - bootblock_code[bootblock_len - 13] = '\0'; - bootblock_code[bootblock_len - 12] = '\0'; + /* This cleans out the area after the reset vector */ + for(i=13; i>0; i--) + bootblock_code[bootblock_len - i] = '\0'; + + /* add lar size to image */ + size_pos=(uint32_t *)(bootblock_code+bootblock_len-12); + size_pos[0] = get_larsize(); return 0; } Index: util/lar/lar.c =================================================================== --- util/lar/lar.c (revision 426) +++ util/lar/lar.c (working copy) @@ -96,10 +96,10 @@ larmode = CREATE; break; case 'C': - if (strcmp("lzma", optarg) == 0) { + if (strcasecmp("lzma", optarg) == 0) { algo = lzma; } - if (strcmp("nrv2b", optarg) == 0) { + if (strcasecmp("nrv2b", optarg) == 0) { algo = nrv2b; } break; Index: arch/x86/stage1.c =================================================================== --- arch/x86/stage1.c (revision 426) +++ arch/x86/stage1.c (working copy) @@ -101,8 +101,12 @@ // FIXME this should be defined in the VPD area // but NOT IN THE CODE. - archive.len=(CONFIG_LINUXBIOS_ROMSIZE_KB)*1024; - archive.start=(void *)(0UL-(CONFIG_LINUXBIOS_ROMSIZE_KB*1024)); + /* The len field starts behind the reset vector on x86. + * The start is not correct for all platforms. sc520 will + * need some hands on here. + */ + archive.len = *(u32 *)0xfffffff4; + archive.start =(void *)(0UL-archive.len); // FIXME check integrity -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/

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coreboot July 2007