coreboot July 2007

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[LinuxBIOS] r433 - in LinuxBIOSv3: arch/x86 arch/x86/geodelx include/arch/x86
by svn＠openbios.org 05 Jul '07

05 Jul '07

Author: mjones Date: 2007-07-05 18:58:10 +0200 (Thu, 05 Jul 2007) New Revision: 433 Added: LinuxBIOSv3/include/arch/x86/legacy.h Modified: LinuxBIOSv3/arch/x86/geodelx/geodelx.c LinuxBIOSv3/arch/x86/speaker.c Log: Moved some generic 8254 PIT #defines out of the speaker code to legacy.h. Use legacy.h PIT defines in Geode code. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: LinuxBIOSv3/arch/x86/geodelx/geodelx.c =================================================================== --- LinuxBIOSv3/arch/x86/geodelx/geodelx.c 2007-07-03 20:33:33 UTC (rev 432) +++ LinuxBIOSv3/arch/x86/geodelx/geodelx.c 2007-07-05 16:58:10 UTC (rev 433) @@ -30,6 +30,7 @@ #include <io.h> #include <amd_geodelx.h> #include <spd.h> +#include <legacy.h> /* all these functions used to be in a lot of fiddly little files. To * make it easier to find functions, we are merging them here. This @@ -41,8 +42,6 @@ /** * Starts Timer 1 for port 61 use. - * 0x43 is PIT command/control. - * 0x41 is PIT counter 1. * * The command 0x56 means write counter 1 lower 8 bits in next IO, * set the counter mode to square wave generator (count down to 0 @@ -58,8 +57,8 @@ */ void start_timer1(void) { - outb(0x56, 0x43); - outb(0x12, 0x41); + outb(0x56, I82C54_CONTROL_WORD_REGISTER); + outb(0x12, I82C54_COUNTER1); } /** Modified: LinuxBIOSv3/arch/x86/speaker.c =================================================================== --- LinuxBIOSv3/arch/x86/speaker.c 2007-07-03 20:33:33 UTC (rev 432) +++ LinuxBIOSv3/arch/x86/speaker.c 2007-07-05 16:58:10 UTC (rev 433) @@ -27,13 +27,8 @@ #include <io.h> #include <lib.h> +#include <legacy.h> -#define I82C54_CONTROL_WORD_REGISTER 0x43 /* Write-only. */ - -#define I82C54_COUNTER0 0x40 -#define I82C54_COUNTER1 0x41 -#define I82C54_COUNTER2 0x42 - #define PC_SPEAKER_PORT 0x61 /** Added: LinuxBIOSv3/include/arch/x86/legacy.h =================================================================== --- LinuxBIOSv3/include/arch/x86/legacy.h (rev 0) +++ LinuxBIOSv3/include/arch/x86/legacy.h 2007-07-05 16:58:10 UTC (rev 433) @@ -0,0 +1,34 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Datasheet: + * - Name: 82C54 CHMOS Programmable Interval Timer + * - PDF: http://www.intel.com/design/archives/periphrl/docs/23124406.pdf + * - Order number: 231244-006 + * + * See also: + * - http://en.wikipedia.org/wiki/Intel_8253 + */ + +#define I82C54_CONTROL_WORD_REGISTER 0x43 /* Write-only. */ +#define I82C54_COUNTER0 0x40 +#define I82C54_COUNTER1 0x41 +#define I82C54_COUNTER2 0x42

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[LinuxBIOS] Machine check panic.
by Feng, Libo 05 Jul '07

05 Jul '07

Hi, all, The system I am using is: Tyan 3992, AMD Athlon64, Redhat enterprise version 4. LinuxBios is based on MSI ms9185. I encountered a Machine check panic. Who can interpret the below information. I think ADDR is a Mci_ADDR register, but what is TSC. Furthermore, I think Athlon64 should have 5 error-reporting banks, there is only 3 showing, maybe the serial port missed something, but what means 4 Bank, and what is the last long number? The attached is the whole log file. The system hung, what should I do next? Thank you. Loading dm-zero.ko module Loadi CPU 0: Machine Check Exception: 4 Bank 0: 947a400000000833 TSC 45a20e904a ADDR 3fb07340 CPU 0: Machine Check Exception: 4 Bank 1: b600200000000853 TSC 45a20e957c ADDR 1d3480 CPU 0: Machine Check Exception: 4 Bank 2: d000400000000863 TSC 45a20e970a Kernel panic - not syncing: Machine check ng dm-snapshot.ko module <<TyanLB05.txt>> Best Regards 丰立波 Feng Libo @ AMD Ext: 20906 Mobile Phone: 13683249071 Office Phone: 0086-010-62801406

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[LinuxBIOS] MS-6391 and intel 845
by polytan 05 Jul '07

05 Jul '07

Hi, I've got a motherboard with a plcc socket and a flashrom not soldered on it. So I'm going to by a bigger memory and put a LinuxBios on it but...is this software supported ? It's a quite old motherboard (it's for 1.3 - 2GHz P4 processors). Amitiés, -- -=( Polytan )=-

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[LinuxBIOS] r2732 build service
by LinuxBIOS information 04 Jul '07

04 Jul '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "" checked in revision 2732 to the LinuxBIOS source repository and caused the following changes: Change Log: Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2732&device=hdama&vendor=… Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2732&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2732&device=e326&vendor=i… Compilation of iei:juki-511p is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2732&device=juki-511p&ven… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2732&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2732&device=dk8x&vendor=i… If something broke during this checkin please be a pain in 's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

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[LinuxBIOS] [patch] flashrom: add support for tyan tomcat k7m.
by Luc Verhaegen 04 Jul '07

04 Jul '07

Luc Verhaegen.

2 1

[LinuxBIOS] r2732 - trunk/util/flashrom
by svn＠openbios.org 04 Jul '07

04 Jul '07

Author: uwe Date: 2007-07-04 19:51:49 +0200 (Wed, 04 Jul 2007) New Revision: 2732 Modified: trunk/util/flashrom/board_enable.c Log: Flashrom: Add support for Tyan Tomcat K7M. Same board enable as Asus A7V8-MX. Tested by Reinhard Max. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/flashrom/board_enable.c =================================================================== --- trunk/util/flashrom/board_enable.c 2007-07-01 19:47:31 UTC (rev 2731) +++ trunk/util/flashrom/board_enable.c 2007-07-04 17:51:49 UTC (rev 2732) @@ -138,8 +138,9 @@ } /* - * Suited for ASUS A7V8X-MX SE and A7V400-MX. - * + * Suited for: + * ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235 + * Tyan Tomcat K7M: AMD Geode NX + VIA KM400 + VT8237. */ static int board_asus_a7v8x_mx(const char *name) @@ -148,8 +149,10 @@ uint8_t val; dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */ + if (!dev) + dev = pci_dev_find(0x1106, 0x3227); /* VT8237 ISA bridge */ if (!dev) { - fprintf(stderr, "\nERROR: VT8235 ISA Bridge not found.\n"); + fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n"); return -1; } @@ -300,6 +303,8 @@ NULL, NULL, "VIA EPIA M/MII/...", board_via_epia_m}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS A7V8-MX SE", board_asus_a7v8x_mx}, + {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, + NULL, NULL, "Tyan Tomcat K7M", board_asus_a7v8x_mx}, {0x10B9, 0x1541, 0x0000, 0x0000, 0x10B9, 0x1533, 0x0000, 0x0000, "asus", "p5a", "ASUS P5A", board_asus_p5a}, {0x1166, 0x0205, 0x1014, 0x0347, 0x0000, 0x0000, 0x0000, 0x0000,

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[LinuxBIOS] [PATCH] v3: 8254_pit.patch
by Marc Jones 04 Jul '07

04 Jul '07

I think that I put the 8254_pit.h in the correct place. LinuxBIOSv3\include\arch\x86\8254_pit.h Marc -- Marc Jones Senior Software Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Moved some generic 8254 PIT #defines out of the speaker code to a seperate .h. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Index: LinuxBIOSv3/arch/x86/geodelx/geodelx.c =================================================================== --- LinuxBIOSv3.orig/arch/x86/geodelx/geodelx.c 2007-07-02 10:23:52.000000000 -0600 +++ LinuxBIOSv3/arch/x86/geodelx/geodelx.c 2007-07-03 09:37:11.000000000 -0600 @@ -30,6 +30,7 @@ #include <io.h> #include <amd_geodelx.h> #include <spd.h> +#include <8254_pit.h> /* all these functions used to be in a lot of fiddly little files. To * make it easier to find functions, we are merging them here. This @@ -41,8 +42,6 @@ /** * Starts Timer 1 for port 61 use. - * 0x43 is PIT command/control. - * 0x41 is PIT counter 1. * * The command 0x56 means write counter 1 lower 8 bits in next IO, * set the counter mode to square wave generator (count down to 0 @@ -58,8 +57,8 @@ */ void start_timer1(void) { - outb(0x56, 0x43); - outb(0x12, 0x41); + outb(0x56, I82C54_CONTROL_WORD_REGISTER); + outb(0x12, I82C54_COUNTER1); } /** Index: LinuxBIOSv3/arch/x86/speaker.c =================================================================== --- LinuxBIOSv3.orig/arch/x86/speaker.c 2007-07-02 10:23:37.000000000 -0600 +++ LinuxBIOSv3/arch/x86/speaker.c 2007-07-03 09:34:08.000000000 -0600 @@ -2,6 +2,7 @@ * This file is part of the LinuxBIOS project. * * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,23 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* - * Datasheet: - * - Name: 82C54 CHMOS Programmable Interval Timer - * - PDF: http://www.intel.com/design/archives/periphrl/docs/23124406.pdf - * - Order number: 231244-006 - */ - #include <io.h> #include <lib.h> - -#define I82C54_CONTROL_WORD_REGISTER 0x43 /* Write-only. */ - -#define I82C54_COUNTER0 0x40 -#define I82C54_COUNTER1 0x41 -#define I82C54_COUNTER2 0x42 - -#define PC_SPEAKER_PORT 0x61 +#include <8254_pit.h> /** * Use the PC speaker to create a tone/sound of the specified frequency. Index: LinuxBIOSv3/include/arch/x86/8254_pit.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ LinuxBIOSv3/include/arch/x86/8254_pit.h 2007-07-03 09:34:04.000000000 -0600 @@ -0,0 +1,36 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Datasheet: + * - Name: 82C54 CHMOS Programmable Interval Timer + * - PDF: http://www.intel.com/design/archives/periphrl/docs/23124406.pdf + * - Order number: 231244-006 + * + * See also: + * - http://en.wikipedia.org/wiki/Intel_8253 + */ + +#define I82C54_CONTROL_WORD_REGISTER 0x43 /* Write-only. */ +#define I82C54_COUNTER0 0x40 +#define I82C54_COUNTER1 0x41 +#define I82C54_COUNTER2 0x42 +#define PC_SPEAKER_PORT 0x61

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Re: [LinuxBIOS] r2731 - trunk/LinuxBIOSv2/util
by Peter Stuge 04 Jul '07

04 Jul '07

On Sun, Jul 01, 2007 at 09:47:31PM +0200, svn(a)openbios.org wrote: > Name: svn:externals > + flashrom svn://linuxbios.org/repos/trunk/util/flashrom Do we want a completely new repo for utils? //Peter

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[LinuxBIOS] [Re: [PATCH] geode_v3_cleanup.patch - Re: r387 - in LinuxBIOSv3/arch/x86: . geodelx]
by Marc Jones 03 Jul '07

03 Jul '07

2 3

[LinuxBIOS] r432 - in LinuxBIOSv3: arch/x86/geodelx include/arch/x86
by svn＠openbios.org 03 Jul '07

03 Jul '07

Author: mjones Date: 2007-07-03 22:33:33 +0200 (Tue, 03 Jul 2007) New Revision: 432 Modified: LinuxBIOSv3/arch/x86/geodelx/geodelx.c LinuxBIOSv3/arch/x86/geodelx/stage1.c LinuxBIOSv3/include/arch/x86/amd_geodelx.h Log: Clean up comments and #defines in Geode LX code. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: LinuxBIOSv3/arch/x86/geodelx/geodelx.c =================================================================== --- LinuxBIOSv3/arch/x86/geodelx/geodelx.c 2007-07-03 16:58:16 UTC (rev 431) +++ LinuxBIOSv3/arch/x86/geodelx/geodelx.c 2007-07-03 20:33:33 UTC (rev 432) @@ -40,8 +40,21 @@ */ /** - * start_time1 Starts Timer 1 for port 61 use. FIXME try to figure - * out what these values mean. + * Starts Timer 1 for port 61 use. + * 0x43 is PIT command/control. + * 0x41 is PIT counter 1. + * + * The command 0x56 means write counter 1 lower 8 bits in next IO, + * set the counter mode to square wave generator (count down to 0 + * from programmed value twice in a row, alternating the output signal) + * counting in 16-bit binary mode. + * + * 0x12 is counter/timer 1 and signals the PIT to do a RAM refresh + * approximately every 15us. + * + * The PIT typically is generating 1.19318 MHz + * Timer 1 was used for RAM refresh on XT/AT and can be read on port61. + * Port61 is used by many timing loops for calibration. */ void start_timer1(void) { @@ -134,42 +147,44 @@ */ void pll_reset(int manualconf, u32 pll_hi, u32 pll_lo) { - struct msr msrGlcpSysRstpll; + struct msr msr_glcp_sys_pll; /* GeodeLink PLL control MSR */ - msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL); + msr_glcp_sys_pll = rdmsr(GLCP_SYS_RSTPLL); printk(BIOS_DEBUG, - "_MSR GLCP_SYS_RSTPLL (%08x) value is: %08x:%08x\n", msrGlcpSysRstpll.hi, msrGlcpSysRstpll.lo); + "_MSR GLCP_SYS_RSTPLL (%08x) value is: %08x:%08x\n", msr_glcp_sys_pll.hi, msr_glcp_sys_pll.lo); post_code(POST_PLL_INIT); - if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) { + if (!(msr_glcp_sys_pll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) { printk(BIOS_DEBUG,"Configuring PLL\n"); if (manualconf) { post_code(POST_PLL_MANUAL); /* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */ - msrGlcpSysRstpll.hi = pll_hi; + msr_glcp_sys_pll.hi = pll_hi; /* Hold Count - how long we will sit in reset */ - msrGlcpSysRstpll.lo = pll_lo; + msr_glcp_sys_pll.lo = pll_lo; } else { /*automatic configuration (straps) */ post_code(POST_PLL_STRAP); - msrGlcpSysRstpll.lo &= + /* Hold 0xDE * 16 clocks during reset. */ + /* AMD recomended value for PLL reset from silicon validation. */ + msr_glcp_sys_pll.lo &= ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT); - msrGlcpSysRstpll.lo |= + msr_glcp_sys_pll.lo |= (0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT); - msrGlcpSysRstpll.lo &= + msr_glcp_sys_pll.lo &= ~(RSTPPL_LOWER_COREBYPASS_SET | RSTPPL_LOWER_MBBYPASS_SET); - msrGlcpSysRstpll.lo |= + msr_glcp_sys_pll.lo |= RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET; } /* Use SWFLAGS to remember: "we've already been here" */ - msrGlcpSysRstpll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT); + msr_glcp_sys_pll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT); /* "reset the chip" value */ - msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET; - wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll); + msr_glcp_sys_pll.lo |= RSTPPL_LOWER_CHIP_RESET_SET; + wrmsr(GLCP_SYS_RSTPLL, msr_glcp_sys_pll); /* You should never get here..... The chip has reset. */ printk(BIOS_EMERG,"CONFIGURING PLL FAILURE -- HALT\n"); @@ -183,9 +198,8 @@ /** - * Return the CPU clock rate. Rates in this system are always returned - * as multkiples of 33 Mhz. - * + * Return the CPU clock rate from the PLL MSR. + * @return CPU speed in MHz */ u32 cpu_speed(void) { @@ -193,17 +207,16 @@ struct msr msr; msr = rdmsr(GLCP_SYS_RSTPLL); - speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) / 10; - if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) { + speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & RSTPLL_UPPER_CPUMULT_MASK) + 1) * 333) / 10; + if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & RSTPLL_UPPER_CPUMULT_MASK) + 1) * 333) % 10) > 5) { ++speed; } return (speed); } /** - * Return the Geode Link clock rate. Rates in this system are always - * returned as multkiples of 33 Mhz. - * + * Return the GeodeLink clock rate from the PLL MSR. + * @return GeodeLink speed in MHz */ u32 geode_link_speed(void) { @@ -211,8 +224,8 @@ struct msr msr; msr = rdmsr(GLCP_SYS_RSTPLL); - speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) / 10; - if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) { + speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & RSTPLL_UPPER_GLMULT_MASK) + 1) * 333) / 10; + if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & RSTPLL_UPPER_GLMULT_MASK) + 1) * 333) % 10) > 5) { ++speed; } return (speed); @@ -220,9 +233,8 @@ /** - * Return the PCI bus clock rate. Rates in this system are always - * returned as multkiples of 33 Mhz. - * + * Return the PCI bus clock rate from the PLL MSR. + * @return PCI speed in MHz */ u32 pci_speed(void) { @@ -295,7 +307,7 @@ */ msrnum = GLCP_DELAY_CONTROLS; msr = rdmsr(msrnum); - if (msr.lo & ~(0x7C0)) { + if (msr.lo & ~(DELAY_LOWER_STATUS_MASK)) { return; } Modified: LinuxBIOSv3/arch/x86/geodelx/stage1.c =================================================================== --- LinuxBIOSv3/arch/x86/geodelx/stage1.c 2007-07-03 16:58:16 UTC (rev 431) +++ LinuxBIOSv3/arch/x86/geodelx/stage1.c 2007-07-03 20:33:33 UTC (rev 432) @@ -50,22 +50,23 @@ wrmsr(CPU_RCONF_C0_DF, msr); wrmsr(CPU_RCONF_E0_FF, msr); - /* Setup access to the cache for under 640K. Note MC not setup yet. */ + /* Setup access to the cache for under 640K. */ + /* Note memory controler not setup yet. */ msr.hi = 0x20000000; - msr.lo = 0xfff80; - wrmsr(MSR_GLIU0 + 0x20, msr); + msr.lo = 0x000fff80; /* 0-0x7FFFF */ + wrmsr(MSR_GLIU0_BASE1, msr); msr.hi = 0x20000000; - msr.lo = 0x80fffe0; - wrmsr(MSR_GLIU0 + 0x21, msr); + msr.lo = 0x080fffe0; /* 0x80000-0x9FFFF */ + wrmsr(MSR_GLIU0_BASE2, msr); msr.hi = 0x20000000; - msr.lo = 0xfff80; - wrmsr(MSR_GLIU1 + 0x20, msr); + msr.lo = 0x000fff80; /* 0-0x7FFFF */ + wrmsr(MSR_GLIU1_BASE1, msr); msr.hi = 0x20000000; - msr.lo = 0x80fffe0; - wrmsr(MSR_GLIU1 + 0x21, msr); + msr.lo = 0x080fffe0; /* 0x80000-0x9FFFF */ + wrmsr(MSR_GLIU0_BASE2, msr); } Modified: LinuxBIOSv3/include/arch/x86/amd_geodelx.h =================================================================== --- LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2007-07-03 16:58:16 UTC (rev 431) +++ LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2007-07-03 20:33:33 UTC (rev 432) @@ -354,10 +354,13 @@ #define GLCP_GLD_MSR_ERROR (MSR_GLCP + 0x2003) #define GLCP_GLD_MSR_PM (MSR_GLCP + 0x2004) #define GLCP_DELAY_CONTROLS (MSR_GLCP + 0x0F) +#define DELAY_LOWER_STATUS_MASK 0x7C0 #define GLCP_SYS_RSTPLL (MSR_GLCP + 0x14) /* R/W */ #define RSTPLL_UPPER_GLMULT_SHIFT 7 +#define RSTPLL_UPPER_GLMULT_MASK 0x1F #define RSTPLL_UPPER_GLDIV_SHIFT 6 #define RSTPLL_UPPER_CPUMULT_SHIFT 1 +#define RSTPLL_UPPER_CPUMULT_MASK 0x1F #define RSTPLL_UPPER_CPUDIV_SHIFT 0 #define RSTPLL_LOWER_SWFLAGS_SHIFT 26 #define RSTPLL_LOWER_SWFLAGS_MASK (0x03F << RSTPLL_LOWER_SWFLAGS_SHIFT)

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coreboot July 2007