coreboot July 2007

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[LinuxBIOS] r437 - in LinuxBIOSv3: device include/device
by svn＠openbios.org 07 Jul '07

07 Jul '07

Author: uwe Date: 2007-07-07 21:19:44 +0200 (Sat, 07 Jul 2007) New Revision: 437 Modified: LinuxBIOSv3/device/device.c LinuxBIOSv3/device/device_util.c LinuxBIOSv3/include/device/device.h Log: Drop the round() function, as it is an exact copy of align_up(). Also, make align_up()/align_down() non-static as they are useful even outside of device/device_util.c. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: … [View More]LinuxBIOSv3/device/device.c =================================================================== --- LinuxBIOSv3/device/device.c 2007-07-07 09:34:56 UTC (rev 436) +++ LinuxBIOSv3/device/device.c 2007-07-07 19:19:44 UTC (rev 437) @@ -244,22 +244,6 @@ } /** - * Round a number up to an alignment. - * - * @param val The starting value. - * @param roundup Alignment as a power of two. - * @returns Rounded up number. - */ -static resource_t round(resource_t val, unsigned long pow) -{ - resource_t mask; - mask = (1ULL << pow) - 1ULL; - val += mask; - val &= ~mask; - return val; -} - -/** * Read the resources on all devices of a given bus. * * @param bus Bus to read the resources on. @@ -492,9 +476,9 @@ base = 0x3e0; } } - if (((round(base, align) + size) - 1) <= resource->limit) { + if (((align_up(base, align) + size) - 1) <= resource->limit) { /* Base must be aligned to size. */ - base = round(base, align); + base = align_up(base, align); resource->base = base; resource->flags |= IORESOURCE_ASSIGNED; resource->flags &= ~IORESOURCE_STORED; @@ -517,7 +501,7 @@ * minimum granularity so we know not to place something else at an * address positively decoded by the bridge. */ - bridge->size = round(base, bridge->gran) - bridge->base; + bridge->size = align_up(base, bridge->gran) - bridge->base; printk(BIOS_SPEW, "%s compute_allocate_%s: base: %08Lx size: %08Lx align: %d gran: %d done\n", dev_path(bus->dev), (bridge->flags & IORESOURCE_IO) ? "io" : (bridge->flags & IORESOURCE_PREFETCH) ? "prefmem" : "mem", base, bridge->size, bridge->align, bridge->gran); } Modified: LinuxBIOSv3/device/device_util.c =================================================================== --- LinuxBIOSv3/device/device_util.c 2007-07-07 09:34:56 UTC (rev 436) +++ LinuxBIOSv3/device/device_util.c 2007-07-07 19:19:44 UTC (rev 437) @@ -496,7 +496,7 @@ * @param gran Granularity we are aligning the number to. * @returns The aligned value. */ -static resource_t align_up(resource_t val, unsigned long gran) +resource_t align_up(resource_t val, unsigned long gran) { resource_t mask; mask = (1ULL << gran) - 1ULL; @@ -512,7 +512,7 @@ * @param gran Granularity we are aligning the number to. * @returns The aligned value. */ -static resource_t align_down(resource_t val, unsigned long gran) +resource_t align_down(resource_t val, unsigned long gran) { resource_t mask; mask = (1ULL << gran) - 1ULL; Modified: LinuxBIOSv3/include/device/device.h =================================================================== --- LinuxBIOSv3/include/device/device.h 2007-07-07 09:34:56 UTC (rev 436) +++ LinuxBIOSv3/include/device/device.h 2007-07-07 19:19:44 UTC (rev 437) @@ -257,6 +257,9 @@ #define DEVICE_IO_ALIGN 16 #define DEVICE_MEM_ALIGN 4096 +resource_t align_up(resource_t val, unsigned long gran); +resource_t align_down(resource_t val, unsigned long gran); + extern struct device_operations default_dev_ops_root; extern int id_eq(struct device_id *id1, struct device_id *id2); [View Less]

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[LinuxBIOS] r436 - in LinuxBIOSv3: arch/x86 northbridge/amd/geodelx northbridge/intel/i440bxemulation southbridge/intel/i82371eb superio/winbond/w83627hf
by svn＠openbios.org 07 Jul '07

07 Jul '07

Author: stepan Date: 2007-07-07 11:34:56 +0200 (Sat, 07 Jul 2007) New Revision: 436 Modified: LinuxBIOSv3/arch/x86/Makefile LinuxBIOSv3/northbridge/amd/geodelx/Makefile LinuxBIOSv3/northbridge/intel/i440bxemulation/Makefile LinuxBIOSv3/southbridge/intel/i82371eb/Makefile LinuxBIOSv3/superio/winbond/w83627hf/Makefile Log: trivial: fix some dependencies (for make -j) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.… [View More]de> Modified: LinuxBIOSv3/arch/x86/Makefile =================================================================== --- LinuxBIOSv3/arch/x86/Makefile 2007-07-06 18:03:43 UTC (rev 435) +++ LinuxBIOSv3/arch/x86/Makefile 2007-07-07 09:34:56 UTC (rev 436) @@ -95,7 +95,7 @@ $(patsubst %,$(obj)/arch/x86/%,$(STAGE0_CAR_OBJ)) \ $(STAGE0_MAINBOARD_OBJ) -$(obj)/stage0.init: $(STAGE0_OBJ) +$(obj)/stage0.o $(obj)/stage0.init: $(STAGE0_OBJ) $(Q)# We need to be careful. If stage0.o gets bigger than $(Q)# 0x4000 - 0x100, we will end up with a 4 gig file. $(Q)# I wonder if that behavior is on purpose. Modified: LinuxBIOSv3/northbridge/amd/geodelx/Makefile =================================================================== --- LinuxBIOSv3/northbridge/amd/geodelx/Makefile 2007-07-06 18:03:43 UTC (rev 435) +++ LinuxBIOSv3/northbridge/amd/geodelx/Makefile 2007-07-07 09:34:56 UTC (rev 436) @@ -21,7 +21,7 @@ STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/geodelx/geodelx.o $(obj)/northbridge/amd/geodelx/geodelxinit.o -$(obj)/northbridge/amd/geodelx/%.o: $(src)/northbridge/amd/geodelx/%.c +$(obj)/northbridge/amd/geodelx/%.o: $(src)/northbridge/amd/geodelx/%.c $(obj)/statictree.h $(Q)mkdir -p $(obj)/northbridge/amd/geodelx $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" $(Q)$(CC) $(INITCFLAGS) -c $< -o $@ Modified: LinuxBIOSv3/northbridge/intel/i440bxemulation/Makefile =================================================================== --- LinuxBIOSv3/northbridge/intel/i440bxemulation/Makefile 2007-07-06 18:03:43 UTC (rev 435) +++ LinuxBIOSv3/northbridge/intel/i440bxemulation/Makefile 2007-07-07 09:34:56 UTC (rev 436) @@ -21,7 +21,7 @@ STAGE2_CHIPSET_OBJ += $(obj)/northbridge/intel/i440bxemulation/i440bx.o -$(obj)/northbridge/intel/i440bxemulation/%.o: $(src)/northbridge/intel/i440bxemulation/%.c +$(obj)/northbridge/intel/i440bxemulation/%.o: $(src)/northbridge/intel/i440bxemulation/%.c $(obj)/statictree.h $(Q)mkdir -p $(obj)/northbridge/intel/i440bxemulation $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" $(Q)$(CC) $(INITCFLAGS) -c $< -o $@ Modified: LinuxBIOSv3/southbridge/intel/i82371eb/Makefile =================================================================== --- LinuxBIOSv3/southbridge/intel/i82371eb/Makefile 2007-07-06 18:03:43 UTC (rev 435) +++ LinuxBIOSv3/southbridge/intel/i82371eb/Makefile 2007-07-07 09:34:56 UTC (rev 436) @@ -20,7 +20,7 @@ STAGE2_CHIPSET_OBJ += $(obj)/southbridge/intel/i82371eb/i82371eb.o -$(obj)/southbridge/intel/i82371eb/%.o: $(src)/southbridge/intel/i82371eb/%.c +$(obj)/southbridge/intel/i82371eb/%.o: $(src)/southbridge/intel/i82371eb/%.c $(obj)/statictree.h $(Q)mkdir -p $(obj)/southbridge/intel/i82371eb/ $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" $(Q)$(CC) $(INITCFLAGS) -c $< -o $@ Modified: LinuxBIOSv3/superio/winbond/w83627hf/Makefile =================================================================== --- LinuxBIOSv3/superio/winbond/w83627hf/Makefile 2007-07-06 18:03:43 UTC (rev 435) +++ LinuxBIOSv3/superio/winbond/w83627hf/Makefile 2007-07-07 09:34:56 UTC (rev 436) @@ -22,7 +22,7 @@ # Always add to variables, as there could be more than one Super I/O. STAGE2_CHIPSET_OBJ += $(obj)/superio/winbond/w83627hf/superio.o -$(obj)/superio/winbond/w83627hf/%.o: $(src)/superio/winbond/w83627hf/%.c +$(obj)/superio/winbond/w83627hf/%.o: $(src)/superio/winbond/w83627hf/%.c $(obj)/statictree.h $(Q)mkdir -p $(obj)/superio/winbond/w83627hf/ $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" $(Q)$(CC) $(INITCFLAGS) -c $< -o $@ [View Less]

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[LinuxBIOS] FILO and USB: Out of heap space
by Corey Osgood 07 Jul '07

07 Jul '07

FILO is giving me the error below when using autoboot and attempting to boot from a usb drive. I think this might be due to this board having 4 USB controllers, but I'm not really sure. The board in question is the CN700/VT8237R board, booting the factory BIOS and then booting FILO through grub. USB is enabled in the BIOS, EHCI is disabled, and all USB controllers are enabled (there's no option to disable some, it's all or none). BTW, Peter's FILO IDE speedup patch works great on this board! … [View More]This error occurs with a fresh checkout as well. I'm hoping someone with more USB knowledge than me (which doesn't take much) can tell what's wrong here. Thanks, Corey Error log: boot: uda1:/vmlinuz malloc_diag: alloc: 416 bytes (3 blocks), free: 15960 bytes (1 blocks) malloc_diag: alloc: 432 bytes (4 blocks), free: 15944 bytes (1 blocks) file_open: dev=uda1, path=/vmlinuz LinuxLabs USB bootloader uhc_init: Found UHCI at fffffd00 uhc_reset: Resetting UHCI uhc_init: uhc_init setting framelist to: 1ddaa2d0 uhc_start: Starting UHCI dump_uhci: HCI at fffffd00 uhc_init: Found UHCI at fffffc00 uhc_reset: Resetting UHCI uhc_init: uhc_init setting framelist to: 1ddaa2d0 uhc_start: Starting UHCI dump_uhci: HCI at fffffc00 uhc_init: Found UHCI at fffffb00 uhc_reset: Resetting UHCI uhc_init: uhc_init setting framelist to: 1ddaa2d0 uhc_start: Starting UHCI dump_uhci: HCI at fffffb00 uhc_init: Found UHCI at fffffa00 uhc_reset: Resetting UHCI uhc_init: uhc_init setting framelist to: 1ddaa2d0 uhc_start: Starting UHCI dump_uhci: HCI at fffffa00 malloc_diag: alloc: 8632 bytes (5 blocks), free: 7744 bytes (1 blocks) init_framelist: frame_list is at 12e000 dump_link: frame_list_link: addr: 00121db0 dump_link: frame_list_link: raw addr: 1decc080 dump_link: frame_list_link: terminate: 0 dump_link: frame_list_link: queue: 1 dump_link: frame_list_link: depth: 0 Out of heap space [View Less]

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[LinuxBIOS] Geode delay control setting cleanup
by Marc Jones 06 Jul '07

06 Jul '07

Last week Peter commented that the delay control setting code should be made clearer. Here is what I came up with. I think that it makes more sense now. Marc -- Marc Jones Senior Software Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Rework the Geode delay control setup to table driven and much more readable. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Index: LinuxBIOSv3/arch/x86/geodelx/geodelx.c ==============================… [View More]===================================== --- LinuxBIOSv3.orig/arch/x86/geodelx/geodelx.c 2007-07-03 18:20:19.000000000 -0600 +++ LinuxBIOSv3/arch/x86/geodelx/geodelx.c 2007-07-03 17:40:27.000000000 -0600 @@ -247,6 +247,54 @@ } } + +/** + * Delay Control Settings Table from AMD (MCP 0x4C00000F) + * DIMMs devices Slow (<=333MHz) Fast (>334MHz) + * ----- ------- ---------------------- ---------------------- + * 1 4 0x83*100FF 0x56960004 0x82*100FF 0x56960004 + * 1 8 0x83*100AA 0x56960004 0x82*100AA 0x56960004 + * 1 16 0x83*100AA 0x56960004 0x82*10055 0x56960004 + * + * 2 8 0x837100A5 0x56960004 0x82710000 0x56960004 + * 2 16 0x937100A5 0x56960004 0xC27100A5 0x56960004 + * 2 20 0xB37100A5 0x56960004 0xB27100A5 0x56960004 + * 2 24 0xB37100A5 0x56960004 0xB27100A5 0x56960004 + * 2 32 0xB37100A5 0x56960004 0xB2710000 0x56960004 + * + * ========================================================================= + * - Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM + * in slot 0, but it should be clear for all 2 DIMM settings and if a + * single DIMM is in slot 1. Bits 54:52 should always be set to '111'. + * + * Settings for single DIMM and no VTT termination (Like db800 platform) + * 0xF2F100FF 0x56960004 + * ------------------------------------- + * ADDR/CTL have 22 ohm series R + * DQ/DQM/DQS have 33 ohm series R +*/ + +struct delay_controls { + u8 dimms; + u8 devices; + u32 slow_hi; + u32 slow_low; + u32 fast_hi; + u32 fast_low; +}; + +const struct delay_controls delay_control_table [] = { +/* DIMMs devices Slow (<=333MHz) Fast (>334MHz)*/ +{ 1, 4, 0x0837100FF, 0x056960004, 0x0827100FF, 0x056960004}, +{ 1, 8, 0x0837100AA, 0x056960004, 0x0827100AA, 0x056960004}, +{ 1, 16, 0x0837100AA, 0x056960004, 0x082710055, 0x056960004}, +{ 2, 8, 0x0837100A5, 0x056960004, 0x082710000, 0x056960004}, +{ 2, 16, 0x0937100A5, 0x056960004, 0x0C27100A5, 0x056960004}, +{ 2, 20, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004}, +{ 2, 24, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004}, +{ 2, 32, 0x0B37100A5, 0x056960004, 0x0B2710000, 0x056960004} +}; + /** * set_delay_control. This is Black Magic DRAM timing * juju(http://www.thefreedictionary.com/juju) Dram delay depends on @@ -263,12 +311,10 @@ * @param dimm1 DIMM 1 SMBus address * @param sram_width Data width of the SDRAM */ - void set_delay_control(u8 dimm0, u8 dimm1) { u32 msrnum, glspeed; - u8 spdbyte0, spdbyte1; - int numdimms = 0; + u8 spdbyte0, spdbyte1, dimms, i; struct msr msr; glspeed = geode_link_speed(); @@ -317,7 +363,7 @@ */ spdbyte0 = smbus_read_byte(dimm0, SPD_PRIMARY_SDRAM_WIDTH); if (spdbyte0 != 0xFF) { - numdimms++; + dimms++; spdbyte0 = (unsigned char)64 / spdbyte0 * (unsigned char)(smbus_read_byte(dimm0, SPD_NUM_DIMM_BANKS)); } else { @@ -326,134 +372,32 @@ spdbyte1 = smbus_read_byte(dimm1, SPD_PRIMARY_SDRAM_WIDTH); if (spdbyte1 != 0xFF) { - numdimms++; + dimms++; spdbyte1 = (unsigned char)64 / spdbyte1 * (unsigned char)(smbus_read_byte(dimm1, SPD_NUM_DIMM_BANKS)); } else { spdbyte1 = 0; } -/* The current thinking. Subject to change... - -; "FUTURE ROBUSTNESS" PROPOSAL -; ---------------------------- -; DIMM Max MBUS MC 0x2000001A bits 26:24 -;DIMMs devices Frequency MCP 0x4C00000F Setting vvv -;----- ------- --------- ---------------------- ---------- -;1 4 400MHz 0x82*100FF 0x56960004 4 -;1 8 400MHz 0x82*100AA 0x56960004 4 -;1 16 400MHz 0x82*10055 0x56960004 4 -; -;2 4,4 400MHz 0x82710000 0x56960004 4 -;2 8,8 400MHz 0xC27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE *** -; -;2 16,4 >333 0xB27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE *** -;2 16,8 >333 0xB27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE *** -;2 16,16 >333 0xB2710000 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE *** -; -;1 4 <=333MHz 0x83*100FF 0x56960004 3 -;1 8 <=333MHz 0x83*100AA 0x56960004 3 -;1 16 <=333MHz 0x83*100AA 0x56960004 3 -; -;2 4,4 <=333MHz 0x837100A5 0x56960004 3 -;2 8,8 <=333MHz 0x937100A5 0x56960004 3 -; -;2 16,4 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE *** -;2 16,8 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE *** -;2 16,16 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE *** -;========================================================================= -;* - Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM in slot 0, -; but it should be clear for all 2 DIMM settings and if a single DIMM is in slot 1. -; Bits 54:52 should always be set to '111'. - -;No VTT termination -;------------------------------------- -;ADDR/CTL have 22 ohm series R -;DQ/DQM/DQS have 33 ohm series R -; -; DIMM Max MBUS -;DIMMs devices Frequency MCP 0x4C00000F Setting -;----- ------- --------- ---------------------- -;1 4 400MHz 0xF2F100FF 0x56960004 4 The MC changes improve Salsa. -;1 8 400MHz 0xF2F100FF 0x56960004 4 Delay controls no real change, -;1 4 <=333MHz 0xF2F100FF 0x56960004 3 just fixing typo in left side. -;1 8 <=333MHz 0xF2F100FF 0x56960004 3 -;1 16 <=333MHz 0xF2F100FF 0x56960004 3 -*/ + /* zero GLCP_DELAY_CONTROLS MSR */ msr.hi = msr.lo = 0; - if (spdbyte0 == 0 || spdbyte1 == 0) { - /* one dimm solution */ - if (spdbyte1 == 0) { - msr.hi |= 0x000800000; - } - spdbyte0 += spdbyte1; - if (spdbyte0 > 8) { - /* large dimm */ - if (glspeed < 334) { - msr.hi |= 0x0837100AA; - msr.lo |= 0x056960004; - } else { - msr.hi |= 0x082710055; - msr.lo |= 0x056960004; - } - } else if (spdbyte0 > 4) { - /* medium dimm */ - if (glspeed < 334) { - msr.hi |= 0x0837100AA; - msr.lo |= 0x056960004; - } else { - msr.hi |= 0x0827100AA; - msr.lo |= 0x056960004; - } - } else { - /* small dimm */ - if (glspeed < 334) { - msr.hi |= 0x0837100FF; - msr.lo |= 0x056960004; - } else { - msr.hi |= 0x0827100FF; - msr.lo |= 0x056960004; - } - } - } else { - /* two dimm solution */ - spdbyte0 += spdbyte1; - if (spdbyte0 > 24) { - /* huge dimms */ - if (glspeed < 334) { - msr.hi |= 0x0B37100A5; - msr.lo |= 0x056960004; - } else { - msr.hi |= 0x0B2710000; - msr.lo |= 0x056960004; - } - } else if (spdbyte0 > 16) { - /* large dimms */ - if (glspeed < 334) { - msr.hi |= 0x0B37100A5; - msr.lo |= 0x056960004; - } else { - msr.hi |= 0x0B27100A5; - msr.lo |= 0x056960004; - } - } else if (spdbyte0 >= 8) { - /* medium dimms */ - if (glspeed < 334) { - msr.hi |= 0x0937100A5; - msr.lo |= 0x056960004; - } else { - msr.hi |= 0x0C27100A5; - msr.lo |= 0x056960004; - } - } else { - /* small dimms */ + /* save some power, disable clock to second DIMM if it is empty */ + if (spdbyte1 == 0) { + msr.hi |= 0x000800000; + } + + spdbyte0 += spdbyte1; + + for(i = 0; i < ARRAY_SIZE(delay_control_table); i++){ + if((dimms == delay_control_table[i].dimms) && + (spdbyte0 <= delay_control_table[i].devices)) { if (glspeed < 334) { - msr.hi |= 0x0837100A5; - msr.lo |= 0x056960004; + msr.hi |= delay_control_table[i].slow_hi; + msr.lo |= delay_control_table[i].slow_low; } else { - msr.hi |= 0x082710000; - msr.lo |= 0x056960004; + msr.hi |= delay_control_table[i].fast_hi; + msr.lo |= delay_control_table[i].fast_low; } } } [View Less]

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[LinuxBIOS] r435 - in LinuxBIOSv3: arch/x86/geodelx include/arch/x86
by svn＠openbios.org 06 Jul '07

06 Jul '07

Author: mjones Date: 2007-07-06 20:03:43 +0200 (Fri, 06 Jul 2007) New Revision: 435 Modified: LinuxBIOSv3/arch/x86/geodelx/geodelx.c LinuxBIOSv3/include/arch/x86/amd_geodelx.h Log: Rework the Geode delay control setup to table driven and much more readable. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Peter Stuge <peter(a)stuge.se> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: LinuxBIOSv3/arch/x86/geodelx/geodelx.c =============================… [View More]====================================== --- LinuxBIOSv3/arch/x86/geodelx/geodelx.c 2007-07-05 17:27:23 UTC (rev 434) +++ LinuxBIOSv3/arch/x86/geodelx/geodelx.c 2007-07-06 18:03:43 UTC (rev 435) @@ -247,7 +247,43 @@ } } + /** + * Delay Control Settings Table from AMD (MCP 0x4C00000F) + * ========================================================================= + */ +const struct delay_controls { + u8 dimms; + u8 devices; + u32 slow_hi; + u32 slow_low; + u32 fast_hi; + u32 fast_low; +} delay_control_table [] = { + /* DIMMs Devs Slow (<=333MHz) Fast (>334MHz) */ + { 1, 4, 0x0837100FF, 0x056960004, 0x0827100FF, 0x056960004 }, + { 1, 8, 0x0837100AA, 0x056960004, 0x0827100AA, 0x056960004 }, + { 1, 16, 0x0837100AA, 0x056960004, 0x082710055, 0x056960004 }, + { 2, 8, 0x0837100A5, 0x056960004, 0x082710000, 0x056960004 }, + { 2, 16, 0x0937100A5, 0x056960004, 0x0C27100A5, 0x056960004 }, + { 2, 20, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 }, + { 2, 24, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 }, + { 2, 32, 0x0B37100A5, 0x056960004, 0x0B2710000, 0x056960004 }, +}; +/** + * - Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM + * in slot 0, but it should be clear for all 2 DIMM settings and if a + * single DIMM is in slot 1. Bits 54:52 should always be set to '111'. + * + * Settings for single DIMM and no VTT termination (Like db800 platform) + * 0xF2F100FF 0x56960004 + * ------------------------------------- + * ADDR/CTL have 22 ohm series R + * DQ/DQM/DQS have 33 ohm series R + */ + + +/** * set_delay_control. This is Black Magic DRAM timing * juju(http://www.thefreedictionary.com/juju) Dram delay depends on * cpu clock, memory bus clock, memory bus loading, memory bus @@ -263,12 +299,10 @@ * @param dimm1 DIMM 1 SMBus address * @param sram_width Data width of the SDRAM */ - void set_delay_control(u8 dimm0, u8 dimm1) { u32 msrnum, glspeed; - u8 spdbyte0, spdbyte1; - int numdimms = 0; + u8 spdbyte0, spdbyte1, dimms, i; struct msr msr; glspeed = geode_link_speed(); @@ -315,9 +349,10 @@ * # of Devices = Module Width (SPD6) / Device Width(SPD13) * Physical Banks(SPD5) * Note - We only support module width of 64. */ + dimms = 0; spdbyte0 = smbus_read_byte(dimm0, SPD_PRIMARY_SDRAM_WIDTH); if (spdbyte0 != 0xFF) { - numdimms++; + dimms++; spdbyte0 = (unsigned char)64 / spdbyte0 * (unsigned char)(smbus_read_byte(dimm0, SPD_NUM_DIMM_BANKS)); } else { @@ -326,136 +361,34 @@ spdbyte1 = smbus_read_byte(dimm1, SPD_PRIMARY_SDRAM_WIDTH); if (spdbyte1 != 0xFF) { - numdimms++; + dimms++; spdbyte1 = (unsigned char)64 / spdbyte1 * (unsigned char)(smbus_read_byte(dimm1, SPD_NUM_DIMM_BANKS)); } else { spdbyte1 = 0; } -/* The current thinking. Subject to change... + /* zero GLCP_DELAY_CONTROLS MSR */ + msr.hi = msr.lo = 0; -; "FUTURE ROBUSTNESS" PROPOSAL -; ---------------------------- -; DIMM Max MBUS MC 0x2000001A bits 26:24 -;DIMMs devices Frequency MCP 0x4C00000F Setting vvv -;----- ------- --------- ---------------------- ---------- -;1 4 400MHz 0x82*100FF 0x56960004 4 -;1 8 400MHz 0x82*100AA 0x56960004 4 -;1 16 400MHz 0x82*10055 0x56960004 4 -; -;2 4,4 400MHz 0x82710000 0x56960004 4 -;2 8,8 400MHz 0xC27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE *** -; -;2 16,4 >333 0xB27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE *** -;2 16,8 >333 0xB27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE *** -;2 16,16 >333 0xB2710000 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE *** -; -;1 4 <=333MHz 0x83*100FF 0x56960004 3 -;1 8 <=333MHz 0x83*100AA 0x56960004 3 -;1 16 <=333MHz 0x83*100AA 0x56960004 3 -; -;2 4,4 <=333MHz 0x837100A5 0x56960004 3 -;2 8,8 <=333MHz 0x937100A5 0x56960004 3 -; -;2 16,4 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE *** -;2 16,8 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE *** -;2 16,16 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE *** -;========================================================================= -;* - Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM in slot 0, -; but it should be clear for all 2 DIMM settings and if a single DIMM is in slot 1. -; Bits 54:52 should always be set to '111'. + /* save some power, disable clock to second DIMM if it is empty */ + if (spdbyte1 == 0) { + msr.hi |= DELAY_UPPER_DISABLE_CLK135; + } -;No VTT termination -;------------------------------------- -;ADDR/CTL have 22 ohm series R -;DQ/DQM/DQS have 33 ohm series R -; -; DIMM Max MBUS -;DIMMs devices Frequency MCP 0x4C00000F Setting -;----- ------- --------- ---------------------- -;1 4 400MHz 0xF2F100FF 0x56960004 4 The MC changes improve Salsa. -;1 8 400MHz 0xF2F100FF 0x56960004 4 Delay controls no real change, -;1 4 <=333MHz 0xF2F100FF 0x56960004 3 just fixing typo in left side. -;1 8 <=333MHz 0xF2F100FF 0x56960004 3 -;1 16 <=333MHz 0xF2F100FF 0x56960004 3 -*/ - msr.hi = msr.lo = 0; + spdbyte0 += spdbyte1; - if (spdbyte0 == 0 || spdbyte1 == 0) { - /* one dimm solution */ - if (spdbyte1 == 0) { - msr.hi |= 0x000800000; - } - spdbyte0 += spdbyte1; - if (spdbyte0 > 8) { - /* large dimm */ + for (i = 0; i < ARRAY_SIZE(delay_control_table); i++) { + if ((dimms == delay_control_table[i].dimms) && + (spdbyte0 <= delay_control_table[i].devices)) { if (glspeed < 334) { - msr.hi |= 0x0837100AA; - msr.lo |= 0x056960004; + msr.hi |= delay_control_table[i].slow_hi; + msr.lo |= delay_control_table[i].slow_low; } else { - msr.hi |= 0x082710055; - msr.lo |= 0x056960004; + msr.hi |= delay_control_table[i].fast_hi; + msr.lo |= delay_control_table[i].fast_low; } - } else if (spdbyte0 > 4) { - /* medium dimm */ - if (glspeed < 334) { - msr.hi |= 0x0837100AA; - msr.lo |= 0x056960004; - } else { - msr.hi |= 0x0827100AA; - msr.lo |= 0x056960004; - } - } else { - /* small dimm */ - if (glspeed < 334) { - msr.hi |= 0x0837100FF; - msr.lo |= 0x056960004; - } else { - msr.hi |= 0x0827100FF; - msr.lo |= 0x056960004; - } } - } else { - /* two dimm solution */ - spdbyte0 += spdbyte1; - if (spdbyte0 > 24) { - /* huge dimms */ - if (glspeed < 334) { - msr.hi |= 0x0B37100A5; - msr.lo |= 0x056960004; - } else { - msr.hi |= 0x0B2710000; - msr.lo |= 0x056960004; - } - } else if (spdbyte0 > 16) { - /* large dimms */ - if (glspeed < 334) { - msr.hi |= 0x0B37100A5; - msr.lo |= 0x056960004; - } else { - msr.hi |= 0x0B27100A5; - msr.lo |= 0x056960004; - } - } else if (spdbyte0 >= 8) { - /* medium dimms */ - if (glspeed < 334) { - msr.hi |= 0x0937100A5; - msr.lo |= 0x056960004; - } else { - msr.hi |= 0x0C27100A5; - msr.lo |= 0x056960004; - } - } else { - /* small dimms */ - if (glspeed < 334) { - msr.hi |= 0x0837100A5; - msr.lo |= 0x056960004; - } else { - msr.hi |= 0x082710000; - msr.lo |= 0x056960004; - } - } } wrmsr(GLCP_DELAY_CONTROLS, msr); return; Modified: LinuxBIOSv3/include/arch/x86/amd_geodelx.h =================================================================== --- LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2007-07-05 17:27:23 UTC (rev 434) +++ LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2007-07-06 18:03:43 UTC (rev 435) @@ -354,7 +354,8 @@ #define GLCP_GLD_MSR_ERROR (MSR_GLCP + 0x2003) #define GLCP_GLD_MSR_PM (MSR_GLCP + 0x2004) #define GLCP_DELAY_CONTROLS (MSR_GLCP + 0x0F) -#define DELAY_LOWER_STATUS_MASK 0x7C0 +#define DELAY_UPPER_DISABLE_CLK135 (1 << 23) +#define DELAY_LOWER_STATUS_MASK 0x7C0 #define GLCP_SYS_RSTPLL (MSR_GLCP + 0x14) /* R/W */ #define RSTPLL_UPPER_GLMULT_SHIFT 7 #define RSTPLL_UPPER_GLMULT_MASK 0x1F [View Less]

1 0

Re: [LinuxBIOS] Porting Linux BIOS to MSI ms7250 (k9n platinum) motherboard
by George V. Adamov 06 Jul '07

06 Jul '07

I have changed the config for MB. (Actualy I took the config from Gigabyte as base, then changed superIO chipset to winbond). George. yhlu wrote: > it mean your mem is not initilized properly. > > socket AM2 or Socket F? you need to specify that in MB Config.lb > > YH >

2 4

[LinuxBIOS] [PATCH][v3] Spinlock fixes
by Uwe Hermann 06 Jul '07

06 Jul '07

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 2

[LinuxBIOS] [PATCH][v3] Add automagic detection for -fno-stack-protector
by Jordan Crouse 05 Jul '07

05 Jul '07

Yay! You have no idea how happy I am to push this patch up. No more -fno-stack-protector hacks (at least for v3). Jordan [PATCH][v3] Add automatic detection for -fno-stack-protector This borrows the cc-option call from the kernel to check if -fno-stack-protector is supported by the compiler, and if it is, then enable it. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Index: LinuxBIOSv3/Makefile =================================================================== --- … [View More]

4 7

[LinuxBIOS] r434 - in LinuxBIOSv3: . util/xcompile
by svn＠openbios.org 05 Jul '07

05 Jul '07

Author: mjones Date: 2007-07-05 19:27:23 +0200 (Thu, 05 Jul 2007) New Revision: 434 Modified: LinuxBIOSv3/Makefile LinuxBIOSv3/util/xcompile/xcompile Log: Add testcc() function to xcompile to check for various compiler flags and set them in the CFLAGS variable if they are located. Added check for -fno-stack-protector flag. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Marc Jones <marc.jones(a)amd.com> … [View More]Modified: LinuxBIOSv3/Makefile =================================================================== --- LinuxBIOSv3/Makefile 2007-07-05 16:58:10 UTC (rev 433) +++ LinuxBIOSv3/Makefile 2007-07-05 17:27:23 UTC (rev 434) @@ -96,6 +96,7 @@ AS := $(AS_$(ARCH)) LD := $(LD_$(ARCH)) OBJCOPY := $(OBJCOPY_$(ARCH)) +CFLAGS += $(CFLAGS_$(ARCH)) CPPFLAGS := $(LINUXBIOSINCLUDE) CFLAGS += $(LINUXBIOSINCLUDE) Modified: LinuxBIOSv3/util/xcompile/xcompile =================================================================== --- LinuxBIOSv3/util/xcompile/xcompile 2007-07-05 16:58:10 UTC (rev 433) +++ LinuxBIOSv3/util/xcompile/xcompile 2007-07-05 17:27:23 UTC (rev 434) @@ -25,6 +25,15 @@ -e s/s390x/s390/ -e s/parisc64/parisc/ \ -e s/ppc.*/powerpc/ -e s/mips.*/mips/` +testcc() +{ + TMP=".$$$$.tmp" + $1 $2 -S -xc /dev/null -o $TMP > /dev/null 2>&1 + ret=$? + rm -rf $TMP + return $ret +} + searchgnu() { # $1 short name @@ -45,18 +54,23 @@ case "$ARCH" in "x86_64") echo "CC_x86 := gcc -m32" + CC="gcc -m32" + searchgnu as >/dev/null && echo "AS_x86 := $(searchgnu as) --32" searchgnu ld >/dev/null && echo "LD_x86 := $(searchgnu ld) -b elf32-i386 -melf_i386" searchgnu objcopy >/dev/null && echo "OBJCOPY_x86 := $(searchgnu objcopy)" ;; "x86") echo "CC_x86 := gcc" + CC="gcc" + searchgnu as >/dev/null && echo "AS_x86 := $(searchgnu as)" searchgnu ld >/dev/null && echo "LD_x86 := $(searchgnu ld)" searchgnu objcopy >/dev/null && echo "OBJCOPY_x86 := $(searchgnu objcopy)" ;; *) # FIXME: This should be detected. + CC="i386-linux-gcc" echo "CC_x86 := i386-linux-gcc" echo "AS_x86 := i386-linux-as" echo "LD_x86 := i386-linux-ld" @@ -64,6 +78,13 @@ ;; esac +# This is where we test for various flags and other things + +CFLAGS="" +testcc "$CC" "-fno-stack-protector" && CFLAGS="$CFLAGS-fno-stack-protector " + +echo "CFLAGS_x86 := $CFLAGS" + # TODO: The same as above for PowerPC, and other architectures # as soon as they are supported by LinuxBIOSv3. [View Less]

1 0

[LinuxBIOS] [Fwd: Re: [PATCH] v3: 8254_pit.patch]
by Marc Jones 05 Jul '07

05 Jul '07

1 0

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coreboot July 2007