July 2007 - coreboot - mail.coreboot.org

[LinuxBIOS] [PATCH][v3] Drop useless Makefiles
by Uwe Hermann July 10, 2007

July 10, 2007

See patch (based on original idea from Juergen Beisert). Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[LinuxBIOS] r442 - in LinuxBIOSv3: . arch mainboard/emulation
by svn＠openbios.org July 10, 2007

July 10, 2007

Author: uwe Date: 2007-07-10 16:38:01 +0200 (Tue, 10 Jul 2007) New Revision: 442 Removed: LinuxBIOSv3/arch/Kconfig LinuxBIOSv3/arch/powerpc/ Modified: LinuxBIOSv3/Kconfig LinuxBIOSv3/mainboard/emulation/Kconfig Log: Drop unused and non-working PowerPC stubs for now (trivial). Will be re-added as soon as we support PowerPC in v3, of course. Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: LinuxBIOSv3/Kconfig =================================================================== --- LinuxBIOSv3/Kconfig 2007-07-10 12:30:07 UTC (rev 441) +++ LinuxBIOSv3/Kconfig 2007-07-10 14:38:01 UTC (rev 442) @@ -63,7 +63,7 @@ endmenu source mainboard/Kconfig -source arch/Kconfig +source arch/x86/Kconfig source lib/Kconfig source device/Kconfig Deleted: LinuxBIOSv3/arch/Kconfig =================================================================== --- LinuxBIOSv3/arch/Kconfig 2007-07-10 12:30:07 UTC (rev 441) +++ LinuxBIOSv3/arch/Kconfig 2007-07-10 14:38:01 UTC (rev 442) @@ -1,25 +0,0 @@ -## -## This file is part of the LinuxBIOS project. -## -## Copyright (C) 2006 coresystems GmbH -## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -# Source all architectures. -source arch/x86/Kconfig -source arch/powerpc/Kconfig - Modified: LinuxBIOSv3/mainboard/emulation/Kconfig =================================================================== --- LinuxBIOSv3/mainboard/emulation/Kconfig 2007-07-10 12:30:07 UTC (rev 441) +++ LinuxBIOSv3/mainboard/emulation/Kconfig 2007-07-10 14:38:01 UTC (rev 442) @@ -35,13 +35,6 @@ help x86 QEMU variant. -config BOARD_EMULATION_QEMU_POWERPC - bool "PowerPC QEMU (EXPERIMENTAL)" - depends on EXPERIMENTAL - select ARCH_POWERPC - help - PowerPC QEMU variant. - endchoice source "mainboard/emulation/qemu-x86/Kconfig"

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[LinuxBIOS] r441 - in LinuxBIOSv3: . northbridge northbridge/amd northbridge/intel southbridge southbridge/amd southbridge/intel superio superio/winbond
by svn＠openbios.org July 10, 2007

July 10, 2007

Author: uwe Date: 2007-07-10 14:30:07 +0200 (Tue, 10 Jul 2007) New Revision: 441 Removed: LinuxBIOSv3/northbridge/Kconfig LinuxBIOSv3/northbridge/amd/Kconfig LinuxBIOSv3/northbridge/intel/Kconfig LinuxBIOSv3/southbridge/Kconfig LinuxBIOSv3/southbridge/amd/Kconfig LinuxBIOSv3/southbridge/intel/Kconfig LinuxBIOSv3/superio/Kconfig LinuxBIOSv3/superio/winbond/Kconfig Modified: LinuxBIOSv3/Kconfig Log: Drop a bunch of useless Kconfig files. Instead of having lots of almost-empty Kconfig files all over the place, we now collect all the "book-keeping" information (as opposed to real LinuxBIOS configuration stuff) in one Kconfig file. The benefits are obvious. Say we have (at some point in the future) 30 supported northbridges, 30 southbridges, and 30 Super I/O chips. That would make 90 useless Kconfig files with just one or two lines in them, spread all over the place. With this new approach we would instead have no additional Kconfig files, just a list of all 90 supported chip(set)s in one Kconfig file. For "real" config options we would still use Kconfig files in (e.g.) southbridge/foo/bar/Kconfig, of course, which are manually "hooked" into the config system in the top-level Kconfig file. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: LinuxBIOSv3/Kconfig =================================================================== --- LinuxBIOSv3/Kconfig 2007-07-10 12:14:36 UTC (rev 440) +++ LinuxBIOSv3/Kconfig 2007-07-10 12:30:07 UTC (rev 441) @@ -67,11 +67,27 @@ source lib/Kconfig source device/Kconfig -# These are used for internal purposes only. -source northbridge/Kconfig -source southbridge/Kconfig -source superio/Kconfig +# These are used for internal purposes only: +# Northbridges: +config NORTHBRIDGE_AMD_GEODELX + boolean +config NORTHBRIDGE_INTEL_I440BXEMULATION + boolean + +# Southbridges: +config SOUTHBRIDGE_AMD_CS5536 + boolean +config SOUTHBRIDGE_INTEL_I82371EB + boolean + +# Super I/Os: +config SUPERIO_WINBOND_W83627HF + boolean + +# Source all northbridge/southbridge/superio Kconfig files: +source northbridge/intel/i440bxemulation/Kconfig + menu "Payload" choice Deleted: LinuxBIOSv3/northbridge/Kconfig =================================================================== --- LinuxBIOSv3/northbridge/Kconfig 2007-07-10 12:14:36 UTC (rev 440) +++ LinuxBIOSv3/northbridge/Kconfig 2007-07-10 12:30:07 UTC (rev 441) @@ -1,24 +0,0 @@ -## -## This file is part of the LinuxBIOS project. -## -## Copyright (C) 2007 coresystems GmbH -## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -source northbridge/amd/Kconfig -source northbridge/intel/Kconfig - Deleted: LinuxBIOSv3/northbridge/amd/Kconfig =================================================================== --- LinuxBIOSv3/northbridge/amd/Kconfig 2007-07-10 12:14:36 UTC (rev 440) +++ LinuxBIOSv3/northbridge/amd/Kconfig 2007-07-10 12:30:07 UTC (rev 441) @@ -1,27 +0,0 @@ -## -## This file is part of the LinuxBIOS project. -## -## Copyright (C) 2007 coresystems GmbH -## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -config NORTHBRIDGE_AMD_GEODELX - boolean - help - This option is internally used to decide which northbridge code to - use. It is set in the mainboard Kconfig file. - Deleted: LinuxBIOSv3/northbridge/intel/Kconfig =================================================================== --- LinuxBIOSv3/northbridge/intel/Kconfig 2007-07-10 12:14:36 UTC (rev 440) +++ LinuxBIOSv3/northbridge/intel/Kconfig 2007-07-10 12:30:07 UTC (rev 441) @@ -1,29 +0,0 @@ -## -## This file is part of the LinuxBIOS project. -## -## Copyright (C) 2007 coresystems GmbH -## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -config NORTHBRIDGE_INTEL_I440BXEMULATION - boolean - help - This option is internally used to decide which northbridge code to - use. It is set in the mainboard Kconfig file. - -source northbridge/intel/i440bxemulation/Kconfig - Deleted: LinuxBIOSv3/southbridge/Kconfig =================================================================== --- LinuxBIOSv3/southbridge/Kconfig 2007-07-10 12:14:36 UTC (rev 440) +++ LinuxBIOSv3/southbridge/Kconfig 2007-07-10 12:30:07 UTC (rev 441) @@ -1,24 +0,0 @@ -## -## This file is part of the LinuxBIOS project. -## -## Copyright (C) 2007 coresystems GmbH -## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -source southbridge/amd/Kconfig -source southbridge/intel/Kconfig - Deleted: LinuxBIOSv3/southbridge/amd/Kconfig =================================================================== --- LinuxBIOSv3/southbridge/amd/Kconfig 2007-07-10 12:14:36 UTC (rev 440) +++ LinuxBIOSv3/southbridge/amd/Kconfig 2007-07-10 12:30:07 UTC (rev 441) @@ -1,27 +0,0 @@ -## -## This file is part of the LinuxBIOS project. -## -## Copyright (C) 2007 coresystems GmbH -## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -config SOUTHBRIDGE_AMD_CS5536 - boolean - help - This option is internally used to decide which southbridge code to - use. It is set in the mainboard Kconfig file. - Deleted: LinuxBIOSv3/southbridge/intel/Kconfig =================================================================== --- LinuxBIOSv3/southbridge/intel/Kconfig 2007-07-10 12:14:36 UTC (rev 440) +++ LinuxBIOSv3/southbridge/intel/Kconfig 2007-07-10 12:30:07 UTC (rev 441) @@ -1,27 +0,0 @@ -## -## This file is part of the LinuxBIOS project. -## -## Copyright (C) 2007 coresystems GmbH -## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -config SOUTHBRIDGE_INTEL_I82371EB - boolean - help - This option is internally used to decide which southbridge code to - use. It is set in the mainboard Kconfig file. - Deleted: LinuxBIOSv3/superio/Kconfig =================================================================== --- LinuxBIOSv3/superio/Kconfig 2007-07-10 12:14:36 UTC (rev 440) +++ LinuxBIOSv3/superio/Kconfig 2007-07-10 12:30:07 UTC (rev 441) @@ -1,23 +0,0 @@ -## -## This file is part of the LinuxBIOS project. -## -## Copyright (C) 2007 coresystems GmbH -## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -source superio/winbond/Kconfig - Deleted: LinuxBIOSv3/superio/winbond/Kconfig =================================================================== --- LinuxBIOSv3/superio/winbond/Kconfig 2007-07-10 12:14:36 UTC (rev 440) +++ LinuxBIOSv3/superio/winbond/Kconfig 2007-07-10 12:30:07 UTC (rev 441) @@ -1,27 +0,0 @@ -## -## This file is part of the LinuxBIOS project. -## -## Copyright (C) 2007 coresystems GmbH -## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -config SUPERIO_WINBOND_W83627HF - boolean - help - This option is internally used to decide which Super I/O code to - use. It is set in the mainboard Kconfig file. -

1 0

[LinuxBIOS] r440 - in LinuxBIOSv3: . northbridge northbridge/amd northbridge/amd/geodelx northbridge/intel northbridge/intel/i440bxemulation southbridge southbridge/amd southbridge/amd/cs5536 southbridge/intel southbridge/intel/i82371eb superio superio/winbond superio/winbond/w83627hf
by svn＠openbios.org July 10, 2007

July 10, 2007

Author: uwe Date: 2007-07-10 14:14:36 +0200 (Tue, 10 Jul 2007) New Revision: 440 Removed: LinuxBIOSv3/northbridge/Makefile LinuxBIOSv3/northbridge/amd/Makefile LinuxBIOSv3/northbridge/intel/Makefile LinuxBIOSv3/southbridge/Makefile LinuxBIOSv3/southbridge/amd/Makefile LinuxBIOSv3/southbridge/intel/Makefile LinuxBIOSv3/superio/Makefile LinuxBIOSv3/superio/winbond/Makefile Modified: LinuxBIOSv3/Makefile LinuxBIOSv3/northbridge/amd/geodelx/Makefile LinuxBIOSv3/northbridge/intel/i440bxemulation/Makefile LinuxBIOSv3/southbridge/amd/cs5536/Makefile LinuxBIOSv3/southbridge/intel/i82371eb/Makefile LinuxBIOSv3/superio/winbond/w83627hf/Makefile Log: Drop a bunch of almost-empty Makefiles which are of no real use. Instead unconditionally include _all_ northbridge/southbridge/superio Makefiles, but put 'ifeq's in each of them to guard against including unwanted contents. This may sound like it's very slow when there are many Makefiles, but in practice the speed difference is neglectable. A few ad hoc tests I did showed no measurable speed differences at all (I used 30 or 40 sample Makefiles). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: LinuxBIOSv3/Makefile =================================================================== --- LinuxBIOSv3/Makefile 2007-07-08 00:19:26 UTC (rev 439) +++ LinuxBIOSv3/Makefile 2007-07-10 12:14:36 UTC (rev 440) @@ -109,9 +109,9 @@ include lib/Makefile include device/Makefile include mainboard/$(MAINBOARDDIR)/Makefile -include northbridge/Makefile -include southbridge/Makefile -include superio/Makefile +include northbridge/*/*/Makefile +include southbridge/*/*/Makefile +include superio/*/*/Makefile include arch/$(ARCH)/Makefile endif Deleted: LinuxBIOSv3/northbridge/Makefile =================================================================== --- LinuxBIOSv3/northbridge/Makefile 2007-07-08 00:19:26 UTC (rev 439) +++ LinuxBIOSv3/northbridge/Makefile 2007-07-10 12:14:36 UTC (rev 440) @@ -1,24 +0,0 @@ -## -## This file is part of the LinuxBIOS project. -## -## Copyright (C) 2007 coresystems GmbH -## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -include $(src)/northbridge/amd/Makefile -include $(src)/northbridge/intel/Makefile - Deleted: LinuxBIOSv3/northbridge/amd/Makefile =================================================================== --- LinuxBIOSv3/northbridge/amd/Makefile 2007-07-08 00:19:26 UTC (rev 439) +++ LinuxBIOSv3/northbridge/amd/Makefile 2007-07-10 12:14:36 UTC (rev 440) @@ -1,25 +0,0 @@ -## -## This file is part of the LinuxBIOS project. -## -## Copyright (C) 2007 coresystems GmbH -## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -ifeq ($(CONFIG_NORTHBRIDGE_AMD_GEODELX),y) - include $(src)/northbridge/amd/geodelx/Makefile -endif - Modified: LinuxBIOSv3/northbridge/amd/geodelx/Makefile =================================================================== --- LinuxBIOSv3/northbridge/amd/geodelx/Makefile 2007-07-08 00:19:26 UTC (rev 439) +++ LinuxBIOSv3/northbridge/amd/geodelx/Makefile 2007-07-10 12:14:36 UTC (rev 440) @@ -19,10 +19,15 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/geodelx/geodelx.o $(obj)/northbridge/amd/geodelx/geodelxinit.o +ifeq ($(CONFIG_NORTHBRIDGE_AMD_GEODELX),y) -$(obj)/northbridge/amd/geodelx/%.o: $(src)/northbridge/amd/geodelx/%.c $(obj)/statictree.h +STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/geodelx/geodelx.o \ + $(obj)/northbridge/amd/geodelx/geodelxinit.o + +$(obj)/northbridge/amd/geodelx/%.o: $(src)/northbridge/amd/geodelx/%.c \ + $(obj)/statictree.h $(Q)mkdir -p $(obj)/northbridge/amd/geodelx $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" $(Q)$(CC) $(INITCFLAGS) -c $< -o $@ +endif Deleted: LinuxBIOSv3/northbridge/intel/Makefile =================================================================== --- LinuxBIOSv3/northbridge/intel/Makefile 2007-07-08 00:19:26 UTC (rev 439) +++ LinuxBIOSv3/northbridge/intel/Makefile 2007-07-10 12:14:36 UTC (rev 440) @@ -1,25 +0,0 @@ -## -## This file is part of the LinuxBIOS project. -## -## Copyright (C) 2007 coresystems GmbH -## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION),y) - include $(src)/northbridge/intel/i440bxemulation/Makefile -endif - Modified: LinuxBIOSv3/northbridge/intel/i440bxemulation/Makefile =================================================================== --- LinuxBIOSv3/northbridge/intel/i440bxemulation/Makefile 2007-07-08 00:19:26 UTC (rev 439) +++ LinuxBIOSv3/northbridge/intel/i440bxemulation/Makefile 2007-07-10 12:14:36 UTC (rev 440) @@ -19,6 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION),y) + STAGE2_CHIPSET_OBJ += $(obj)/northbridge/intel/i440bxemulation/i440bx.o $(obj)/northbridge/intel/i440bxemulation/%.o: $(src)/northbridge/intel/i440bxemulation/%.c $(obj)/statictree.h @@ -26,3 +28,4 @@ $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" $(Q)$(CC) $(INITCFLAGS) -c $< -o $@ +endif Deleted: LinuxBIOSv3/southbridge/Makefile =================================================================== --- LinuxBIOSv3/southbridge/Makefile 2007-07-08 00:19:26 UTC (rev 439) +++ LinuxBIOSv3/southbridge/Makefile 2007-07-10 12:14:36 UTC (rev 440) @@ -1,24 +0,0 @@ -## -## This file is part of the LinuxBIOS project. -## -## Copyright (C) 2007 coresystems GmbH -## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -include $(src)/southbridge/amd/Makefile -include $(src)/southbridge/intel/Makefile - Deleted: LinuxBIOSv3/southbridge/amd/Makefile =================================================================== --- LinuxBIOSv3/southbridge/amd/Makefile 2007-07-08 00:19:26 UTC (rev 439) +++ LinuxBIOSv3/southbridge/amd/Makefile 2007-07-10 12:14:36 UTC (rev 440) @@ -1,26 +0,0 @@ -## -## This file is part of the LinuxBIOS project. -## -## Copyright (C) 2007 coresystems GmbH -## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -# One entry like the below for each supported AMD southbridge. -ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y) - include $(src)/southbridge/amd/cs5536/Makefile -endif - Modified: LinuxBIOSv3/southbridge/amd/cs5536/Makefile =================================================================== --- LinuxBIOSv3/southbridge/amd/cs5536/Makefile 2007-07-08 00:19:26 UTC (rev 439) +++ LinuxBIOSv3/southbridge/amd/cs5536/Makefile 2007-07-10 12:14:36 UTC (rev 440) @@ -19,10 +19,14 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y) + STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/cs5536.o -$(obj)/southbridge/amd/cs5536/%.o: $(src)/southbridge/amd/cs5536/%.c $(obj)/statictree.h +$(obj)/southbridge/amd/cs5536/%.o: $(src)/southbridge/amd/cs5536/%.c \ + $(obj)/statictree.h $(Q)mkdir -p $(obj)/southbridge/amd/cs5536/ $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" $(Q)$(CC) $(INITCFLAGS) -c $< -o $@ +endif Deleted: LinuxBIOSv3/southbridge/intel/Makefile =================================================================== --- LinuxBIOSv3/southbridge/intel/Makefile 2007-07-08 00:19:26 UTC (rev 439) +++ LinuxBIOSv3/southbridge/intel/Makefile 2007-07-10 12:14:36 UTC (rev 440) @@ -1,26 +0,0 @@ -## -## This file is part of the LinuxBIOS project. -## -## Copyright (C) 2007 coresystems GmbH -## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -# One entry like the below for each supported Intel southbridge. -ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82371EB),y) - include $(src)/southbridge/intel/i82371eb/Makefile -endif - Modified: LinuxBIOSv3/southbridge/intel/i82371eb/Makefile =================================================================== --- LinuxBIOSv3/southbridge/intel/i82371eb/Makefile 2007-07-08 00:19:26 UTC (rev 439) +++ LinuxBIOSv3/southbridge/intel/i82371eb/Makefile 2007-07-10 12:14:36 UTC (rev 440) @@ -18,10 +18,14 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82371EB),y) + STAGE2_CHIPSET_OBJ += $(obj)/southbridge/intel/i82371eb/i82371eb.o -$(obj)/southbridge/intel/i82371eb/%.o: $(src)/southbridge/intel/i82371eb/%.c $(obj)/statictree.h +$(obj)/southbridge/intel/i82371eb/%.o: $(src)/southbridge/intel/i82371eb/%.c \ + $(obj)/statictree.h $(Q)mkdir -p $(obj)/southbridge/intel/i82371eb/ $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" $(Q)$(CC) $(INITCFLAGS) -c $< -o $@ +endif Deleted: LinuxBIOSv3/superio/Makefile =================================================================== --- LinuxBIOSv3/superio/Makefile 2007-07-08 00:19:26 UTC (rev 439) +++ LinuxBIOSv3/superio/Makefile 2007-07-10 12:14:36 UTC (rev 440) @@ -1,23 +0,0 @@ -## -## This file is part of the LinuxBIOS project. -## -## Copyright (C) 2007 coresystems GmbH -## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -include $(src)/superio/winbond/Makefile - Deleted: LinuxBIOSv3/superio/winbond/Makefile =================================================================== --- LinuxBIOSv3/superio/winbond/Makefile 2007-07-08 00:19:26 UTC (rev 439) +++ LinuxBIOSv3/superio/winbond/Makefile 2007-07-10 12:14:36 UTC (rev 440) @@ -1,25 +0,0 @@ -## -## This file is part of the LinuxBIOS project. -## -## Copyright (C) 2007 coresystems GmbH -## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -ifeq ($(CONFIG_SUPERIO_WINBOND_W83627HF),y) - include $(src)/superio/winbond/w83627hf/Makefile -endif - Modified: LinuxBIOSv3/superio/winbond/w83627hf/Makefile =================================================================== --- LinuxBIOSv3/superio/winbond/w83627hf/Makefile 2007-07-08 00:19:26 UTC (rev 439) +++ LinuxBIOSv3/superio/winbond/w83627hf/Makefile 2007-07-10 12:14:36 UTC (rev 440) @@ -19,6 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SUPERIO_WINBOND_W83627HF),y) + # Always add to variables, as there could be more than one Super I/O. STAGE2_CHIPSET_OBJ += $(obj)/superio/winbond/w83627hf/superio.o @@ -27,3 +29,4 @@ $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" $(Q)$(CC) $(INITCFLAGS) -c $< -o $@ +endif

1 0

[LinuxBIOS] #82: Fix the memory map in LinuxBIOSv3
by LinuxBIOS July 10, 2007

July 10, 2007

#82: Fix the memory map in LinuxBIOSv3 ---------------------------------+------------------------------------------ Reporter: oxygene | Owner: oxygene Type: defect | Status: new Priority: major | Milestone: Setting up LinuxBIOS v3 Component: code | Version: v3 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ Right now, the memory map in lbv3 is mostly a dummy. Make it represent the situation correctly (ie. exclude the areas taken by the ELF image, the lb tables, ...) -- Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/82> LinuxBIOS <http://www.linuxbios.org/>

1 0

[LinuxBIOS] Convert hex to dec
by Joseph Smith July 10, 2007

July 10, 2007

Hello, Got another silly C newbie question. If I want to convert a hex value to decimal, would this work? value = ff /* Hex value */ sscanf(value, %d, &value) Is the variable "value" now 255?? Thanks - Joe

7 20

[LinuxBIOS] another question for cs5536
by Songmao Tian July 8, 2007

July 8, 2007

Hi Marc, Thanks for you last reply on virtual pci config space, I finally find a doc on it at http://www.amd.com/files/connectivitysolutions/geode/geode_gx/32663C_lx_gx_… by reading the paper of <<Breaking the Chains—Using LinuxBIOS to Liberate Embedded x86 Processors>>, really thanks. And I am curious with the irq signal of cs5536. it's said that gpio12 can be used as a INTR_OUT of pic, I have configure the GPIO as out_aux1，but it's seems I have missed something, the output of gpio12 doesn't change with some rtc interrupt occur(I can see some bit of irr of 8259 set). Thanks in advanced. Tian

5 9

[LinuxBIOS] r439 - LinuxBIOSv3/northbridge/amd/geodelx
by svn＠openbios.org July 8, 2007

July 8, 2007

Author: uwe Date: 2007-07-08 02:19:26 +0200 (Sun, 08 Jul 2007) New Revision: 439 Modified: LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c LinuxBIOSv3/northbridge/amd/geodelx/geodelxinit.c LinuxBIOSv3/northbridge/amd/geodelx/raminit.c Log: Even more coding style fixes and other cosmetic fixes (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c =================================================================== --- LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c 2007-07-07 21:18:47 UTC (rev 438) +++ LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c 2007-07-08 00:19:26 UTC (rev 439) @@ -30,54 +30,74 @@ #include <io.h> #include <amd_geodelx.h> -/* here is programming for the various MSRs.*/ +/* Here is programming for the various MSRs. */ #define IM_QWAIT 0x100000 -/* set in high nibl */ -#define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ +/* Set in high nibble. */ +#define DMCF_WRITE_SERIALIZE_REQUEST (2 << 12) /* 2 outstanding */ -#define DMCF_SERIAL_LOAD_MISSES (2) /* enabled */ +#define DMCF_SERIAL_LOAD_MISSES 2 /* Enabled */ -/* these are the 8-bit attributes for controlling RCONF registers - * RCONF is Region CONFiguraiton, and controls caching and other - * attributes of a region. Just like MTRRs, only different. - */ -#define CACHE_DISABLE (1<<0) -#define WRITE_ALLOCATE (1<<1) -#define WRITE_PROTECT (1<<2) -#define WRITE_THROUGH (1<<3) -#define WRITE_COMBINE (1<<4) -#define WRITE_SERIALIZE (1<<5) +/* These are the 8-bit attributes for controlling RCONF registers. + * + * RCONF is Region CONFiguration, and controls caching and other + * attributes of a region. Just like MTRRs, only different. + */ +#define CACHE_DISABLE (1 << 0) +#define WRITE_ALLOCATE (1 << 1) +#define WRITE_PROTECT (1 << 2) +#define WRITE_THROUGH (1 << 3) +#define WRITE_COMBINE (1 << 4) +#define WRITE_SERIALIZE (1 << 5) -/* ram has none of this stuff */ -#define RAM_PROPERTIES (0) -#define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE) -#define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE) -#define MSR_WS_CD_DEFAULT (0x21212121) +/* RAM has none of this stuff. */ +#define RAM_PROPERTIES 0 +#define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE) +#define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE) +#define MSR_WS_CD_DEFAULT 0x21212121 /* RCONF registers 1810-1817 give you 8 registers with which to * program protection regions the are region configuration range * registers, or RRCF in msr terms, the are a straight base, top * address assign, since they are 4k aligned. */ -/* so no left-shift needed for top or base */ -#define RRCF_LOW(base,properties) (base|(1<<8)|properties) -#define RRCF_LOW_CD(base) RRCF_LOW(base, CACHE_DISABLE) +/* So no left-shift needed for top or base. */ +#define RRCF_LOW(base, properties) (base | (1 << 8) | properties) +#define RRCF_LOW_CD(base) RRCF_LOW(base, CACHE_DISABLE) -/* build initializer for P2D MSR */ -/* this is complex enough that you are going to need to RTFM if you - * really want to understand it. +/* Build initializer for P2D MSR. + * + * This is complex enough that you are going to need to RTFM if you + * really want to understand it. */ -#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pbase>>24), .lo=(pbase<<8)|pmask}} -#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pbase>>24), .lo=(pbase<<8)|pmask}} -#define P2D_R(msr, pdid1, bizarro, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pmax>>12), .lo=(pmax<<20)|pmin}} -#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pmax>>12), .lo=(pmax<<20)|pmin}} -#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(wen), .lo=(ren<<16)|(pscbase>>18)}} -#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}} -#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}} +#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) \ + {msr, {.hi = (pdid1 << 29) | (bizarro << 28) | (pbase >> 24), \ + .lo = (pbase << 8) | pmask}} +#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) \ + {msr, {.hi = (pdid1 << 29) | (bizarro << 28) | \ + (poffset << 8) | (pbase >> 24), \ + .lo = (pbase << 8) | pmask}} +#define P2D_R(msr, pdid1, bizarro, pmax, pmin) \ + {msr, {.hi = (pdid1 << 29) | (bizarro << 28) | (pmax >> 12), \ + .lo = (pmax << 20) | pmin}} +#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) \ + {msr, {.hi = (pdid1 << 29) | (bizarro << 28) | \ + (poffset << 8) | (pmax >> 12), \ + .lo = (pmax << 20) | pmin}} +#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) \ + {msr, {.hi = (pdid1 << 29) | (bizarro << 28) | (wen), \ + .lo = (ren << 16) | (pscbase >> 18)}} +#define IOD_BM(msr, pdid1, bizarro, ibase, imask) \ + {msr, {.hi = (pdid1 << 29) | (bizarro << 28) | (ibase >> 12), \ + .lo = (ibase << 20) | imask}} +#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) \ + {msr, {.hi = (pdid1 << 29) | (bizarro << 28), \ + .lo = (en << 24) | (wen << 21) | \ + (ren << 20) | (ibase << 3)}} #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) +/* TODO: Should be in some header file? */ extern void graphics_init(void); extern void cpu_bug(void); extern void chipsetinit(void); @@ -90,195 +110,213 @@ struct msr_defaults { int msr_no; - struct msr msr; + struct msr msr; } msr_defaults[] = { - {0x1700, {.hi = 0,.lo = IM_QWAIT}}, - {0x1800, {.hi = DMCF_WRITE_SERIALIZE_REQUEST, - .lo = DMCF_SERIAL_LOAD_MISSES}}, + { 0x1700, {.hi = 0,.lo = IM_QWAIT}}, + { 0x1800, {.hi = DMCF_WRITE_SERIALIZE_REQUEST, + .lo = DMCF_SERIAL_LOAD_MISSES}}, + /* 1808 will be done down below, so we have to do 180a->1817 - * (well, 1813 really) + * (well, 1813 really). */ - /* for 180a, for now, we assume VSM will configure it */ - /* 180b is left at reset value,a0000-bffff is non-cacheable */ - /* 180c, c0000-dffff is set to write serialize and non-cachable */ - /* oops, 180c will be set by cpu bug handling in cpubug.c */ - //{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}}, - /* 180d is left at default, e0000-fffff is non-cached */ - /* we will assume 180e, the ssm region configuration, is left - * at default or set by VSM */ - /* we will not set 0x180f, the DMM,yet + /* For 180a, for now, we assume VSM will configure it. */ + /* 180b is left at reset value, a0000-bffff is non-cacheable. */ + /* 180c, c0000-dffff is set to write serialize and non-cachable. */ + /* Oops, 180c will be set by CPU bug handling in cpubug.c. */ + /* TODO: There's no cpubug.c. */ + // {0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}}, + /* 180d is left at default, e0000-fffff is non-cached. */ + /* We will assume 180e, the ssm region configuration, is left + * at default or set by VSM. */ - //{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}}, - //{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}}, - //{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}}, - //{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}}, - /* now for GLPCI routing */ + /* We will not set 0x180f, the DMM, yet. */ + + // {0x1810, {.hi = 0xee7ff000, + // .lo = RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}}, + // {0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}}, + // {0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}}, + // {0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}}, + + /* Now for GLPCI routing. */ + /* GLIU0 */ - P2D_BM(MSR_GLIU0_BASE1, 0x1, 0x0, 0x0, 0xfff80), - P2D_BM(MSR_GLIU0_BASE2, 0x1, 0x0, 0x80000, 0xfffe0), + P2D_BM(MSR_GLIU0_BASE1, 0x1, 0x0, 0x0, 0xfff80), + P2D_BM(MSR_GLIU0_BASE2, 0x1, 0x0, 0x80000, 0xfffe0), P2D_SC(MSR_GLIU0_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), + /* GLIU1 */ - P2D_BM(MSR_GLIU1_BASE1, 0x1, 0x0, 0x0, 0xfff80), - P2D_BM(MSR_GLIU1_BASE2, 0x1, 0x0, 0x80000, 0xfffe0), - P2D_SC(MSR_GLIU1_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), - {0} + P2D_BM(MSR_GLIU1_BASE1, 0x1, 0x0, 0x0, 0xfff80), + P2D_BM(MSR_GLIU1_BASE2, 0x1, 0x0, 0x80000, 0xfffe0), + P2D_SC(MSR_GLIU1_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), + + {0}, }; -/** - * Size up ram. All we need to here is read the MSR for DRAM and grab - * out the sizing bits. Note that this code depends on initram - * having run. It uses the MSRs, not the SPDs, and the MSRs of course - * are set up by initram. - */ +/** + * Size up ram. + * + * All we need to do here is read the MSR for DRAM and grab out the sizing + * bits. Note that this code depends on initram having run. It uses the MSRs, + * not the SPDs, and the MSRs of course are set up by initram. + * + * @return TODO + */ int sizeram(void) { - struct msr msr; + struct msr msr; int sizem = 0; unsigned short dimm; /* Get the RAM size from the memory controller as calculated - * and set by auto_size_dimm() + * and set by auto_size_dimm(). */ msr = rdmsr(MC_CF07_DATA); - printk(BIOS_DEBUG,"sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo); - - /* dimm 0 */ + printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, + msr.lo); + + /* DIMM 0 */ dimm = msr.hi; - /* installed? */ + /* Installed? */ if ((dimm & 7) != 7) { /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */ - sizem = 4 << ((dimm >> 12) & 0x0F); } - - /* dimm 1 */ + sizem = 4 << ((dimm >> 12) & 0x0F); + } + + /* DIMM 1 */ dimm = msr.hi >> 16; - /* installed? */ + /* Installed? */ if ((dimm & 7) != 7) { /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */ sizem += 4 << ((dimm >> 12) & 0x0F); } - printk(BIOS_DEBUG,"sizeram: sizem 0x%xMB\n", sizem); + printk(BIOS_DEBUG, "sizeram: sizem 0x%xMB\n", sizem); + return sizem; } -/** - * enable_shadow. Currently not set up. - * @param dev The nortbridge device. - */ -static void enable_shadow(struct device * dev) +/** + * Currently not set up. + * + * @param dev The nortbridge device. + */ +static void enable_shadow(struct device *dev) { } /** - * init the northbridge pci device. Right now this a no op. We leave - * it here as a hook for later use. - * @param dev The nortbridge device. - */ -static void geodelx_northbridge_init(struct device * dev) + * Initialize the northbridge PCI device. + * Right now this a no op. We leave it here as a hook for later use. + * + * @param dev The nortbridge device. + */ +static void geodelx_northbridge_init(struct device *dev) { - //struct msr msr; + /* struct msr msr; */ - printk(BIOS_SPEW,">> Entering northbridge.c: %s\n", __FUNCTION__); + printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__); enable_shadow(dev); - /* - * Swiss cheese - */ - //msr = rdmsr(MSR_GLIU0_SHADOW); - //msr.hi |= 0x3; - //msr.lo |= 0x30000; +#if 0 + /* Swiss cheese */ + msr = rdmsr(MSR_GLIU0_SHADOW); - //printk(BIOS_DEBUG,"MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo); - //printk(BIOS_DEBUG,"MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo); + msr.hi |= 0x3; + msr.lo |= 0x30000; + + printk(BIOS_DEBUG,"MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo); + printk(BIOS_DEBUG,"MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo); +#endif } -/** - * Set resources for the PCI northbridge device. This function is - * required due to VSA interactions. - * @param dev The nortbridge device. - */ +/** + * Set resources for the PCI northbridge device. + * This function is required due to VSA interactions. + * + * @param dev The nortbridge device. + */ void geodelx_northbridge_set_resources(struct device *dev) { struct resource *resource, *last; - unsigned link; + unsigned int link; u8 line; last = &dev->resource[dev->resources]; for (resource = &dev->resource[0]; resource < last; resource++) { - - /* - * from AMD: do not change the base address, it will - * make the VSA virtual registers unusable + /* From AMD: do not change the base address, it will + * make the VSA virtual registers unusable. */ - //pci_set_resource(dev, resource); - // FIXME: static allocation may conflict with dynamic mappings! + // pci_set_resource(dev, resource); + // FIXME: Static allocation may conflict with dynamic mappings! } - + for (link = 0; link < dev->links; link++) { struct bus *bus; bus = &dev->link[link]; if (bus->children) { - printk(BIOS_DEBUG, - "my_dev_set_resources: phase4_assign_resources %d\n", bus); + printk(BIOS_DEBUG, + "my_dev_set_resources: phase4_assign_resources %d\n", + bus); phase4_assign_resources(bus); } } - - /* set a default latency timer */ + + /* Set a default latency timer. */ pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40); - - /* set a default secondary latency timer */ - if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) { + + /* Set a default secondary latency timer. */ + if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40); - } - /* zero the irq settings */ + /* Zero the IRQ settings. */ line = pci_read_config8(dev, PCI_INTERRUPT_PIN); - if (line) { + if (line) pci_write_config8(dev, PCI_INTERRUPT_LINE, 0); - } - /* set the cache line size, so far 64 bytes is good for everyone */ + /* Set the cache line size, so far 64 bytes is good for everyone. */ pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2); } - - -/** - * Set resources for the PCI domain. Just set up basic global ranges - * for IO and memory Allocation of sub-resources draws on these - * top-level resources in the usual hierarchical manner. - * @param dev The nortbridge device. - */ -static void geodelx_pci_domain_read_resources(struct device * dev) +/** + * Set resources for the PCI domain. + * + * Just set up basic global ranges for I/O and memory. Allocation of + * sub-resources draws on these top-level resources in the usual + * hierarchical manner. + * + * @param dev The nortbridge device. + */ +static void geodelx_pci_domain_read_resources(struct device *dev) { struct resource *resource; - printk(BIOS_SPEW,">> Entering northbridge.c: %s\n", __FUNCTION__); - /* Initialize the system wide io space constraints */ + printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__); + + /* Initialize the system wide I/O space constraints. */ resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); resource->limit = 0xffffUL; resource->flags = - IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - /* Initialize the system wide memory resources constraints */ + /* Initialize the system wide memory resources constraints. */ resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); resource->limit = 0xffffffffULL; resource->flags = - IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; } -/** - * Create a ram resource, by taking the passed-in size and createing - * a resource record. - * @param dev the device - * @param index a resource index - * @param basek base memory address in k - * @param sizek size of memory in k - */ -static void ram_resource(struct device * dev, unsigned long index, +/** + * Create a RAM resource, by taking the passed-in size and creating + * a resource record. + * + * @param dev The device. + * @param index A resource index. + * @param basek Base memory address in KB. + * @param sizek Size of memory in KB. + */ +static void ram_resource(struct device *dev, unsigned long index, unsigned long basek, unsigned long sizek) { struct resource *resource; @@ -290,159 +328,169 @@ resource->base = ((resource_t) basek) << 10; resource->size = ((resource_t) sizek) << 10; resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -/** - * Set resources in the pci domain. Also, as a side effect, create a - * ram resource in the child which, interestingly enough, is the - * north bridge pci device, for later allocation of address space. - * @param dev the device - */ - static void geodelx_pci_domain_set_resources(struct device * dev) +/** + * Set resources in the PCI domain. + * + * Also, as a side effect, create a RAM resource in the child which, + * interestingly enough, is the northbridge PCI device, for later + * allocation of address space. + * + * @param dev The device. + */ +static void geodelx_pci_domain_set_resources(struct device *dev) { int idx; - struct device * mc_dev; + struct device *mc_dev; - printk(BIOS_SPEW,">> Entering northbridge.c: %s\n", __FUNCTION__); + printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__); mc_dev = dev->link[0].children; if (mc_dev) { - /* Report the memory regions */ + /* Report the memory regions. */ idx = 10; + /* 0 .. 640 KB */ ram_resource(dev, idx++, 0, 640); - /* Systop - 1 MB -> KB*/ - ram_resource(dev, idx++, 1024, (get_systop() - 0x100000) / 1024); + /* 1 MB .. (Systop - 1 MB) (converted to KB) */ + ram_resource(dev, idx++, 1024, + (get_systop() - (1 * 1024 * 1024)) / 1024); } phase4_assign_resources(&dev->link[0]); } /** - * enable the pci domain. A littly tricky on this chipset due to the - * VSA interactions. This must happen before any PCI scans happen. - * we do early northbridge init to make sure pci scans will work, but - * the weird part is we actually have to run some code in x86 mode to - * get the VSM installed, since the VSM actually handles some PCI bus - * scan tasks via the System Management Interrupt. Yes, it gets - * tricky ... - * @param dev the device - */ -static void geodelx_pci_domain_phase2(struct device * dev) + * Enable the PCI domain. + * + * A littly tricky on this chipset due to the VSA interactions. This must + * happen before any PCI scans happen. We do early northbridge init to make + * sure PCI scans will work, but the weird part is we actually have to run + * some code in x86 mode to get the VSM installed, since the VSM actually + * handles some PCI bus scan tasks via the System Management Interrupt. + * Yes, it gets tricky... + * + * @param dev The device. + */ +static void geodelx_pci_domain_phase2(struct device *dev) { + printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__); - printk(BIOS_SPEW,">> Entering northbridge.c: %s\n", __FUNCTION__); - northbridge_init_early(); #warning cpu bug has been moved to initram stage -// cpu_bug(); + /* cpu_bug(); */ chipsetinit(); setup_realmode_idt(); - printk(BIOS_DEBUG,"Before VSA:\n"); - // print_conf(); -#warning Not doing vsm bios -- linux will fail. -// do_vsmbios(); // do the magic stuff here, so prepare your tambourine ;) + printk(BIOS_DEBUG, "Before VSA:\n"); + /* print_conf(); */ +#warning Not doing vsm bios -- linux will fail. + /* Do the magic stuff here, so prepare your tambourine ;) */ + /* do_vsmbios(); */ + printk(BIOS_DEBUG, "After VSA:\n"); + /* print_conf(); */ - printk(BIOS_DEBUG,"After VSA:\n"); - // print_conf(); - -#warning graphics_init is disabled. -// graphics_init(); +#warning graphics_init is disabled. + /* graphics_init(); */ pci_set_method(dev); } /** - * Support for scan bus from the "tippy top" -- i.e. the pci domain, - * not the 0:0.0 device. - * @param dev The pci domain device - * @param max max number of devices to scan. - */ -static unsigned int geodelx_pci_domain_scan_bus(struct device * dev, unsigned int max) + * Support for scan bus from the "tippy top" -- i.e. the PCI domain, + * not the 0:0.0 device. + * + * @param dev The PCI domain device. + * @param max Maximum number of devices to scan. + */ +static unsigned int geodelx_pci_domain_scan_bus(struct device *dev, + unsigned int max) { - printk(BIOS_SPEW,">> Entering northbridge.c: %s\n", __FUNCTION__); + printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__); max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); return max; } - /** - * Support for apic cluster init. TODO should we do this in phase 2? - * It is now done in phase 6 - * @param dev The pci domain device - */ -static void cpu_bus_init(struct device * dev) + * Support for APIC cluster init. + * + * TODO: Should we do this in phase 2? It is now done in phase 6. + * + * @param dev The PCI domain device. + */ +static void cpu_bus_init(struct device *dev) { - printk(BIOS_SPEW,">> Entering northbridge.c: %s\n", __FUNCTION__); - printk(BIOS_SPEW,">> Exiting northbridge.c: %s\n", __FUNCTION__); - + printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__); + printk(BIOS_SPEW, ">> Exiting northbridge.c: %s\n", __FUNCTION__); } -static void cpu_bus_noop(struct device * dev) +static void cpu_bus_noop(struct device *dev) { } -/* the same hardware, being multifunction, has several roles. In this - * case, the north is a pci domain controller, apic cluster, and the - * traditional 0:0.0 device - */ +/* The same hardware, being multifunction, has several roles. In this case, + * the northbridge is a PCI domain controller, APIC cluster, and the + * traditional 0:0.0 device. + */ -/* Here are the operations for when the northbridge is running a PCI - * domain. - */ +/** Operations for when the northbridge is running a PCI domain. */ struct device_operations geodelx_pcidomainops = { - .constructor = default_device_constructor, - .phase2_setup_scan_bus = geodelx_pci_domain_phase2, - .phase3_scan = geodelx_pci_domain_scan_bus, - .phase4_read_resources = geodelx_pci_domain_read_resources, - .phase4_set_resources = geodelx_pci_domain_set_resources, - .phase5_enable_resources = enable_childrens_resources, - .phase6_init = 0, - .ops_pci_bus = &pci_cf8_conf1, - + .constructor = default_device_constructor, + .phase2_setup_scan_bus = geodelx_pci_domain_phase2, + .phase3_scan = geodelx_pci_domain_scan_bus, + .phase4_read_resources = geodelx_pci_domain_read_resources, + .phase4_set_resources = geodelx_pci_domain_set_resources, + .phase5_enable_resources = enable_childrens_resources, + .phase6_init = 0, + .ops_pci_bus = &pci_cf8_conf1, }; -/* Here are the operations for when the northbridge is running an APIC - * cluster. - */ +/** Operations for when the northbridge is running an APIC cluster. */ struct device_operations geodelx_apicops = { - .constructor = default_device_constructor, - .phase3_scan = 0, - .phase4_read_resources = cpu_bus_noop, - .phase4_set_resources = cpu_bus_noop, - .phase5_enable_resources = cpu_bus_noop, - .phase6_init = cpu_bus_init, - .ops_pci_bus = &pci_cf8_conf1, + .constructor = default_device_constructor, + .phase3_scan = 0, + .phase4_read_resources = cpu_bus_noop, + .phase4_set_resources = cpu_bus_noop, + .phase5_enable_resources = cpu_bus_noop, + .phase6_init = cpu_bus_init, + .ops_pci_bus = &pci_cf8_conf1, }; -/* Here are the operations for when the northbridge is running a PCI - * device. - */ +/** Operations for when the northbridge is running a PCI device. */ struct device_operations geodelx_pci_ops = { - .constructor = default_device_constructor, - .phase3_scan = geodelx_pci_domain_scan_bus, - .phase4_read_resources = geodelx_pci_domain_read_resources, - .phase4_set_resources = geodelx_northbridge_set_resources, - .phase5_enable_resources = enable_childrens_resources, - .phase6_init = geodelx_northbridge_init, - .ops_pci_bus = &pci_cf8_conf1, - + .constructor = default_device_constructor, + .phase3_scan = geodelx_pci_domain_scan_bus, + .phase4_read_resources = geodelx_pci_domain_read_resources, + .phase4_set_resources = geodelx_northbridge_set_resources, + .phase5_enable_resources = enable_childrens_resources, + .phase6_init = geodelx_northbridge_init, + .ops_pci_bus = &pci_cf8_conf1, }; +/** + * The constructor for the device. + * Domain ops and APIC cluster ops and PCI device ops are different. + */ +struct constructor geodelx_north_constructors[] = { + /* Northbridge running a PCI domain. */ + {.id = {.type = DEVICE_ID_PCI_DOMAIN, + .u = {.pci_domain = {.vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_LXBRIDGE}}}, + .ops = &geodelx_pcidomainops}, -/* The constructor for the device. */ -/* Domain ops and apic cluster ops and pci device ops are different */ -struct constructor geodelx_north_constructors[] = { - {.id = {.type = DEVICE_ID_PCI_DOMAIN, - .u = {.pci_domain = {.vendor = PCI_VENDOR_ID_AMD,.device = PCI_DEVICE_ID_AMD_LXBRIDGE}}}, - &geodelx_pcidomainops}, - {.id = {.type = DEVICE_ID_APIC_CLUSTER, - .u = {.apic_cluster = {.vendor = PCI_VENDOR_ID_AMD,.device = PCI_DEVICE_ID_AMD_LXBRIDGE}}}, - &geodelx_apicops}, - {.id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = PCI_VENDOR_ID_AMD,.device = PCI_DEVICE_ID_AMD_LXBRIDGE}}}, - &geodelx_pci_ops}, - {.ops = 0}, + /* Northbridge running an APIC cluster. */ + {.id = {.type = DEVICE_ID_APIC_CLUSTER, + .u = {.apic_cluster = {.vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_LXBRIDGE}}}, + .ops = &geodelx_apicops}, + + /* Northbridge running a PCI device. */ + {.id = {.type = DEVICE_ID_PCI, + .u = {.pci = {.vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_LXBRIDGE}}}, + .ops = &geodelx_pci_ops}, + + {.ops = 0}, }; Modified: LinuxBIOSv3/northbridge/amd/geodelx/geodelxinit.c =================================================================== --- LinuxBIOSv3/northbridge/amd/geodelx/geodelxinit.c 2007-07-07 21:18:47 UTC (rev 438) +++ LinuxBIOSv3/northbridge/amd/geodelx/geodelxinit.c 2007-07-08 00:19:26 UTC (rev 439) @@ -37,21 +37,21 @@ }; struct gliutable gliu0table[] = { - /* 0-7FFFF to MC */ + /* 0-7FFFF to MC */ {.desc_name = MSR_GLIU0_BASE1,.desc_type = BM,.hi = MSR_MC + 0x0, .lo = 0x0FFF80}, - /* 80000-9ffff to Mc */ + /* 80000-9FFFF to MC */ {.desc_name = MSR_GLIU0_BASE2,.desc_type = BM,.hi = MSR_MC + 0x0, .lo = (0x80 << 20) + 0x0FFFE0}, - /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff - * handled by SoftVideo + /* C0000-FFFFF split to MC and PCI (sub decode) A0000-BFFFF + * handled by SoftVideo. */ {.desc_name = MSR_GLIU0_SHADOW,.desc_type = SC_SHADOW, .hi = MSR_MC + 0x0,.lo = 0x03}, - /* Catch and fix dynamicly. */ + /* Catch and fix dynamically. */ {.desc_name = MSR_GLIU0_SYSMEM,.desc_type = R_SYSMEM, .hi = MSR_MC,.lo = 0x0}, - /* Catch and fix dynamicly. */ + /* Catch and fix dynamically. */ {.desc_name = MSR_GLIU0_SMM,.desc_type = BMO_SMM, .hi = MSR_MC,.lo = 0x0}, {.desc_name = GLIU0_GLD_MSR_COH,.desc_type = OTHER, @@ -60,24 +60,24 @@ }; struct gliutable gliu1table[] = { - /* 0-7FFFF to MC */ + /* 0-7FFFF to MC */ {.desc_name = MSR_GLIU1_BASE1,.desc_type = BM,.hi = MSR_GL0 + 0x0, .lo = 0x0FFF80}, - /* 80000-9ffff to Mc */ + /* 80000-9FFFF to MC */ {.desc_name = MSR_GLIU1_BASE2,.desc_type = BM,.hi = MSR_GL0 + 0x0, .lo = (0x80 << 20) + 0x0FFFE0}, - /* C0000-Fffff split to MC and PCI (sub decode) */ + /* C0000-Fffff split to MC and PCI (sub decode) */ {.desc_name = MSR_GLIU1_SHADOW,.desc_type = SC_SHADOW, .hi = MSR_GL0 + 0x0,.lo = 0x03}, - /* Catch and fix dynamicly. */ + /* Catch and fix dynamically. */ {.desc_name = MSR_GLIU1_SYSMEM,.desc_type = R_SYSMEM, .hi = MSR_GL0,.lo = 0x0}, - /* Catch and fix dynamicly. */ + /* Catch and fix dynamically. */ {.desc_name = MSR_GLIU1_SMM,.desc_type = BM_SMM, .hi = MSR_GL0,.lo = 0x0}, {.desc_name = GLIU1_GLD_MSR_COH,.desc_type = OTHER, .hi = 0x0,.lo = GL1_GLIU0}, - /* FooGlue FPU 0xF0 */ + /* FooGlue FPU 0xF0 */ {.desc_name = MSR_GLIU1_FPU_TRAP,.desc_type = SCIO, .hi = (GL1_GLCP << 29) + 0x0,.lo = 0x033000F0}, {.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0}, @@ -87,121 +87,116 @@ struct msrinit { unsigned long msrnum; - struct msr msr; + struct msr msr; }; struct msrinit clock_gating_default[] = { - {GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}}, - {MC_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}}, - {VG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}}, - {GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}}, - {DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0555}}, - {GLIU1_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}}, - {GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0014}}, - {GLPCI_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}}, - {VIP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}}, - {AES_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}}, - {CPU_BC_PMODE_MSR, {.hi = 0x00,.lo = 0x70303}}, - {0xffffffff, {0xffffffff, 0xffffffff}}, + {GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}}, + {MC_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}}, + {VG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}}, + {GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}}, + {DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0555}}, + {GLIU1_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}}, + {GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0014}}, + {GLPCI_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}}, + {VIP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}}, + {AES_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}}, + {CPU_BC_PMODE_MSR, {.hi = 0x00,.lo = 0x70303}}, // TODO: Correct? + {0xffffffff, {0xffffffff, 0xffffffff}}, }; -/* */ -/* SET GeodeLink PRIORITY*/ -/* */ +/** GeodeLink priority table. */ struct msrinit geode_link_priority_table[] = { - {CPU_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0220}}, - {DF_GLD_MSR_MASTER_CONF, {.hi = 0x00,.lo = 0x0000}}, - {VG_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0720}}, - {GP_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0010}}, - {GLPCI_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0017}}, - {GLCP_GLD_MSR_CONF, {.hi = 0x00,.lo = 0x0001}}, - {VIP_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0622}}, - {AES_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0013}}, - {0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END */ + {CPU_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0220}}, + {DF_GLD_MSR_MASTER_CONF, {.hi = 0x00,.lo = 0x0000}}, + {VG_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0720}}, + {GP_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0010}}, + {GLPCI_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0017}}, + {GLCP_GLD_MSR_CONF, {.hi = 0x00,.lo = 0x0001}}, + {VIP_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0622}}, + {AES_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0013}}, + {0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, }; extern int sizeram(void); /** - * Write a GeodeLink MSR. - * @param gl A Geode Link table descriptor - */ + * Write a GeodeLink MSR. + * + * @param gl A GeodeLink table descriptor. + */ static void writeglmsr(struct gliutable *gl) { - struct msr msr; + struct msr msr; msr.lo = gl->lo; msr.hi = gl->hi; - wrmsr(gl->desc_name, msr); // MSR - see table above - printk(BIOS_SPEW, - "%s: MSR 0x%08x, val 0x%08x:0x%08x\n", - __FUNCTION__, gl->desc_name, msr.hi, msr.lo); + wrmsr(gl->desc_name, msr); /* MSR - see table above. */ + printk(BIOS_SPEW, + "%s: MSR 0x%08x, val 0x%08x:0x%08x\n", + __FUNCTION__, gl->desc_name, msr.hi, msr.lo); } /** - * Read the MSR specified in the gl struct. If the low 32 bits is zero, - * indicating - * it has not been set, set it. - * @param gl A Geode Link table descriptor - */ + * Read the MSR specified in the gl struct. If the low 32 bits are zero, + * indicating it has not been set, set it. + * + * @param gl A GeodeLink table descriptor. + */ static void ShadowInit(struct gliutable *gl) { - struct msr msr; + struct msr msr; msr = rdmsr(gl->desc_name); - - if (msr.lo == 0) { + if (msr.lo == 0) writeglmsr(gl); - } } -extern int sizeram(void); - /** - * Set up the system memory registers, i.e. memory that can be used - * for non-VSM (or SMM) purposes. - * @param gl A Geode Link table descriptor - */ - + * Set up the system memory registers, i.e. memory that can be used + * for non-VSM (or SMM) purposes. + * + * @param gl A GeodeLink table descriptor. + */ static void sysmem_init(struct gliutable *gl) { - struct msr msr; + struct msr msr; int sizembytes, sizebytes; - /* - * Figure out how much RAM is in the machine and alocate all to the + /* Figure out how much RAM is in the machine and allocate all to the * system. We will adjust for SMM now and Frame Buffer later. */ sizembytes = sizeram(); - printk(BIOS_DEBUG, "%s: enable for %dMBytes\n", + printk(BIOS_DEBUG, "%s: enable for %dMBytes\n", __FUNCTION__, sizembytes); sizebytes = sizembytes << 20; sizebytes -= ((SMM_SIZE * 1024) + 1); - printk(BIOS_DEBUG, "usable RAM: %d bytes\n", sizebytes); + printk(BIOS_DEBUG, "Usable RAM: %d bytes\n", sizebytes); - /* 20 bit address The bottom 12 bits go into bits 20-31 in msr.lo - The top 8 bits go into 0-7 of msr.hi. */ + /* 20 bit address. The bottom 12 bits go into bits 20-31 in msr.lo. + * The top 8 bits go into 0-7 of msr.hi. + */ sizebytes--; msr.hi = (gl->hi & 0xFFFFFF00) | (sizebytes >> 24); - sizebytes <<= 8; /* move bits 23:12 in bits 31:20. */ + sizebytes <<= 8; /* Move bits 23:12 in bits 31:20. */ sizebytes &= 0xfff00000; - sizebytes |= 0x100; /* start at 1MB */ + sizebytes |= 0x100; /* Start at 1 MB. */ msr.lo = sizebytes; - wrmsr(gl->desc_name, msr); // MSR - see table above + wrmsr(gl->desc_name, msr); /* MSR - see table above. */ printk(BIOS_DEBUG, "%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, - gl->desc_name, msr.hi, msr.lo); + gl->desc_name, msr.hi, msr.lo); } /** - * Set up GL0 memory mapping. Again, SMM memory is subtracted. - * @param gl A Geode Link table descriptor - */ - + * Set up GL0 memory mapping. Again, SMM memory is subtracted. + * + * @param gl A GeodeLink table descriptor. + */ static void SMMGL0Init(struct gliutable *gl) { - struct msr msr; + struct msr msr; int sizebytes = sizeram() << 20; long offset; @@ -209,7 +204,7 @@ printk(BIOS_DEBUG, "%s: %d bytes\n", __FUNCTION__, sizebytes); - /* calculate the Two's complement offset */ + /* Calculate the "two's complement" offset. */ offset = sizebytes - SMM_OFFSET; offset = (offset >> 12) & 0x000fffff; printk(BIOS_DEBUG, "%s: offset is 0x%08x\n", __FUNCTION__, SMM_OFFSET); @@ -220,94 +215,89 @@ msr.lo = SMM_OFFSET << 8; msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff; - wrmsr(gl->desc_name, msr); // MSR - See table above + wrmsr(gl->desc_name, msr); /* MSR - See table above. */ printk(BIOS_DEBUG, "%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, - gl->desc_name, msr.hi, msr.lo); + gl->desc_name, msr.hi, msr.lo); } /** - * Set up GL1 memory mapping. Again, SMM memory is subtracted. - * @param gl A Geode Link table descriptor - */ - + * Set up GL1 memory mapping. Again, SMM memory is subtracted. + * + * @param gl A GeodeLink table descriptor. + */ static void SMMGL1Init(struct gliutable *gl) { - struct msr msr; + struct msr msr; printk(BIOS_DEBUG, "%s:\n", __FUNCTION__); msr.hi = gl->hi; - /* I don't think this is needed */ + /* I don't think this is needed. */ msr.hi &= 0xffffff00; msr.hi |= (SMM_OFFSET >> 24); msr.lo = (SMM_OFFSET << 8) & 0xFFF00000; msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff; - wrmsr(gl->desc_name, msr); // MSR - See table above + wrmsr(gl->desc_name, msr); /* MSR - See table above. */ printk(BIOS_DEBUG, "%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, - gl->desc_name, msr.hi, msr.lo); + gl->desc_name, msr.hi, msr.lo); } /** - * Set up all Geode Link Interfaces. Iterate over the table until done. - * Case out on the link type, and call the appropriate function. - * @param gl A Geode Link table descriptor - */ - + * Set up all GeodeLink interfaces. Iterate over the table until done. + * + * Case out on the link type, and call the appropriate function. + * + * @param gl A GeodeLink table descriptor. + */ static void GLIUInit(struct gliutable *gl) { - while (gl->desc_type != GL_END) { switch (gl->desc_type) { default: - /* For Unknown types: Write then read MSR */ + /* For unknown types: Write then read MSR. */ writeglmsr(gl); - case SC_SHADOW: /* Check for a Shadow entry */ + case SC_SHADOW: /* Check for a Shadow entry. */ ShadowInit(gl); break; - - case R_SYSMEM: /* check for a SYSMEM entry */ + case R_SYSMEM: /* Check for a SYSMEM entry. */ sysmem_init(gl); break; - - case BMO_SMM: /* check for a SMM entry */ + case BMO_SMM: /* Check for a SMM entry. */ SMMGL0Init(gl); break; - - case BM_SMM: /* check for a SMM entry */ + case BM_SMM: /* Check for a SMM entry. */ SMMGL1Init(gl); break; } gl++; } - } /** - * Set up the region config registers for the Geode Link PCI interface. - * R0: 0-640KB, - * R1: 1MB - Top of System Memory - * R2: SMM Memory - * R3: Framebuffer? - not set up yet - */ + * Set up the region config registers for the GeodeLink PCI interface. + * + * R0: 0 - 640 KB + * R1: 1 MB - Top of System Memory + * R2: SMM Memory + * R3: Framebuffer? - not set up yet. + */ static void GLPCI_init(void) { - struct gliutable *gl = 0; - int i; - struct msr msr; - int msrnum, enable_preempt, enable_cpu_override; + struct gliutable *gl = NULL; + struct msr msr; + int i, msrnum, enable_preempt, enable_cpu_override; int nic_grants_control, enable_bus_parking; - /* R0 - GLPCI settings for Conventional Memory space. */ + /* R0 - GLPCI settings for Conventional Memory space. */ msr.hi = (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT; /* 640 */ - msr.lo = 0; /* 0 */ - msr.lo |= - GLPCI_RC_LOWER_EN_SET + GLPCI_RC_LOWER_PF_SET + - GLPCI_RC_LOWER_WC_SET; + msr.lo = 0; /* 0 */ + msr.lo |= GLPCI_RC_LOWER_EN_SET + GLPCI_RC_LOWER_PF_SET + + GLPCI_RC_LOWER_WC_SET; msrnum = GLPCI_RC0; wrmsr(msrnum, msr); - /* R1 - GLPCI settings for SysMem space. */ - /* Get systop from GLIU0 SYSTOP Descriptor */ + /* R1 - GLPCI settings for SysMem space. */ + /* Get systop from GLIU0 SYSTOP Descriptor. */ for (i = 0; gliu0table[i].desc_name != GL_END; i++) { if (gliu0table[i].desc_type == R_SYSMEM) { gl = &gliu0table[i]; @@ -318,51 +308,52 @@ unsigned long pah, pal; msrnum = gl->desc_name; msr = rdmsr(msrnum); - /* example R_SYSMEM value: 20:00:00:0f:fb:f0:01:00 + + /* Example: R_SYSMEM value 20:00:00:0f:fb:f0:01:00 * translates to a base of 0x00100000 and top of 0xffbf0000 - * base of 1M and top of around 256M + * base of 1M and top of around 256M. */ /* we have to create a page-aligned (4KB page) address - * for base and top */ - /* So we need a high page aligned addresss (pah) and + * for base and top. + * So we need a high page aligned addresss (pah) and * low page aligned address (pal) pah is from msr.hi * << 12 | msr.low >> 20. pal is msr.lo << 12 */ pah = ((msr.hi & 0xFF) << 12) | ((msr.lo >> 20) & 0xFFF); - /* we have the page address. Now make it a - * page-aligned address */ + + /* We have the page address. Now make it page-aligned. */ pah <<= 12; pal = msr.lo << 12; msr.hi = pah; msr.lo = pal; - msr.lo |= - GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET | - GLPCI_RC_LOWER_WC_SET; - printk(BIOS_DEBUG, + msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET | + GLPCI_RC_LOWER_WC_SET; + printk(BIOS_DEBUG, "GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n", - msr.lo, msr.hi); + msr.lo, msr.hi); msrnum = GLPCI_RC1; wrmsr(msrnum, msr); } - /* R2 - GLPCI settings for SMM space */ - msr.hi = - ((SMM_OFFSET + - (SMM_SIZE * 1024 - 1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT; + /* R2 - GLPCI settings for SMM space. */ + msr.hi = ((SMM_OFFSET + + (SMM_SIZE * 1024 - 1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT; msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT; msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET; - printk(BIOS_DEBUG, "GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", + printk(BIOS_DEBUG, "GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi); msrnum = GLPCI_RC2; wrmsr(msrnum, msr); - /* this is done elsewhere already, but it does no harm to do - * it more than once */ - /* write serialize memory hole to PCI. Need to to unWS when - * something is shadowed regardless of cachablility. */ - msr.lo = 0x021212121; /* cache disabled and write serialized */ - msr.hi = 0x021212121; /* cache disabled and write serialized */ + /* This is done elsewhere already, but it does no harm to do + * it more than once. + */ + /* Write serialize memory hole to PCI. Need to to unWS when + * something is shadowed regardless of cachablility. + */ + msr.lo = 0x021212121; /* Cache disabled and write serialized. */ + msr.hi = 0x021212121; /* Cache disabled and write serialized. */ msrnum = CPU_RCONF_A0_BF; wrmsr(msrnum, msr); @@ -373,8 +364,9 @@ msrnum = CPU_RCONF_E0_FF; wrmsr(msrnum, msr); - /* Set Non-Cacheable Read Only for NorthBound Transactions to - * Memory. The Enable bit is handled in the Shadow setup. */ + /* Set Non-Cacheable Read Only for NorthBound Transactions to + * Memory. The Enable bit is handled in the Shadow setup. + */ msrnum = GLPCI_A0_BF; msr.hi = 0x35353535; msr.lo = 0x35353535; @@ -390,20 +382,19 @@ msr.lo = 0x35353535; wrmsr(msrnum, msr); - /* Set WSREQ */ + /* Set WSREQ. */ msrnum = CPU_DM_CONFIG0; msr = rdmsr(msrnum); msr.hi &= ~(7 << DM_CONFIG0_UPPER_WSREQ_SHIFT); - /* reduce to 1 for safe mode */ + /* Reduce to 1 for safe mode. */ msr.hi |= 2 << DM_CONFIG0_UPPER_WSREQ_SHIFT; wrmsr(msrnum, msr); - /* The following settings will not work with a CS5530 southbridge */ - /* we are ignoring the 5530 case for now, and perhaps forever. */ + /* The following settings will not work with a CS5530 southbridge. + * We are ignoring the CS5530 case for now, and perhaps forever. + */ - /* */ /* 553x NB Init */ - /* */ /* Arbiter setup */ enable_preempt = @@ -424,9 +415,9 @@ msrnum = GLPCI_CTRL; msr = rdmsr(msrnum); - /* (Out will be disabled in CPUBUG649 for < 2.0 parts .) */ - msr.lo |= GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET - | GLPCI_CTRL_LOWER_PCD_SET; + /* Out will be disabled in CPUBUG649 for < 2.0 parts. */ + msr.lo |= GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET | + GLPCI_CTRL_LOWER_PCD_SET; msr.lo |= GLPCI_CTRL_LOWER_LDE_SET; msr.lo &= ~(0x03 << GLPCI_CTRL_LOWER_IRFC_SHIFT); @@ -454,11 +445,11 @@ /* Set GLPCI Latency Timer */ msrnum = GLPCI_CTRL; msr = rdmsr(msrnum); - /* Change once 1.x is gone */ + /* Change once 1.x is gone. */ msr.hi |= 0x1F << GLPCI_CTRL_UPPER_LAT_SHIFT; wrmsr(msrnum, msr); - /* GLPCI_SPARE */ + /* GLPCI_SPARE */ msrnum = GLPCI_SPARE; msr = rdmsr(msrnum); msr.lo &= ~0x7; @@ -470,11 +461,11 @@ } /** - * Enable Clock Gating in ALL MSRs which relate to clocks. - */ + * Enable Clock Gating in ALL MSRs which relate to clocks. + */ static void clock_gating_init(void) { - struct msr msr; + struct msr msr; struct msrinit *gating = clock_gating_default; int i; @@ -482,18 +473,17 @@ msr = rdmsr(gating->msrnum); msr.hi |= gating->msr.hi; msr.lo |= gating->msr.lo; - wrmsr(gating->msrnum, msr); // MSR - See the table above + wrmsr(gating->msrnum, msr); /* MSR - See table above. */ gating += 1; } - } /** - * Set all Geode Link Priority register as determined by the - */ + * Set all GeodeLink priority registers as determined by the TODO. + */ static void geode_link_priority(void) { - struct msr msr; + struct msr msr; struct msrinit *prio = geode_link_priority_table; int i; @@ -502,74 +492,78 @@ msr.hi |= prio->msr.hi; msr.lo &= ~0xfff; msr.lo |= prio->msr.lo; - wrmsr(prio->msrnum, msr); // MSR - See the table above + wrmsr(prio->msrnum, msr); /* MSR - See table above. */ prio += 1; } } /** - * Get the GLIU0 shadow register settings - * If the set_shadow function is used then all shadow descriptors - * will stay sync'ed. + * Get the GLIU0 shadow register settings. + * + * If the set_shadow() function is used then all shadow descriptors + * will stay sync'ed. + * + * @return TODO */ static u64 get_shadow(void) { - struct msr msr; + struct msr msr; msr = rdmsr(MSR_GLIU0_SHADOW); return (((u64) msr.hi) << 32) | msr.lo; } /** - * Set the cache RConf registers for the memory hole. - * Keeps all cache shadow descriptors sync'ed. - * This is part of the PCI lockup solution - * @param Hi the high 32 bits of the msr setting - * @param lo The low 32 bits of the msr setting + * Set the cache RConf registers for the memory hole. + * + * Keeps all cache shadow descriptors sync'ed. + * This is part of the PCI lockup solution. + * + * @param shadowHi The high 32 bits of the msr setting. + * @param shadowLo The low 32 bits of the msr setting. */ static void set_shadowRCONF(u32 shadowHi, u32 shadowLo) { - - // ok this is whacky bit translation time. + /* Ok, this is whacky bit translation time. */ int bit; u8 shadowByte; - struct msr msr = { 0, 0 }; + struct msr msr = { 0, 0 }; shadowByte = (u8) (shadowLo >> 16); - // load up D000 settings in edx. + /* Load up D000 settings in edx. */ for (bit = 8; (bit > 4); bit--) { msr.hi <<= 8; - msr.hi |= 1; // cache disable PCI/Shadow memory + msr.hi |= 1; /* Cache disable PCI/Shadow memory. */ if (shadowByte && (1 << bit)) - msr.hi |= 0x20; // write serialize PCI memory + msr.hi |= 0x20; /* Write serialize PCI memory. */ } - // load up C000 settings in eax. - for (; bit; bit--) { + /* Load up C000 settings in eax. */ + for (/* Nothing */; bit; bit--) { msr.lo <<= 8; - msr.lo |= 1; // cache disable PCI/Shadow memory + msr.lo |= 1; /* Cache disable PCI/Shadow memory. */ if (shadowByte && (1 << bit)) - msr.lo |= 0x20; // write serialize PCI memory + msr.lo |= 0x20; /* Write serialize PCI memory. */ } wrmsr(CPU_RCONF_C0_DF, msr); shadowByte = (u8) (shadowLo >> 24); - // load up F000 settings in edx. + /* Load up F000 settings in edx. */ for (bit = 8; (bit > 4); bit--) { msr.hi <<= 8; - msr.hi |= 1; // cache disable PCI/Shadow memory + msr.hi |= 1; /* Cache disable PCI/Shadow memory. */ if (shadowByte && (1 << bit)) - msr.hi |= 0x20; // write serialize PCI memory + msr.hi |= 0x20; /* Write serialize PCI memory. */ } - // load up E000 settings in eax. - for (; bit; bit--) { + /* Load up E000 settings in eax. */ + for (/* Nothing */; bit; bit--) { msr.lo <<= 8; - msr.lo |= 1; // cache disable PCI/Shadow memory + msr.lo |= 1; /* Cache disable PCI/Shadow memory. */ if (shadowByte && (1 << bit)) - msr.lo |= 0x20; // write serialize PCI memory + msr.lo |= 0x20; /* write serialize PCI memory. */ } wrmsr(CPU_RCONF_E0_FF, msr); @@ -577,15 +571,17 @@ /** * Set the GLPCI registers for the memory hole. + * * Keeps all cache shadow descriptors sync'ed. - * @param shadowhi the high 32 bits of the msr setting - * @param shadowlo The low 32 bits of the msr setting - */ + * + * @param shadowhi The high 32 bits of the msr setting. + * @param shadowlo The low 32 bits of the msr setting. + */ static void set_shadowGLPCI(u32 shadowhi, u32 shadowlo) { - struct msr msr; + struct msr msr; -// Set the Enable Register. + /* Set the Enable register. */ msr = rdmsr(GLPCI_REN); msr.lo &= 0xFFFF00FF; msr.lo |= ((shadowlo & 0xFFFF0000) >> 8); @@ -593,14 +589,17 @@ } /** - * Set the GLIU SC register settings. Scans descriptor tables for - * SC_SHADOW. Keeps all shadow descriptors sync'ed. - * @param shadowSettings Shadow register settings + * Set the GLIU SC register settings. + * + * Scans descriptor tables for SC_SHADOW. + * Keeps all shadow descriptors sync'ed. + * + * @param shadowSettings Shadow register settings. */ static void set_shadow(u64 shadowSettings) { int i; - struct msr msr; + struct msr msr; struct gliutable *pTable; u32 shadowLo, shadowHi; @@ -609,66 +608,70 @@ set_shadowRCONF(shadowHi, shadowLo); set_shadowGLPCI(shadowHi, shadowLo); - + for (i = 0; gliutables[i]; i++) { for (pTable = gliutables[i]; pTable->desc_type != GL_END; pTable++) { if (pTable->desc_type == SC_SHADOW) { - msr = rdmsr(pTable->desc_name); msr.lo = (u32) shadowSettings; - /* maintain PDID in upper EDX*/ - msr.hi &= 0xFFFF0000; + /* Maintain PDID in upper EDX. */ + msr.hi &= 0xFFFF0000; msr.hi |= - ((u32) (shadowSettings >> 32)) & - 0x0000FFFF; - // MSR - See the table above + ((u32) (shadowSettings >> 32)) & 0x0000FFFF; + /* MSR - See the table above. */ wrmsr(pTable->desc_name, msr); } } } } +/** + * TODO. + */ static void rom_shadow_settings(void) { + u64 shadowSettings = get_shadow(); - u64 shadowSettings = get_shadow(); - // Disable read & writes + /* Disable read & writes. */ shadowSettings &= (u64) 0xFFFF00000000FFFFULL; - // Enable reads for F0000-FFFFF + + /* Enable reads for F0000-FFFFF. */ shadowSettings |= (u64) 0x00000000F0000000ULL; - // Enable rw for C0000-CFFFF + + /* Enable read & writes for C0000-CFFFF. */ shadowSettings |= (u64) 0x0000FFFFFFFF0000ULL; + set_shadow(shadowSettings); } /** + * Set up RCONF_DEFAULT and any other RCONF registers needed. * - * - * Set up RCONF_DEFAULT and any other RCONF registers needed - * - * DEVRC_RCONF_DEFAULT: - * ROMRC(63:56) = 04h write protect ROMBASE - * ROMBASE(36:55) = 0FFFC0h Top of PCI/bottom of rom chipselect area - * DEVRC(35:28) = 39h cache disabled in PCI memory + WS bit on - + Write Combine + write burst. - * SYSTOP(27:8) = top of system memory - * SYSRC(7:0) = 0 writeback, can set to 08h to make writethrough - * - */ -#define SYSMEM_RCONF_WRITETHROUGH 8 -#define DEVRC_RCONF_DEFAULT 0x21 -#define ROMBASE_RCONF_DEFAULT 0xFFFC0000 -#define ROMRC_RCONF_DEFAULT 0x25 + * DEVRC_RCONF_DEFAULT: + * ROMRC(63:56) = 0x04 Write protect ROMBASE + * ROMBASE(36:55) = 0x0FFFC0 Top of PCI/bottom of ROM chipselect area + * DEVRC(35:28) = 0x39 Cache disabled in PCI memory + WS bit on + * Write Combine + write burst. + * SYSTOP(27:8) = top of system memory + * SYSRC(7:0) = 0 Writeback, can set to 0x08 to make writethrough + */ +#define SYSMEM_RCONF_WRITETHROUGH 8 +#define DEVRC_RCONF_DEFAULT 0x21 +#define ROMBASE_RCONF_DEFAULT 0xFFFC0000 +#define ROMRC_RCONF_DEFAULT 0x25 +/** + * TODO. + */ static void enable_L1_cache(void) { - struct gliutable *gl = 0; + struct gliutable *gl = NULL; int i; - struct msr msr; + struct msr msr; u8 SysMemCacheProp; - /* Locate SYSMEM entry in GLIU0table */ + /* Locate SYSMEM entry in GLIU0table. */ for (i = 0; gliu0table[i].desc_name != GL_END; i++) { if (gliu0table[i].desc_type == R_SYSMEM) { gl = &gliu0table[i]; @@ -676,43 +679,46 @@ } } if (gl == 0) { - post_code(0xCE); /* POST_RCONFInitError */ - while (1) ; + post_code(POST_RCONFInitError); + while (1); /* TODO: Should be hlt()? */ } + // sysdescfound: msr = rdmsr(gl->desc_name); - /* 20 bit address - The bottom 12 bits go into bits 20-31 in eax, the + /* 20 bit address - The bottom 12 bits go into bits 20-31 in eax, the * top 8 bits go into 0-7 of edx. */ msr.lo = (msr.lo & 0xFFFFFF00) | (msr.hi & 0xFF); msr.lo = ((msr.lo << 12) | (msr.lo >> 20)) & 0x000FFFFF; msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT; // 8 - // Set Default SYSMEM region properties - // NOT writethrough == writeback 8 (or ~8) + /* Set Default SYSMEM region properties. + * NOT writethrough == writeback 8 (or ~8) + */ msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH; - // Set PCI space cache properties - // setting is split betwwen hi and lo... + /* Set PCI space cache properties. + * Setting is split between hi and lo... + */ msr.hi = (DEVRC_RCONF_DEFAULT >> 4); msr.lo |= (DEVRC_RCONF_DEFAULT << 28); - // Set the ROMBASE. This is usually FFFC0000h + /* Set the ROMBASE. This is usually 0xFFFC0000. */ msr.hi |= (ROMBASE_RCONF_DEFAULT >> 12) << RCONF_DEFAULT_UPPER_ROMBASE_SHIFT; - // Set ROMBASE cache properties. + /* Set ROMBASE cache properties. */ msr.hi |= ((ROMRC_RCONF_DEFAULT >> 8) | (ROMRC_RCONF_DEFAULT << 24)); - // now program RCONF_DEFAULT + /* Now program RCONF_DEFAULT. */ wrmsr(CPU_RCONF_DEFAULT, msr); printk(BIOS_DEBUG, "CPU_RCONF_DEFAULT (1808): 0x%08X:0x%08X\n", msr.hi, - msr.lo); + msr.lo); - // RCONF_BYPASS: Cache tablewalk properties and - // SMM/DMM header access properties. - // Set to match system memory cache properties. + /* RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access + * properties. Set to match system memory cache properties. + */ msr = rdmsr(CPU_RCONF_DEFAULT); SysMemCacheProp = (u8) (msr.lo & 0xFF); msr = rdmsr(CPU_RCONF_BYPASS); @@ -720,37 +726,37 @@ (msr.lo & 0xFFFF0000) | (SysMemCacheProp << 8) | SysMemCacheProp; wrmsr(CPU_RCONF_BYPASS, msr); - printk(BIOS_DEBUG, "CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", + printk(BIOS_DEBUG, "CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", msr.hi, msr.lo); } -/** - * Enable the L2 cache MSRs. - */ +/** + * Enable the L2 cache MSRs. + */ static void enable_L2_cache(void) { - struct msr msr; + struct msr msr; /* Instruction Memory Configuration register - * set EBE bit, required when L2 cache is enabled + * set EBE bit, required when L2 cache is enabled. */ msr = rdmsr(CPU_IM_CONFIG); msr.lo |= 0x400; wrmsr(CPU_IM_CONFIG, msr); - /* Data Memory Subsystem Configuration register - * set EVCTONRPL bit, required when L2 cache is enabled in victim mode + /* Data Memory Subsystem Configuration register. Set EVCTONRPL bit, + * required when L2 cache is enabled in victim mode. */ msr = rdmsr(CPU_DM_CONFIG0); msr.lo |= 0x4000; wrmsr(CPU_DM_CONFIG0, msr); - /* invalidate L2 cache */ + /* Invalidate L2 cache. */ msr.hi = 0x00; msr.lo = 0x10; wrmsr(CPU_BC_L2_CONF, msr); - /* Enable L2 cache */ + /* Enable L2 cache. */ msr.hi = 0x00; msr.lo = 0x0f; wrmsr(CPU_BC_L2_CONF, msr); @@ -763,31 +769,37 @@ #define CONFIG_VIDEO_MB 8 #endif -/** - * set up all LX cache registers, L1, L2, and x86. - */ +/** + * Set up all LX cache registers, L1, L2, and x86. + */ static void setup_lx_cache(void) { - struct msr msr; + struct msr msr; enable_L1_cache(); enable_L2_cache(); - // Make sure all INVD instructions are treated as WBINVD. We do this - // because we've found some programs which require this behavior. + /* Make sure all INVD instructions are treated as WBINVD. We do this + * because we've found some programs which require this behavior. + */ msr = rdmsr(CPU_DM_CONFIG0); msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET; wrmsr(CPU_DM_CONFIG0, msr); enable_cache(); - __asm__("wbinvd\n"); + __asm__("wbinvd\n"); /* TODO: Use wbinvd() function? */ } +/** + * TODO. + * + * @return TODO. + */ u32 get_systop(void) { - struct gliutable *gl = 0; + struct gliutable *gl = NULL; u32 systop; - struct msr msr; + struct msr msr; int i; for (i = 0; gliu0table[i].desc_name != GL_END; i++) { @@ -798,45 +810,44 @@ } if (gl) { msr = rdmsr(gl->desc_name); - systop = ((msr.hi & 0xFF) << 24) | - ((msr.lo & 0xFFF00000) >> 8); + systop = ((msr.hi & 0xFF) << 24) | ((msr.lo & 0xFFF00000) >> 8); systop += 0x1000; /* 4K */ } else { systop = ((sizeram() - CONFIG_VIDEO_MB) * 1024) - SMM_SIZE - 1024; } + return systop; } -/** northbridge_init_early Do all the Nasty Bits that have to - * happen. These can be done once memory is up, but before much else - * is done. So we do them in Phase 2. - */ +/** + * Do all the Nasty Bits that have to happen. + * + * These can be done once memory is up, but before much else is done. + * So we do them in phase 2. + */ void northbridge_init_early(void) { - struct msr msr; int i; + struct msr msr; + printk(BIOS_DEBUG, "Enter %s\n", __FUNCTION__); for (i = 0; gliutables[i]; i++) GLIUInit(gliutables[i]); - /* Now that the descriptor to memory is set up. */ - /* The memory controller needs one read to synch its lines - * before it can be used. + /* Now that the descriptor to memory is set up, the memory controller + * needs one read to synch it's lines before it can be used. */ i = *(int *)0; geode_link_priority(); - setup_lx_cache(); - rom_shadow_settings(); - GLPCI_init(); - clock_gating_init(); - __asm__ __volatile__("FINIT\n"); + __asm__ __volatile__("FINIT\n"); /* TODO: Create finit() function? */ + printk(BIOS_DEBUG, "Exit %s\n", __FUNCTION__); } Modified: LinuxBIOSv3/northbridge/amd/geodelx/raminit.c =================================================================== --- LinuxBIOSv3/northbridge/amd/geodelx/raminit.c 2007-07-07 21:18:47 UTC (rev 438) +++ LinuxBIOSv3/northbridge/amd/geodelx/raminit.c 2007-07-08 00:19:26 UTC (rev 439) @@ -32,16 +32,19 @@ #include <amd_geodelx.h> #include <southbridge/amd/cs5536/cs5536.h> -static const u8 num_col_addr[] = { - 0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07, - 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F +static const u8 num_col_addr[] = { + 0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, }; /** - * Auto-detect, using SPD, the DIMM size. It's the usual magic, with - * all the usual failiure points that can happen. - * @param dimm -- The SMBus address of the DIMM - */ + * Auto-detect, using SPD, the DIMM size. It's the usual magic, with + * all the usual failure points that can happen. + * + * @param dimm TODO + * @param dimm0 The SMBus address of DIMM 0 (mainboard-dependent). + * @param dimm1 The SMBus address of DIMM 1 (mainboard-dependent). + */ static void auto_size_dimm(unsigned int dimm, u8 dimm0, u8 dimm1) { u32 dimm_setting; @@ -51,13 +54,10 @@ dimm_setting = 0; - /* Check that we have a dimm */ - if (smbus_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF) { + /* Check that we have a DIMM. */ + if (smbus_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF) return; - } - /* Field: Module Banks per DIMM */ - /* EEPROM byte usage: (5) Number of DIMM Banks */ spd_byte = smbus_read_byte(dimm, SPD_NUM_DIMM_BANKS); if ((MIN_MOD_BANKS > spd_byte) && (spd_byte > MAX_MOD_BANKS)) { printk(BIOS_EMERG, "Number of module banks not compatible\n"); @@ -66,8 +66,6 @@ } dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT; - /* Field: Banks per SDRAM device */ - /* EEPROM byte usage: (17) Number of Banks on SDRAM Device */ spd_byte = smbus_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM); if ((MIN_DEV_BANKS > spd_byte) && (spd_byte > MAX_DEV_BANKS)) { printk(BIOS_EMERG, "Number of device banks not compatible\n"); @@ -76,59 +74,58 @@ } dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT; - /* Field: DIMM size - *; EEPROM byte usage: (3) Number or Row Addresses - *; (4) Number of Column Addresses - *; (5) Number of DIMM Banks - *; (31) Module Bank Density - *; Size = Module Density * Module Banks - */ if ((smbus_read_byte(dimm, SPD_NUM_ROWS) & 0xF0) || (smbus_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) { - printk(BIOS_EMERG, "Assymetirc DIMM not compatible\n"); + printk(BIOS_EMERG, "Asymmetric DIMM not compatible\n"); post_code(ERROR_UNSUPPORTED_DIMM); hlt(); } + /* Size = Module Density * Module Banks */ dimm_size = smbus_read_byte(dimm, SPD_BANK_DENSITY); - /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */ + /* Align so 1 GB (bit 0) is bit 8. This is a little weird to get gcc + * to not optimize this out. + */ dimm_size |= (dimm_size << 8); - /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */ + /* And off 2 GB DIMM size: not supported and the 1 GB size we just + * moved up to bit 8 as well as all the extra on top. + */ dimm_size &= 0x01FC; - /* Module Density * Module Banks */ - /* shift to multiply by # DIMM banks */ + /* Module Density * Module Banks */ + /* Shift to multiply by the number of DIMM banks. */ dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; dimm_size = __builtin_ctz(dimm_size); - if (dimm_size > 8) { /* 8 is 1GB only support 1GB per DIMM */ + if (dimm_size > 8) { /* 8 is 1 GB only support 1 GB per DIMM */ printk(BIOS_EMERG, "Only support up to 1 GB per DIMM\n"); post_code(ERROR_DENSITY_DIMM); hlt(); } dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT; - /* Field: PAGE size - * EEPROM byte usage: (4) Number of Column Addresses - * PageSize = 2^# Column Addresses * Data width in bytes (should be 8bytes for a normal DIMM) - * - * But this really works by magic. - *If ma[12:0] is the memory address pins, and pa[12:0] is the physical column address - *that MC generates, here is how the MC assigns the pa onto the ma pins: - * - *ma 12 11 10 09 08 07 06 05 04 03 02 01 00 - *------------------------------------------- - *pa 09 08 07 06 05 04 03 (7 col addr bits = 1K page size) - *pa 10 09 08 07 06 05 04 03 (8 col addr bits = 2K page size) - *pa 11 10 09 08 07 06 05 04 03 (9 col addr bits = 4K page size) - *pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size) - *pa 13 AP 12 11 10 09 08 07 06 05 04 03 (11 col addr bits = 16K page size) - *pa 14 13 AP 12 11 10 09 08 07 06 05 04 03 (12 col addr bits = 32K page size) - * *AP=autoprecharge bit - * - *Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes), - *so lower 3 address bits are dont_cares.So from the table above, - *it's easier to see what the old code is doing: if for example,#col_addr_bits=7(06h), - *it adds 3 to get 10, then does 2^10=1K. Get it? - */ + /* PageSize = 2 ^ (number of column addresses) * data width in bytes + * (should be 8 bytes for a normal DIMM) + * + * If ma[12:0] is the memory address pins, and pa[12:0] is the + * physical column address that the memory controller (MC) generates, + * here is how the MC assigns the pa onto the ma pins: + * + * ma 12 11 10 09 08 07 06 05 04 03 02 01 00 + * ------------------------------------------- + * pa 09 08 07 06 05 04 03 (7 col addr bits = 1K page size) + * pa 10 09 08 07 06 05 04 03 (8 col addr bits = 2K page size) + * pa 11 10 09 08 07 06 05 04 03 (9 col addr bits = 4K page size) + * pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size) + * pa 13 AP 12 11 10 09 08 07 06 05 04 03 (11 col addr bits = 16K page size) + * pa 14 13 AP 12 11 10 09 08 07 06 05 04 03 (12 col addr bits = 32K page size) + * + * (AP = autoprecharge bit) + * + * Remember that pa[2:0] are zeroed out since it's a 64-bit data bus + * (8 bytes), so lower 3 address bits are dont_cares. So from the + * table above, it's easier to see what the old code is doing: if for + * example, #col_addr_bits = 7 (06h), it adds 3 to get 10, then does + * 2^10=1K. Get it? + */ spd_byte = num_col_addr[smbus_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF]; if (spd_byte > MAX_COL_ADDR) { @@ -137,10 +134,12 @@ hlt(); } spd_byte -= 7; - if (spd_byte > 5) { /* if the value is above 6 it means >12 address lines */ - spd_byte = 7; /* which means >32k so set to disabled */ + /* If the value is above 6 it means >12 address lines... */ + if (spd_byte > 5) { + spd_byte = 7; /* ...which means >32k so set to disabled. */ } - dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0=1k,1=2k,2=4k,etc */ + /* 0 = 1k, 1 = 2k, 2 = 4k, etc. */ + dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; msr = rdmsr(MC_CF07_DATA); if (dimm == dimm0) { @@ -153,11 +152,15 @@ wrmsr(MC_CF07_DATA, msr); } -/** Try to compute the max DDR clock rate. The only bad news here is that if you have got a geode link - * speed that is too fast, you are going to pay for it: the system will hlt! - * @param dimm0 dimm0 SMBus address - * @param dimm1 dimm1 SMBus address - */ +/** + * Try to compute the max. DDR clock rate. + * + * The only bad news here is that if you have got a GeodeLink speed that is + * too fast, you are going to pay for it: the system will hlt! + * + * @param dimm0 The SMBus address of DIMM 0 (mainboard-dependent). + * @param dimm1 The SMBus address of DIMM 1 (mainboard-dependent). + */ static void check_ddr_max(u8 dimm0, u8 dimm1) { u8 spd_byte0, spd_byte1; @@ -165,32 +168,32 @@ /* PC133 identifier */ spd_byte0 = smbus_read_byte(dimm0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); - if (spd_byte0 == 0xFF) { + if (spd_byte0 == 0xFF) spd_byte0 = 0; - } spd_byte1 = smbus_read_byte(dimm1, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); - if (spd_byte1 == 0xFF) { + if (spd_byte1 == 0xFF) spd_byte1 = 0; + + /* I don't think you need this check. */ +#if 0 + if (spd_byte0 < 0xA0 || spd_byte0 < 0xA0) { + printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink speed\n"); + post_code(POST_PLL_MEM_FAIL); + hlt(); } +#endif - /* I don't think you need this check. - if (spd_byte0 < 0xA0 || spd_byte0 < 0xA0){ - printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n"); - post_code(POST_PLL_MEM_FAIL); - hlt(); - } */ - - /* Use the slowest DIMM */ + /* Use the slowest DIMM. */ if (spd_byte0 < spd_byte1) { spd_byte0 = spd_byte1; } - /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ + /* Turn SPD ns time into MHz. Check what the asm does to this math. */ speed = 2 * ((10000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F)))); - /* current speed > max speed? */ + /* Current speed > max speed? */ if (geode_link_speed() > speed) { - printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n"); + printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink speed\n"); post_code(POST_PLL_MEM_FAIL); hlt(); } @@ -198,11 +201,14 @@ const u16 REFRESH_RATE[] = { 15, 3, 7, 31, 62, 125 }; /* ns */ -/** - * compute a refresh rate. You have to read both dimms and take the one that requires a faster rate. - * @param dimm0 dimm0 SMBus address - * @param dimm1 dimm1 SMBus address - */ +/** + * Compute a refresh rate. + * + * You have to read both DIMMs and take the one that requires a faster rate. + * + * @param dimm0 The SMBus address of DIMM 0 (mainboard-dependent). + * @param dimm1 The SMBus address of DIMM 1 (mainboard-dependent). + */ static void set_refresh_rate(u8 dimm0, u8 dimm1) { u8 spd_byte0, spd_byte1; @@ -223,40 +229,41 @@ } rate1 = REFRESH_RATE[spd_byte1]; - /* Use the faster rate (lowest number) */ + /* Use the faster rate (lowest number). */ if (rate0 > rate1) { rate0 = rate1; } msr = rdmsr(MC_CF07_DATA); - msr.lo |= ((rate0 * (geode_link_speed() / 2)) / 16) - << CF07_LOWER_REF_INT_SHIFT; + msr.lo |= ((rate0 * (geode_link_speed() / 2)) / 16) + << CF07_LOWER_REF_INT_SHIFT; wrmsr(MC_CF07_DATA, msr); } -const u8 CASDDR[] = { 5, 5, 2, 6, 3, 7, 4, 0 }; /* 1(1.5), 1.5, 2, 2.5, 3, 3.5, 4, 0 */ +/* 1(1.5), 1.5, 2, 2.5, 3, 3.5, 4, 0 */ +const u8 CASDDR[] = { 5, 5, 2, 6, 3, 7, 4, 0 }; /** - * Compute the CAS rate. - * EEPROM byte usage: (18) SDRAM device attributes - CAS latency - * EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5 - * EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1 - * - * The CAS setting is based on the information provided in each DIMMs SPD. - * The speed at which a DIMM can run is described relative to the slowest - * CAS the DIMM supports. Each speed for the relative CAS settings is - * checked that it is within the GeodeLink speed. If it isn't within the GeodeLink - * speed, the CAS setting is removed from the list of good settings for - * the DIMM. This is done for both DIMMs and the lists are compared to - * find the lowest common CAS latency setting. If there are no CAS settings - * in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt. - * Result is that we will set fastest CAS Latency based on GeodeLink speed - * and SPD information. - * - * @param dimm0 dimm0 SMBus address - * @param dimm1 dimm1 SMBus address - * - */ + * Compute the CAS rate. + * + * The CAS setting is based on the information provided in each DIMMs SPD. + * + * The speed at which a DIMM can run is described relative to the slowest + * CAS the DIMM supports. Each speed for the relative CAS settings is + * checked that it is within the GeodeLink speed. If it isn't within the + * GeodeLink speed, the CAS setting is removed from the list of good settings + * for the DIMM. + * + * This is done for both DIMMs and the lists are compared to find the lowest + * common CAS latency setting. If there are no CAS settings + * in common we output a ERROR_DIFF_DIMMS (0x78) POST code and halt. + * + * Result is that we will set fastest CAS latency based on GeodeLink speed + * and SPD information. + * + * @param dimm0 The SMBus address of DIMM 0 (mainboard-dependent). + * @param dimm1 The SMBus address of DIMM 1 (mainboard-dependent). + */ static void set_cas(u8 dimm0, u8 dimm1) { u16 glspeed, dimm_speed; @@ -265,72 +272,78 @@ glspeed = geode_link_speed(); - /************************** dimm0 **********************************/ + /* DIMM 0 */ casmap0 = smbus_read_byte(dimm0, SPD_ACCEPTABLE_CAS_LATENCIES); if (casmap0 != 0xFF) { - /* IF -.5 timing is supported, check -.5 timing > GeodeLink */ + /* If -.5 timing is supported, check -.5 timing > GeodeLink. */ + /* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5 */ spd_byte = smbus_read_byte(dimm0, SPD_SDRAM_CYCLE_TIME_2ND); if (spd_byte != 0) { - /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ + /* Turn SPD ns time into MHz. Check what the asm does + * to this math. + */ dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); if (dimm_speed >= glspeed) { - /* IF -1 timing is supported, check -1 timing > GeodeLink */ + /* If -1 timing is supported, check -1 timing > GeodeLink. */ + /* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1 */ spd_byte = smbus_read_byte(dimm0, SPD_SDRAM_CYCLE_TIME_3RD); if (spd_byte != 0) { - /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ + /* Turn SPD ns time into MHz. Check what the asm does to this math. */ dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); if (dimm_speed <= glspeed) { - /* set we can use -.5 timing but not -1 */ + /* Set we can use -.5 timing but not -1. */ spd_byte = 31 - __builtin_clz((u32) casmap0); - /* just want bits in the lower byte since we have to cast to a 32 */ + /* Just want bits in the lower byte since we have to cast to a 32. */ casmap0 &= 0xFF << (--spd_byte); } - } /*MIN_CYCLE_10 !=0 */ + } /* MIN_CYCLE_10 != 0 */ } else { - /* Timing_05 < GLspeed, can't use -.5 or -1 timing */ + /* Timing_05 < GLspeed, can't use -.5 or -1 timing. */ spd_byte = 31 - __builtin_clz((u32) casmap0); - /* just want bits in the lower byte since we have to cast to a 32 */ + /* Just want bits in the lower byte since we have to cast to a 32. */ casmap0 &= 0xFF << (spd_byte); } - } /*MIN_CYCLE_05 !=0 */ + } /* MIN_CYCLE_05 != 0 */ } else { /* No DIMM */ casmap0 = 0; } - /************************** dimm1 **********************************/ + /* DIMM 1 */ casmap1 = smbus_read_byte(dimm1, SPD_ACCEPTABLE_CAS_LATENCIES); if (casmap1 != 0xFF) { - /* IF -.5 timing is supported, check -.5 timing > GeodeLink */ + /* If -.5 timing is supported, check -.5 timing > GeodeLink. */ + /* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5 */ spd_byte = smbus_read_byte(dimm1, SPD_SDRAM_CYCLE_TIME_2ND); if (spd_byte != 0) { - /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ + /* Turn SPD ns time into MHz. Check what the asm does to this math. */ dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); if (dimm_speed >= glspeed) { - /* IF -1 timing is supported, check -1 timing > GeodeLink */ + /* If -1 timing is supported, check -1 timing > GeodeLink. */ + /* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1 */ spd_byte = smbus_read_byte(dimm1, SPD_SDRAM_CYCLE_TIME_3RD); if (spd_byte != 0) { - /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ + /* Turn SPD ns time into MHz. Check what the asm does to this math. */ dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); if (dimm_speed <= glspeed) { - /* set we can use -.5 timing but not -1 */ + /* Set we can use -.5 timing but not -1. */ spd_byte = 31 - __builtin_clz((u32) casmap1); - /* just want bits in the lower byte since we have to cast to a 32 */ + /* Just want bits in the lower byte since we have to cast to a 32. */ casmap1 &= 0xFF << (--spd_byte); } - } /*MIN_CYCLE_10 !=0 */ + } /* MIN_CYCLE_10 != 0 */ } else { - /* Timing_05 < GLspeed, can't use -.5 or -1 timing */ + /* Timing_05 < GLspeed, can't use -.5 or -1 timing. */ spd_byte = 31 - __builtin_clz((u32) casmap1); - /* just want bits in the lower byte since we have to cast to a 32 */ + /* Just want bits in the lower byte since we have to cast to a 32. */ casmap1 &= 0xFF << (spd_byte); } - } /*MIN_CYCLE_05 !=0 */ + } /* MIN_CYCLE_05 != 0 */ } else { /* No DIMM */ casmap1 = 0; } - /********************* CAS_LAT MAP COMPARE ***************************/ + /* Compare CAS latencies. */ if (casmap0 == 0) { spd_byte = CASDDR[__builtin_ctz((u32) casmap1)]; } else if (casmap1 == 0) { @@ -338,7 +351,7 @@ } else if ((casmap0 &= casmap1)) { spd_byte = CASDDR[__builtin_ctz((u32) casmap0)]; } else { - printk(BIOS_EMERG, "DIMM CAS Latencies not compatible\n"); + printk(BIOS_EMERG, "DIMM CAS latencies not compatible\n"); post_code(ERROR_DIFF_DIMMS); hlt(); } @@ -349,12 +362,15 @@ wrmsr(MC_CF8F_DATA, msr); } -/** - * set latencies for DRAM. These are the famed ras and cas latencies. - * Take the one with the tightest requirements, and use that for both. - * @param dimm0 dimm0 SMBus address - * @param dimm1 dimm1 SMBus address - */ +/** + * Set latencies for DRAM. + * + * These are the famed RAS and CAS latencies. Take the one with the tightest + * requirements, and use that for both. + * + * @param dimm0 The SMBus address of DIMM 0 (mainboard-dependent). + * @param dimm1 The SMBus address of DIMM 1 (mainboard-dependent). + */ static void set_latencies(u8 dimm0, u8 dimm1) { u32 memspeed, dimm_setting; @@ -367,36 +383,29 @@ /* MC_CF8F setup */ /* tRAS */ spd_byte0 = smbus_read_byte(dimm0, SPD_tRAS); - if (spd_byte0 == 0xFF) { + if (spd_byte0 == 0xFF) spd_byte0 = 0; - } spd_byte1 = smbus_read_byte(dimm1, SPD_tRAS); - if (spd_byte1 == 0xFF) { + if (spd_byte1 == 0xFF) spd_byte1 = 0; - } - if (spd_byte0 < spd_byte1) { + if (spd_byte0 < spd_byte1) spd_byte0 = spd_byte1; - } /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */ spd_byte1 = (spd_byte0 * memspeed) / 1000; - if (((spd_byte0 * memspeed) % 1000)) { + if (((spd_byte0 * memspeed) % 1000)) ++spd_byte1; - } dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2PRE_SHIFT; /* tRP */ spd_byte0 = smbus_read_byte(dimm0, SPD_tRP); - if (spd_byte0 == 0xFF) { + if (spd_byte0 == 0xFF) spd_byte0 = 0; - } spd_byte1 = smbus_read_byte(dimm1, SPD_tRP); - if (spd_byte1 == 0xFF) { + if (spd_byte1 == 0xFF) spd_byte1 = 0; - } - if (spd_byte0 < spd_byte1) { + if (spd_byte0 < spd_byte1) spd_byte0 = spd_byte1; - } /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */ spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000; @@ -407,16 +416,13 @@ /* tRCD */ spd_byte0 = smbus_read_byte(dimm0, SPD_tRCD); - if (spd_byte0 == 0xFF) { + if (spd_byte0 == 0xFF) spd_byte0 = 0; - } spd_byte1 = smbus_read_byte(dimm1, SPD_tRCD); - if (spd_byte1 == 0xFF) { + if (spd_byte1 == 0xFF) spd_byte1 = 0; - } - if (spd_byte0 < spd_byte1) { + if (spd_byte0 < spd_byte1) spd_byte0 = spd_byte1; - } /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */ spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000; @@ -427,16 +433,13 @@ /* tRRD */ spd_byte0 = smbus_read_byte(dimm0, SPD_tRRD); - if (spd_byte0 == 0xFF) { + if (spd_byte0 == 0xFF) spd_byte0 = 0; - } spd_byte1 = smbus_read_byte(dimm1, SPD_tRRD); - if (spd_byte1 == 0xFF) { + if (spd_byte1 == 0xFF) spd_byte1 = 0; - } - if (spd_byte0 < spd_byte1) { + if (spd_byte0 < spd_byte1) spd_byte0 = spd_byte1; - } /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */ spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000; @@ -447,8 +450,8 @@ /* tRC = tRP + tRAS */ dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) + - ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07)) - << CF8F_LOWER_ACT2ACTREF_SHIFT; + ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07)) + << CF8F_LOWER_ACT2ACTREF_SHIFT; msr = rdmsr(MC_CF8F_DATA); msr.lo &= 0xF00000FF; @@ -459,33 +462,36 @@ /* MC_CF1017 setup */ /* tRFC */ spd_byte0 = smbus_read_byte(dimm0, SPD_tRFC); - if (spd_byte0 == 0xFF) { + if (spd_byte0 == 0xFF) spd_byte0 = 0; - } spd_byte1 = smbus_read_byte(dimm1, SPD_tRFC); - if (spd_byte1 == 0xFF) { + if (spd_byte1 == 0xFF) spd_byte1 = 0; - } - if (spd_byte0 < spd_byte1) { + if (spd_byte0 < spd_byte1) spd_byte0 = spd_byte1; - } if (spd_byte0) { /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */ spd_byte1 = (spd_byte0 * memspeed) / 1000; - if (((spd_byte0 * memspeed) % 1000)) { + if (((spd_byte0 * memspeed) % 1000)) ++spd_byte1; - } - } else { /* Not all SPDs have tRFC setting. Use this formula tRFC = tRC + 1 clk */ + } else { + /* Not all SPDs have tRFC setting. + * Use this formula: tRFC = tRC + 1 clk. + */ spd_byte1 = ((dimm_setting >> CF8F_LOWER_ACT2ACTREF_SHIFT) & 0x0F) + 1; } - dimm_setting = spd_byte1 << CF1017_LOWER_REF2ACT_SHIFT; /* note this clears the cf8f dimm setting */ + + /* Note: This clears the cf8f DIMM setting. */ + dimm_setting = spd_byte1 << CF1017_LOWER_REF2ACT_SHIFT; msr = rdmsr(MC_CF1017_DATA); msr.lo &= ~(0x1F << CF1017_LOWER_REF2ACT_SHIFT); msr.lo |= dimm_setting; wrmsr(MC_CF1017_DATA, msr); - /* tWTR: Set tWTR to 2 for 400MHz and above GLBUS (200Mhz mem) other wise it stay default(1) */ + /* tWTR: Set tWTR to 2 for 400 MHz and above GLBUS (200 Mhz mem) + * otherwise it stay default (1). + */ if (memspeed > 198) { msr = rdmsr(MC_CF1017_DATA); msr.lo &= ~(0x7 << CF1017_LOWER_WR_TO_RD_SHIFT); @@ -494,44 +500,46 @@ } } -/** - * Set the registers for drive, namely drive and fet strength. - * @param dimm0 dimm0 SMBus address - * @param dimm1 dimm1 SMBus address - */ +/** + * Set the registers for drive, namely drive and fet strength. + * + * @param dimm0 The SMBus address of DIMM 0 (mainboard-dependent). + * @param dimm1 The SMBus address of DIMM 1 (mainboard-dependent). + */ static void set_extended_mode_registers(u8 dimm0, u8 dimm1) { u8 spd_byte0, spd_byte1; struct msr msr; + spd_byte0 = smbus_read_byte(dimm0, SPD_DEVICE_ATTRIBUTES_GENERAL); - if (spd_byte0 == 0xFF) { + if (spd_byte0 == 0xFF) spd_byte0 = 0; - } spd_byte1 = smbus_read_byte(dimm1, SPD_DEVICE_ATTRIBUTES_GENERAL); - if (spd_byte1 == 0xFF) { + if (spd_byte1 == 0xFF) spd_byte1 = 0; - } spd_byte1 &= spd_byte0; msr = rdmsr(MC_CF07_DATA); - if (spd_byte1 & 1) { /* Drive Strength Control */ + if (spd_byte1 & 1) { + /* Drive Strength Control */ msr.lo |= CF07_LOWER_EMR_DRV_SET; } - if (spd_byte1 & 2) { /* FET Control */ + if (spd_byte1 & 2) { + /* FET Control */ msr.lo |= CF07_LOWER_EMR_QFC_SET; } wrmsr(MC_CF07_DATA, msr); } /** - * Debug function. Only used when test hardware is connected. - */ + * Debug function. Only used when test hardware is connected. + */ static void EnableMTest(void) { struct msr msr; msr = rdmsr(GLCP_DELAY_CONTROLS); - msr.hi &= ~(7 << 20); /* clear bits 54:52 */ + msr.hi &= ~(7 << 20); /* Clear bits 54:52. */ if (geode_link_speed() < 200) { msr.hi |= 2 << 20; } @@ -547,9 +555,10 @@ printk(BIOS_DEBUG, "Enabled MTest for TLA debug\n"); } -/** Set SDRAM registers that need to be set independent of SPD or even presence or absence of DIMMs - * in a slot. Parameters are ignored. - */ +/** + * Set SDRAM registers that need to be set independent of SPD or even + * presence or absence of DIMMs in a slot. Parameters are ignored. + */ void sdram_set_registers(void) { struct msr msr; @@ -570,20 +579,24 @@ msrnum = MC_CF07_DATA; msr = rdmsr(msrnum); msr.lo &= ~0xF0; - msr.lo |= 0x40; /* set refresh to 4SDRAM clocks */ + msr.lo |= 0x40; /* Set refresh to 4 SDRAM clocks. */ wrmsr(msrnum, msr); - /* Memory Interleave: Set HOI here otherwise default is LOI */ - /* msrnum = MC_CF8F_DATA; - msr = rdmsr(msrnum); - msr.hi |= CF8F_UPPER_HOI_LOI_SET; - wrmsr(msrnum, msr); */ + /* Memory Interleave: Set HOI here otherwise default is LOI. */ +#if 0 + msrnum = MC_CF8F_DATA; + msr = rdmsr(msrnum); + msr.hi |= CF8F_UPPER_HOI_LOI_SET; + wrmsr(msrnum, msr); +#endif } -/** Set SDRAM registers that need to are determined by SPD. - * @param dimm0 dimm0 SMBus address - * @param dimm1 dimm1 SMBus address - */ +/** + * Set SDRAM registers that need to be determined by SPD. + * + * @param dimm0 The SMBus address of DIMM 0 (mainboard-dependent). + * @param dimm1 The SMBus address of DIMM 1 (mainboard-dependent). + */ void sdram_set_spd_registers(u8 dimm0, u8 dimm1) { u8 spd_byte; @@ -591,15 +604,16 @@ post_code(POST_MEM_SETUP); spd_byte = smbus_read_byte(dimm0, SPD_MODULE_ATTRIBUTES); - /* Check DIMM is not Register and not Buffered DIMMs. */ + + /* Check DIMM is not Registered and not Buffered DIMMs. */ if ((spd_byte != 0xFF) && (spd_byte & 3)) { - printk(BIOS_EMERG, "dimm0 NOT COMPATIBLE\n"); + printk(BIOS_EMERG, "DIMM 0 NOT COMPATIBLE!\n"); post_code(ERROR_UNSUPPORTED_DIMM); hlt(); } spd_byte = smbus_read_byte(dimm1, SPD_MODULE_ATTRIBUTES); if ((spd_byte != 0xFF) && (spd_byte & 3)) { - printk(BIOS_EMERG, "dimm1 NOT COMPATIBLE\n"); + printk(BIOS_EMERG, "DIMM 1 NOT COMPATIBLE!\n"); post_code(ERROR_UNSUPPORTED_DIMM); hlt(); } @@ -609,79 +623,85 @@ /* Check that the memory is not overclocked. */ check_ddr_max(dimm0, dimm1); - /* Size the DIMMS */ - /* this is gross. It is an artifact of our move to parametes instead of #defines. FIX ME */ - /* the fix is trivial but I want to see it work first. */ + /* Size the DIMMS. + * This is gross. It is an artifact of our move to parametes instead of + * #defines. FIXME! The fix is trivial but I want to see it work first. + */ post_code(POST_MEM_SETUP3); auto_size_dimm(dimm0, dimm0, dimm1); post_code(POST_MEM_SETUP4); auto_size_dimm(dimm1, dimm0, dimm1); - /* Set CAS latency */ + /* Set CAS latency. */ post_code(POST_MEM_SETUP5); set_cas(dimm0, dimm1); - /* Set all the other latencies here (tRAS, tRP....) */ + /* Set all the other latencies here (tRAS, tRP...). */ set_latencies(dimm0, dimm1); - /* Set Extended Mode Registers */ + /* Set Extended Mode Registers. */ set_extended_mode_registers(dimm0, dimm1); - /* Set Memory Refresh Rate */ + /* Set Memory Refresh Rate. */ set_refresh_rate(dimm0, dimm1); - } /** - * enable the DRAMs. - * Section 6.1.3, LX processor databooks, BIOS Initialization Sequence - * Section 4.1.4, GX/CS5535 GeodeROM Porting guide - * Turn on MC/DIMM interface per JEDEC - * 1) Clock stabilizes > 200us - * 2) Assert CKE - * 3) Precharge All to put all banks into an idles state - * 4) EMRS to enable DLL - * 6) MRS w/ memory config & reset DLL set - * 7) Wait 200 clocks (2us) - * 8) Precharge All and 2 Auto refresh - * 9) MRS w/ memory config & reset DLL clear - * 8) DDR SDRAM ready for normal operation - * - * @param dimm0 dimm0 SMBus address - * @param dimm1 dimm1 SMBus address - */ + * Enable the DRAMs. + * + * Section 6.1.3, LX processor databooks, BIOS Initialization Sequence + * Section 4.1.4, GX/CS5535 GeodeROM Porting guide + * + * Turn on MC/DIMM interface per JEDEC: + * 1) Clock stabilizes > 200us + * 2) Assert CKE + * 3) Precharge All to put all banks into an idle state + * 4) EMRS to enable DLL + * 6) MRS w/ memory config & reset DLL set + * 7) Wait 200 clocks (2us) + * 8) Precharge All and 2 Auto refresh + * 9) MRS w/ memory config & reset DLL clear + * 8) DDR SDRAM ready for normal operation + * + * @param dimm0 The SMBus address of DIMM 0 (mainboard-dependent). + * @param dimm1 The SMBus address of DIMM 1 (mainboard-dependent). + */ void sdram_enable(u8 dimm0, u8 dimm1) { u32 i, msrnum; struct msr msr; - post_code(POST_MEM_ENABLE); // post_76h + post_code(POST_MEM_ENABLE); - /* Only enable MTest for TLA memory debug */ - /*EnableMTest(); */ + /* Only enable MTest for TLA memory debug. */ + /* EnableMTest(); */ - /* If both Page Size = "Not Installed" we have a problems and should halt. */ + /* If both Page Size = "Not Installed" we have a problem and + * should halt. + */ msr = rdmsr(MC_CF07_DATA); - if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) == - ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) { + if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | + (7 << CF07_UPPER_D0_PSZ_SHIFT))) == + ((7 << CF07_UPPER_D1_PSZ_SHIFT) | + (7 << CF07_UPPER_D0_PSZ_SHIFT))) { printk(BIOS_EMERG, "No memory in the system\n"); post_code(ERROR_NO_DIMMS); hlt(); } - /* Set CKEs */ + /* Set CKEs. */ msrnum = MC_CFCLK_DBUG; msr = rdmsr(msrnum); msr.lo &= ~(CFCLK_LOWER_MASK_CKE_SET0 | CFCLK_LOWER_MASK_CKE_SET1); wrmsr(msrnum, msr); - /* Force Precharge All on next command, EMRS */ + /* Force Precharge All on next command, EMRS. */ msrnum = MC_CFCLK_DBUG; msr = rdmsr(msrnum); msr.lo |= CFCLK_LOWER_FORCE_PRE_SET; wrmsr(msrnum, msr); - /* EMRS to enable DLL (pre-setup done in setExtendedModeRegisters) */ + /* EMRS to enable DLL (pre-setup done in setExtendedModeRegisters). */ msrnum = MC_CF07_DATA; msr = rdmsr(msrnum); msr.lo |= CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DDR_SET; @@ -689,13 +709,13 @@ msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DDR_SET); wrmsr(msrnum, msr); - /* Clear Force Precharge All */ + /* Clear Force Precharge All. */ msrnum = MC_CFCLK_DBUG; msr = rdmsr(msrnum); msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET; wrmsr(msrnum, msr); - /* MRS Reset DLL - set */ + /* MRS Reset DLL - set. */ msrnum = MC_CF07_DATA; msr = rdmsr(msrnum); msr.lo |= CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET; @@ -703,23 +723,23 @@ msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET); wrmsr(msrnum, msr); - /* 2us delay (200 clocks @ 200Mhz). We probably really don't - * need this but.... better safe. + /* 2us delay (200 clocks @ 200Mhz). We probably really don't need + * this but... better safe. + * + * Wait two 'port 61 ticks' (between 15us and 30us). + * This would be endless if the timer is stuck. */ - /* Wait 2 PORT61 ticks. between 15us and 30us */ - /* This would be endless if the timer is stuck. */ - while ((inb(0x61))) ; /* find the first edge */ - while (!(~inb(0x61))) ; + while ((inb(0x61))); /* Find the first edge. */ + while (!(~inb(0x61))); - /* Force Precharge All on the next command, auto-refresh */ + /* Force Precharge All on the next command, auto-refresh. */ msrnum = MC_CFCLK_DBUG; msr = rdmsr(msrnum); msr.lo |= CFCLK_LOWER_FORCE_PRE_SET; wrmsr(msrnum, msr); - /* Manually AUTO refresh #1 */ - /* If auto refresh was not enabled above we would need to do 8 - * refreshes to prime the pump before these 2. + /* Manually AUTO refresh #1. If auto refresh was not enabled above we + * would need to do 8 refreshes to prime the pump before these 2. */ msrnum = MC_CF07_DATA; msr = rdmsr(msrnum); @@ -728,14 +748,15 @@ msr.lo &= ~CF07_LOWER_REF_TEST_SET; wrmsr(msrnum, msr); - /* Clear Force Precharge All */ + /* Clear Force Precharge All. */ msrnum = MC_CFCLK_DBUG; msr = rdmsr(msrnum); msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET; wrmsr(msrnum, msr); - /* Manually AUTO refresh */ - /* The MC should insert the right delay between the refreshes */ + /* Manually AUTO refresh. + * The MC should insert the right delay between the refreshes. + */ msrnum = MC_CF07_DATA; msr = rdmsr(msrnum); msr.lo |= CF07_LOWER_REF_TEST_SET; @@ -743,7 +764,7 @@ msr.lo &= ~CF07_LOWER_REF_TEST_SET; wrmsr(msrnum, msr); - /* MRS Reset DLL - clear */ + /* MRS Reset DLL - clear. */ msrnum = MC_CF07_DATA; msr = rdmsr(msrnum); msr.lo |= CF07_LOWER_PROG_DRAM_SET; @@ -751,13 +772,13 @@ msr.lo &= ~CF07_LOWER_PROG_DRAM_SET; wrmsr(msrnum, msr); - /* Allow MC to tristate during idle cycles with MTEST OFF */ + /* Allow MC to tristate during idle cycles with MTEST OFF. */ msrnum = MC_CFCLK_DBUG; msr = rdmsr(msrnum); msr.lo &= ~CFCLK_LOWER_TRISTATE_DIS_SET; wrmsr(msrnum, msr); - /* Disable SDCLK dimm1 slot if no DIMM installed to save power. */ + /* Disable SDCLK DIMM 1 slot if no DIMM installed (to save power). */ msr = rdmsr(MC_CF07_DATA); if ((msr.hi & (7 << CF07_UPPER_D1_PSZ_SHIFT)) == (7 << CF07_UPPER_D1_PSZ_SHIFT)) { @@ -767,53 +788,54 @@ wrmsr(msrnum, msr); } - /* Set PMode0 Sensitivity Counter */ + /* Set PMode0 Sensitivity Counter. */ msr.lo = 0; /* pmode 0=0 most aggressive */ msr.hi = 0x200; /* pmode 1=200h */ wrmsr(MC_CF_PMCTR, msr); - /* Set PMode1 Up delay enable */ + /* Set PMode1 Up delay enable. */ msrnum = MC_CF1017_DATA; msr = rdmsr(msrnum); msr.lo |= (209 << 8); /* bits[15:8] = 209 */ wrmsr(msrnum, msr); printk(BIOS_DEBUG, "DRAM controller init done.\n"); - post_code(POST_MEM_SETUP_GOOD); //0x7E + post_code(POST_MEM_SETUP_GOOD); - /* make sure there is nothing stale in the cache */ + /* Make sure there is nothing stale in the cache. */ /* CAR stack is in the cache __asm__ __volatile__("wbinvd\n"); */ - /* The RAM dll needs a write to lock on so generate a few dummy writes */ - /* Note: The descriptor needs to be enabled to point at memory */ + /* The RAM dll needs a write to lock on so generate a few dummy + * writes. Note: The descriptor needs to be enabled to point at memory. + */ volatile unsigned long *ptr; for (i = 0; i < 5; i++) { ptr = (void *)i; *ptr = (unsigned long)i; } - /* SWAPSiF for PBZ 4112 (Errata 34) */ - /* check for failed DLL settings now that we have done a memory write. */ + + /* SWAPSiF for PBZ 4112 (Errata 34) + * Check for failed DLL settings now that we have done a + * memory write. + */ msrnum = GLCP_DELAY_CONTROLS; msr = rdmsr(msrnum); if ((msr.lo & 0x7FF) == 0x104) { + /* If you had it you would need to clear out the fail boot + * count flag (depending on where it counts from etc). + */ - /* If you had it you would need to clear out the fail - * boot count flag (depending on where it counts from - * etc). - */ - /* The we are about to perform clears the PM_SSC - * register in the 5536 so will need to store the S3 - * resume *flag in NVRAM otherwise it would do a - * normal boot + * register in the CS5536 so will need to store the S3 + * resume flag in NVRAM otherwise it would do a normal boot. */ - /* Reset the system */ + /* Reset the system. */ msrnum = MDD_SOFT_RESET; msr = rdmsr(msrnum); msr.lo |= 1; wrmsr(msrnum, msr); } + printk(BIOS_DEBUG, "RAM DLL lock\n"); - }

1 0

[LinuxBIOS] r438 - LinuxBIOSv3/arch/x86/geodelx
by svn＠openbios.org July 7, 2007

July 7, 2007

Author: uwe Date: 2007-07-07 23:18:47 +0200 (Sat, 07 Jul 2007) New Revision: 438 Modified: LinuxBIOSv3/arch/x86/geodelx/cpu.c LinuxBIOSv3/arch/x86/geodelx/geodelx.c LinuxBIOSv3/arch/x86/geodelx/stage0.S LinuxBIOSv3/arch/x86/geodelx/stage1.c Log: Various coding style fixes, typo fixes, and other cosmetic changes (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: LinuxBIOSv3/arch/x86/geodelx/cpu.c =================================================================== --- LinuxBIOSv3/arch/x86/geodelx/cpu.c 2007-07-07 19:19:44 UTC (rev 437) +++ LinuxBIOSv3/arch/x86/geodelx/cpu.c 2007-07-07 21:18:47 UTC (rev 438) @@ -22,10 +22,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This is a test for the idea of a cpu device. There is only ever - * going to be one CPU device, the bootstrap processor or BP; other - * processors will go through a different path. on Geode it is - * really simple, so we start with that. Later, it gets harder. +/* This is a test for the idea of a CPU device. There is only ever going to + * be one CPU device, the bootstrap processor or BP; other processors will + * go through a different path. On Geode it is really simple, so we start + * with that. Later, it gets harder. */ #include <console.h> @@ -35,35 +35,38 @@ #include <io.h> #include <cpu.h> -/* TODO: better comment on vsm_end_post_smi, and define 0x05a2 down below */ -/** +/* TODO: Better comment on vsm_end_post_smi, and define 0x05a2 down below. */ + +/** * This is a call to the VSM. - * We need to know what it does. + * + * TODO: We need to know what it does. */ static void vsm_end_post_smi(void) { - __asm__ volatile ("push %ax\n" - "mov $0x5000, %ax\n" - ".byte 0x0f, 0x38\n" "pop %ax\n"); + __asm__ volatile("push %ax\n" + "mov $0x5000, %ax\n" + ".byte 0x0f, 0x38\n" + "pop %ax\n"); } /** - * The very last steps in lx init. Turn on caching, - * tell vsm that we are done. Turn A20 back on in - * case VSM turned it off. - * @param dev struct device pointer + * The very last steps in LX init. Turn on caching, tell VSM that we are + * done. Turn A20 back on in case VSM turned it off. + * + * @param dev The device to use. */ static void lx_init(struct device *dev) { - printk(BIOS_SPEW, "lx_init\n"); + printk(BIOS_SPEW, "CPU lx_init\n"); - /* Turn on caching if we haven't already */ + /* Turn on caching if we haven't already. */ enable_cache(); - // do VSA late init + /* Do VSA late init. */ vsm_end_post_smi(); - // Set gate A20 (legacy vsm disables it in late init) + /* Set gate A20 (legacy VSM disables it in late init). */ printk(BIOS_SPEW, "A20 (0x92): %d\n", inb(0x92)); outb(0x02, 0x92); printk(BIOS_SPEW, "A20 (0x92): %d\n", inb(0x92)); @@ -71,30 +74,34 @@ printk(BIOS_SPEW, "CPU lx_init DONE\n"); }; -/* The only operations currently set up are the phase 6. We might, - * however, set up an op in phase3_scan to get the cpuinfo into a - * struct for all to see. On SMP, it would not be hard to have - * phase3 scan set up an array of such structs. Further, for systems - * which have multiple types of CPUs, you can compile in multiple CPU - * files and use the device id, at scan time, to pick which one is - * used. There is a lot of flexibility here! +/** + * The only operations currently set up are the phase 6. We might, however, + * set up an op in phase3_scan to get the cpuinfo into a struct for all to + * see. On SMP, it would not be hard to have phase3_scan set up an array of + * such structs. + * + * Further, for systems which have multiple types of CPUs, you can compile + * in multiple CPU files and use the device ID, at scan time, to pick which + * one is used. There is a lot of flexibility here! */ struct device_operations geodelx_cpuops = { - .constructor = default_device_constructor, - .phase3_scan = NULL, - .phase6_init = lx_init, + .constructor = default_device_constructor, + .phase3_scan = NULL, + .phase6_init = lx_init, }; -/* This is a constructor for a cpu. the PCI id works for now. - * Later, we might need to change it to use a different phase3 scan, - * and match on a cpu id. However, CPU IDs are known to be kind - * of weird, depending on date manufactured they can be all - * over the place (the Geode alone has had 3 vendors!) so - * we will have to be careful - */ +/** + * This is a constructor for a CPU. + * + * Later, we might need to change it to use a different phase3_scan, and + * match on a CPU ID. However, CPU IDs are known to be kind of weird, + * depending on date manufactured they can be all over the place (the Geode + * alone has had 3 vendors!) so we will have to be careful. + */ struct constructor geodelx_constructors[] = { - {.id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = X86_VENDOR_AMD,.device = 0x05A2}}}, - .ops = &geodelx_cpuops}, - {.ops = 0}, + {.id = {.type = DEVICE_ID_PCI, + /* TODO: This is incorrect, these are _not_ PCI IDs! */ + .u = {.pci = {.vendor = X86_VENDOR_AMD,.device = 0x05A2}}}, + .ops = &geodelx_cpuops}, + {.ops = 0}, }; Modified: LinuxBIOSv3/arch/x86/geodelx/geodelx.c =================================================================== --- LinuxBIOSv3/arch/x86/geodelx/geodelx.c 2007-07-07 19:19:44 UTC (rev 437) +++ LinuxBIOSv3/arch/x86/geodelx/geodelx.c 2007-07-07 21:18:47 UTC (rev 438) @@ -28,71 +28,73 @@ #include <string.h> #include <msr.h> #include <io.h> +#include <hlt.h> #include <amd_geodelx.h> #include <spd.h> #include <legacy.h> -/* all these functions used to be in a lot of fiddly little files. To - * make it easier to find functions, we are merging them here. This - * file is our first real cpu-specific support file and should serve - * as a model for v3 cpu-specific support. So, warning, you might - * think it makes sense to split this file up, but we've tried that, - * and it sucks. - */ +/* All these functions used to be in a lot of fiddly little files. To make it + * easier to find functions, we are merging them here. This file is our first + * real CPU-specific support file and should serve as a model for v3 + * CPU-specific support. + * + * So, warning, you might think it makes sense to split this file up, but + * we've tried that, and it sucks. + */ -/** - * Starts Timer 1 for port 61 use. - * - * The command 0x56 means write counter 1 lower 8 bits in next IO, - * set the counter mode to square wave generator (count down to 0 - * from programmed value twice in a row, alternating the output signal) - * counting in 16-bit binary mode. - * - * 0x12 is counter/timer 1 and signals the PIT to do a RAM refresh - * approximately every 15us. - * - * The PIT typically is generating 1.19318 MHz - * Timer 1 was used for RAM refresh on XT/AT and can be read on port61. - * Port61 is used by many timing loops for calibration. - */ +/** + * Starts Timer 1 for port 61 use. + * + * The command 0x56 means write counter 1 lower 8 bits in next I/O, set the + * counter mode to square wave generator (count down to 0 from programmed + * value twice in a row, alternating the output signal) counting in 16-bit + * binary mode. + * + * 0x12 is counter/timer 1 and signals the PIT to do a RAM refresh + * approximately every 15us. + * + * The PIT typically is generating 1.19318 MHz. + * + * Timer 1 was used for RAM refresh on XT/AT and can be read on port 61. + * Port 61 is used by many timing loops for calibration. + */ void start_timer1(void) { outb(0x56, I82C54_CONTROL_WORD_REGISTER); outb(0x12, I82C54_COUNTER1); } -/** - * system_preinit Very early initialization needed for almost - * everything else. Currently, all we do is start timer1. - */ +/** + * Very early initialization needed for almost everything else. + * Currently, all we do is start timer1. + */ void system_preinit(void) { start_timer1(); } +/* CPU bug management */ -/* cpu bug management */ /** + * Bugtool #465 and #609 PCI cache deadlock. + * TODO: URL? * - * pci_deadlock Bugtool #465 and #609 PCI cache deadlock There is - * also fix code in cache and PCI functions. This bug is very is - * pervasive. - * + * There is also fix code in cache and PCI functions. This bug is very is + * pervasive. */ static void pci_deadlock(void) { - struct msr msr; + struct msr msr; - /* - * forces serialization of all load misses. Setting this bit prevents the - * DM pipe from backing up if a read request has to be held up waiting - * for PCI writes to complete. + /* Forces serialization of all load misses. Setting this bit prevents + * the DM pipe from backing up if a read request has to be held up + * waiting for PCI writes to complete. */ msr = rdmsr(CPU_DM_CONFIG0); msr.lo |= DM_CONFIG0_LOWER_MISSER_SET; wrmsr(CPU_DM_CONFIG0, msr); - /* write serialize memory hole to PCI. Need to unWS when something is + /* Write serialize memory hole to PCI. Need to unWS when something is * shadowed regardless of cachablility. */ msr.lo = 0x021212121; @@ -102,16 +104,16 @@ wrmsr(CPU_RCONF_E0_FF, msr); } -/** disable_memory_reorder PBZ 3659: The MC reordered transactions - * incorrectly and breaks coherency. Disable reording and take a - * potential performance hit. This is safe to do here and not in - * MC init since there is nothing to maintain coherency with and - * the cache is not enabled yet. - */ -/****************************************************************************/ +/** + * PBZ 3659: The MC reordered transactions incorrectly and breaks coherency. + * + * Disable reording and take a potential performance hit. This is safe to do + * here and not in MC init, since there is nothing to maintain coherency with + * and the cache is not enabled yet. + */ static void disable_memory_reorder(void) { - struct msr msr; + struct msr msr; msr = rdmsr(MC_CF8F_DATA); msr.hi |= CF8F_UPPER_REORDER_DIS_SET; @@ -119,55 +121,61 @@ } /** - * Fix up register settings to manage known CPU bugs. For cpu - * version C3. Should be the only released version - */ + * Fix up register settings to manage known CPU bugs. + * + * For CPU version C3. Should be the only released version. + */ void cpu_bug(void) { pci_deadlock(); disable_memory_reorder(); - printk(BIOS_DEBUG, "Done cpubug fixes \n"); + printk(BIOS_DEBUG, "Done cpubug fixes\n"); } /** - * Reset the phase locked loop hardware. After power on as part of - * this operation, we have to set the clock hardware and reboot. Thus, - * we have to know if we have been here before. To do this, we use the - * RSTPLL_LOWER_SWFLAGS_SHIFT flag in the msrGlcpSysRstpll. Also, the - * clocks can either be configured via passed-in parameters or - * hardware straps. Once set, we yank the hardware reset line and - * hlt. We should never reach the hlt, but one never knows. + * Reset the phase locked loop (PLL) hardware. * - * @param manualconf If non-zero, use passed-in parameters to - * determine how to configure pll -- manual or automagic. - * If manual, use passed-in parameters pll_hi and pll_lo - * @param pll_hi value to use for the high 32 bits of the pll msr - * @param pll_lo value to use for the low 32 bits of the pll msr + * After power on as part of this operation, we have to set the clock + * hardware and reboot. Thus, we have to know if we have been here before. + * + * To do this, we use the RSTPLL_LOWER_SWFLAGS_SHIFT flag in the + * msrGlcpSysRstpll. Also, the clocks can either be configured via passed-in + * parameters or hardware straps. Once set, we yank the hardware reset line + * and hlt. We should never reach the hlt, but one never knows. + * + * @param manualconf If non-zero, use passed-in parameters to determine how + * to configure PLL -- manual or automagic. If manual, use + * passed-in parameters pll_hi and pll_lo. + * @param pll_hi Value to use for the high 32 bits of the PLL msr. + * @param pll_lo Value to use for the low 32 bits of the PLL msr. */ void pll_reset(int manualconf, u32 pll_hi, u32 pll_lo) { - struct msr msr_glcp_sys_pll; /* GeodeLink PLL control MSR */ + struct msr msr_glcp_sys_pll; /* GeodeLink PLL control MSR */ msr_glcp_sys_pll = rdmsr(GLCP_SYS_RSTPLL); - printk(BIOS_DEBUG, - "_MSR GLCP_SYS_RSTPLL (%08x) value is: %08x:%08x\n", msr_glcp_sys_pll.hi, msr_glcp_sys_pll.lo); + printk(BIOS_DEBUG, + "_MSR GLCP_SYS_RSTPLL (%08x) value is: %08x:%08x\n", + msr_glcp_sys_pll.hi, msr_glcp_sys_pll.lo); post_code(POST_PLL_INIT); if (!(msr_glcp_sys_pll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) { - printk(BIOS_DEBUG,"Configuring PLL\n"); + printk(BIOS_DEBUG, "Configuring PLL\n"); if (manualconf) { post_code(POST_PLL_MANUAL); - /* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */ + /* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */ msr_glcp_sys_pll.hi = pll_hi; /* Hold Count - how long we will sit in reset */ msr_glcp_sys_pll.lo = pll_lo; } else { - /*automatic configuration (straps) */ + /* Automatic configuration (straps) */ post_code(POST_PLL_STRAP); - /* Hold 0xDE * 16 clocks during reset. */ - /* AMD recomended value for PLL reset from silicon validation. */ + + /* Hold 0xDE * 16 clocks during reset. AMD recomended + * value for PLL reset from silicon validation. + */ msr_glcp_sys_pll.lo &= ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT); msr_glcp_sys_pll.lo |= @@ -178,79 +186,81 @@ msr_glcp_sys_pll.lo |= RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET; } - /* Use SWFLAGS to remember: "we've already been here" */ + + /* Use SWFLAGS to remember: "we've already been here". */ msr_glcp_sys_pll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT); - /* "reset the chip" value */ + /* "Reset the chip" value */ msr_glcp_sys_pll.lo |= RSTPPL_LOWER_CHIP_RESET_SET; wrmsr(GLCP_SYS_RSTPLL, msr_glcp_sys_pll); - /* You should never get here..... The chip has reset. */ - printk(BIOS_EMERG,"CONFIGURING PLL FAILURE -- HALT\n"); + /* You should never get here... the chip has reset. */ + printk(BIOS_EMERG, "CONFIGURING PLL FAILURE -- HALT\n"); post_code(POST_PLL_RESET_FAIL); - __asm__ __volatile__("hlt\n"); + hlt(); + } - } printk(BIOS_DEBUG, "Done pll_reset\n"); return; } - /** * Return the CPU clock rate from the PLL MSR. - * @return CPU speed in MHz + * + * @return CPU speed in MHz. */ u32 cpu_speed(void) { u32 speed; - struct msr msr; + struct msr msr; msr = rdmsr(GLCP_SYS_RSTPLL); - speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & RSTPLL_UPPER_CPUMULT_MASK) + 1) * 333) / 10; - if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & RSTPLL_UPPER_CPUMULT_MASK) + 1) * 333) % 10) > 5) { + speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) + & RSTPLL_UPPER_CPUMULT_MASK) + 1) * 333) / 10; + if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) + & RSTPLL_UPPER_CPUMULT_MASK) + 1) * 333) % 10) > 5) { ++speed; } - return (speed); + return speed; } /** * Return the GeodeLink clock rate from the PLL MSR. - * @return GeodeLink speed in MHz + * + * @return GeodeLink speed in MHz. */ u32 geode_link_speed(void) { - unsigned int speed; - struct msr msr; + u32 speed; + struct msr msr; msr = rdmsr(GLCP_SYS_RSTPLL); - speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & RSTPLL_UPPER_GLMULT_MASK) + 1) * 333) / 10; - if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & RSTPLL_UPPER_GLMULT_MASK) + 1) * 333) % 10) > 5) { + speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) + & RSTPLL_UPPER_GLMULT_MASK) + 1) * 333) / 10; + if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) + & RSTPLL_UPPER_GLMULT_MASK) + 1) * 333) % 10) > 5) { ++speed; } - return (speed); + return speed; } - /** * Return the PCI bus clock rate from the PLL MSR. - * @return PCI speed in MHz + * + * @return PCI speed in MHz. */ u32 pci_speed(void) { - struct msr msr; + struct msr msr = rdmsr(GLCP_SYS_RSTPLL); - msr = rdmsr(GLCP_SYS_RSTPLL); - if (msr.hi & (1 << RSTPPL_LOWER_PCISPEED_SHIFT)) { - return (66); - } else { - return (33); - } + if (msr.hi & (1 << RSTPPL_LOWER_PCISPEED_SHIFT)) + return 66; + else + return 33; } - /** - * Delay Control Settings Table from AMD (MCP 0x4C00000F) - * ========================================================================= + * Delay Control Settings table from AMD (MCP 0x4C00000F). */ const struct delay_controls { u8 dimms; @@ -259,55 +269,56 @@ u32 slow_low; u32 fast_hi; u32 fast_low; -} delay_control_table [] = { +} delay_control_table[] = { /* DIMMs Devs Slow (<=333MHz) Fast (>334MHz) */ - { 1, 4, 0x0837100FF, 0x056960004, 0x0827100FF, 0x056960004 }, - { 1, 8, 0x0837100AA, 0x056960004, 0x0827100AA, 0x056960004 }, - { 1, 16, 0x0837100AA, 0x056960004, 0x082710055, 0x056960004 }, - { 2, 8, 0x0837100A5, 0x056960004, 0x082710000, 0x056960004 }, - { 2, 16, 0x0937100A5, 0x056960004, 0x0C27100A5, 0x056960004 }, - { 2, 20, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 }, - { 2, 24, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 }, - { 2, 32, 0x0B37100A5, 0x056960004, 0x0B2710000, 0x056960004 }, + { 1, 4, 0x0837100FF, 0x056960004, 0x0827100FF, 0x056960004 }, + { 1, 8, 0x0837100AA, 0x056960004, 0x0827100AA, 0x056960004 }, + { 1, 16, 0x0837100AA, 0x056960004, 0x082710055, 0x056960004 }, + { 2, 8, 0x0837100A5, 0x056960004, 0x082710000, 0x056960004 }, + { 2, 16, 0x0937100A5, 0x056960004, 0x0C27100A5, 0x056960004 }, + { 2, 20, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 }, + { 2, 24, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 }, + { 2, 32, 0x0B37100A5, 0x056960004, 0x0B2710000, 0x056960004 }, }; -/** - * - Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM - * in slot 0, but it should be clear for all 2 DIMM settings and if a - * single DIMM is in slot 1. Bits 54:52 should always be set to '111'. + +/* + * Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM + * in slot 0, but it should be clear for all 2 DIMM settings and if a + * single DIMM is in slot 1. Bits 54:52 should always be set to '111'. * - * Settings for single DIMM and no VTT termination (Like db800 platform) - * 0xF2F100FF 0x56960004 - * ------------------------------------- - * ADDR/CTL have 22 ohm series R - * DQ/DQM/DQS have 33 ohm series R + * Settings for single DIMM and no VTT termination (like DB800 platform) + * 0xF2F100FF 0x56960004 + * ------------------------------------- + * ADDR/CTL have 22 ohm series R + * DQ/DQM/DQS have 33 ohm series R */ - /** - * set_delay_control. This is Black Magic DRAM timing - * juju(http://www.thefreedictionary.com/juju) Dram delay depends on - * cpu clock, memory bus clock, memory bus loading, memory bus - * termination, your middle initial (ha! caught you!), Geode Link - * clock rate, and dram timing specifications. From this the code - * computes a number which is "known to work". No, hardware is not an - * exact science. And, finally, if an FS2 (jtag debugger) is hooked - * up, then just don't to anything. This code was written by a master + * This is Black Magic DRAM timing juju[1]. + * + * DRAM delay depends on CPU clock, memory bus clock, memory bus loading, + * memory bus termination, your middle initial (ha! caught you!), GeodeLink + * clock rate, and DRAM timing specifications. + * + * From this the code computes a number which is "known to work". No, + * hardware is not an exact science. And, finally, if an FS2 (JTAG debugger) + * is hooked up, then just don't do anything. This code was written by a master * of the Dark Arts at AMD and should not be modified in any way. * - * @param num_banks How many banks of DRAM there are - * @param dimm0 DIMM 0 SMBus address - * @param dimm1 DIMM 1 SMBus address - * @param sram_width Data width of the SDRAM + * [1] (http://www.thefreedictionary.com/juju) + * + * @param dimm0 The SMBus address of DIMM 0 (mainboard dependent). + * @param dimm1 The SMBus address of DIMM 1 (mainboard dependent). */ void set_delay_control(u8 dimm0, u8 dimm1) { u32 msrnum, glspeed; u8 spdbyte0, spdbyte1, dimms, i; - struct msr msr; + struct msr msr; glspeed = geode_link_speed(); - /* fix delay controls for DM and IM arrays */ + /* Fix delay controls for DM and IM arrays. */ msrnum = CPU_BC_MSS_ARRAY_CTL0; msr.hi = 0; msr.lo = 0x2814D352; @@ -328,33 +339,32 @@ msr.hi = 0x00000005; wrmsr(msrnum, msr); - /* Enable setting */ + /* Enable setting. */ msrnum = CPU_BC_MSS_ARRAY_CTL_ENA; msr.hi = 0; msr.lo = 0x00000001; wrmsr(msrnum, msr); - /* Debug Delay Control Setup Check - * - * Leave it alone if it has been setup. FS2 or something is here. - */ + /* Debug Delay Control setup check. + * Leave it alone if it has been setup. FS2 or something is here. + */ msrnum = GLCP_DELAY_CONTROLS; msr = rdmsr(msrnum); - if (msr.lo & ~(DELAY_LOWER_STATUS_MASK)) { + if (msr.lo & ~(DELAY_LOWER_STATUS_MASK)) return; - } - /* - * Delay Controls based on DIMM loading. UGH! - * # of Devices = Module Width (SPD6) / Device Width(SPD13) * Physical Banks(SPD5) - * Note - We only support module width of 64. + /* Delay Controls based on DIMM loading. UGH! + * Number of devices = module width (SPD 6) / device width (SPD 13) + * * physical banks (SPD 5) + * + * Note: We only support a module width of 64. */ dimms = 0; spdbyte0 = smbus_read_byte(dimm0, SPD_PRIMARY_SDRAM_WIDTH); if (spdbyte0 != 0xFF) { dimms++; - spdbyte0 = (unsigned char)64 / spdbyte0 * - (unsigned char)(smbus_read_byte(dimm0, SPD_NUM_DIMM_BANKS)); + spdbyte0 = (u8)64 / spdbyte0 * + (u8)(smbus_read_byte(dimm0, SPD_NUM_DIMM_BANKS)); } else { spdbyte0 = 0; } @@ -362,25 +372,24 @@ spdbyte1 = smbus_read_byte(dimm1, SPD_PRIMARY_SDRAM_WIDTH); if (spdbyte1 != 0xFF) { dimms++; - spdbyte1 = (unsigned char)64 / spdbyte1 * - (unsigned char)(smbus_read_byte(dimm1, SPD_NUM_DIMM_BANKS)); + spdbyte1 = (u8)64 / spdbyte1 * + (u8)(smbus_read_byte(dimm1, SPD_NUM_DIMM_BANKS)); } else { spdbyte1 = 0; } - /* zero GLCP_DELAY_CONTROLS MSR */ + /* Zero GLCP_DELAY_CONTROLS MSR */ msr.hi = msr.lo = 0; - /* save some power, disable clock to second DIMM if it is empty */ - if (spdbyte1 == 0) { + /* Save some power, disable clock to second DIMM if it is empty. */ + if (spdbyte1 == 0) msr.hi |= DELAY_UPPER_DISABLE_CLK135; - } spdbyte0 += spdbyte1; for (i = 0; i < ARRAY_SIZE(delay_control_table); i++) { if ((dimms == delay_control_table[i].dimms) && - (spdbyte0 <= delay_control_table[i].devices)) { + (spdbyte0 <= delay_control_table[i].devices)) { if (glspeed < 334) { msr.hi |= delay_control_table[i].slow_hi; msr.lo |= delay_control_table[i].slow_low; @@ -395,29 +404,28 @@ } /** - * cpu_reg_init. All cpu register settings, here in one place, and - * done in the proper order. + * All CPU register settings, here in one place, and done in the proper order. * - * @param debug_clock_disable Disable the debug clock to save power. Currently ignored, but we need to - * pick this up from a CMOS setting in future. - * @param dimm0 SMBus address of dimm0 (mainboard dependent) - * @param dimm1 SMBus address of dimm1 (mainboard dependent) + * @param debug_clock_disable Disable the debug clock to save power. Currently + * ignored, but we need to pick this up from a CMOS + * setting in future. + * @param dimm0 SMBus address of DIMM 0 (mainboard dependent). + * @param dimm1 SMBus address of DIMM 1 (mainboard dependent). */ void cpu_reg_init(int debug_clock_disable, u8 dimm0, u8 dimm1) { int msrnum; - struct msr msr; + struct msr msr; /* Castle 2.0 BTM periodic sync period. */ - /* [40:37] 1 sync record per 256 bytes */ + /* [40:37] 1 sync record per 256 bytes. */ msrnum = CPU_PF_CONF; msr = rdmsr(msrnum); msr.hi |= (0x8 << 5); wrmsr(msrnum, msr); - /* - ; Castle performance setting. - ; Enable Quack for fewer re-RAS on the MC + /* Castle performance setting. + * Enable Quack for fewer re-RAS on the MC. */ msrnum = GLIU0_ARB; msr = rdmsr(msrnum); @@ -431,45 +439,49 @@ msr.hi |= ARB_UPPER_QUACK_EN_SET; wrmsr(msrnum, msr); - /* GLIU port active enable, limit south pole masters (AES and PCI) to one outstanding transaction. */ + /* GLIU port active enable, limit south pole masters (AES and PCI) to + * one outstanding transaction. + */ msrnum = GLIU1_PORT_ACTIVE; msr = rdmsr(msrnum); msr.lo &= ~0x880; wrmsr(msrnum, msr); - /* Set the Delay Control in GLCP */ + /* Set the Delay Control in GLCP. */ set_delay_control(dimm0, dimm1); - /* Enable RSDC */ + /* Enable RSDC. */ msrnum = CPU_AC_SMM_CTL; msr = rdmsr(msrnum); msr.lo |= SMM_INST_EN_SET; wrmsr(msrnum, msr); - /* FPU imprecise exceptions bit */ + /* FPU imprecise exceptions bit. */ msrnum = CPU_FPU_MSR_MODE; msr = rdmsr(msrnum); msr.lo |= FPU_IE_SET; wrmsr(msrnum, msr); - /* Power Savers (Do after BIST) */ - /* Enable Suspend on HLT & PAUSE instructions */ + /* Power savers (do after BIST). */ + /* Enable Suspend on HLT & PAUSE instructions. */ msrnum = CPU_XC_CONFIG; msr = rdmsr(msrnum); msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE; wrmsr(msrnum, msr); - /* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */ + /* Enable SUSP and allow TSC to run in Suspend (keep speed + * detection happy). + */ msrnum = CPU_BC_CONF_0; msr = rdmsr(msrnum); msr.lo |= TSC_SUSP_SET | SUSP_EN_SET; msr.lo &= 0x0F0FFFFFF; - msr.lo |= 0x002000000; /* PBZ213: Set PAUSEDLY = 2 */ + msr.lo |= 0x002000000; /* PBZ213: Set PAUSEDLY = 2. */ wrmsr(msrnum, msr); /* Disable the debug clock to save power. */ - /* NOTE: leave it enabled for fs2 debug */ - if (debug_clock_disable && 0){ + /* Note: Leave it enabled for FS2 debug. */ + if (debug_clock_disable && 0) { msrnum = GLCP_DBGCLKCTL; msr.hi = 0; msr.lo = 0; @@ -481,7 +493,8 @@ msr.hi = 0; msr.lo = 0x00000603C; wrmsr(msrnum, msr); - /* fix cpu bugs */ + + /* Fix CPU bugs. */ #warning testing fixing bugs in initram cpu_bug(); } Modified: LinuxBIOSv3/arch/x86/geodelx/stage0.S =================================================================== --- LinuxBIOSv3/arch/x86/geodelx/stage0.S 2007-07-07 19:19:44 UTC (rev 437) +++ LinuxBIOSv3/arch/x86/geodelx/stage0.S 2007-07-07 21:18:47 UTC (rev 438) @@ -1,29 +1,29 @@ -## -## This file is part of the LinuxBIOS project. -## -## Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> -## Copyright (C) 2005 Eswar Nallusamy, LANL -## Copyright (C) 2005 Tyan -## (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan) -## Copyright (C) 2007 coresystems GmbH -## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) -## Copyright (C) 2007 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2005 Eswar Nallusamy, LANL + * Copyright (C) 2005 Tyan + * (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan) + * Copyright (C) 2007 coresystems GmbH + * (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ -/* Init code - Switch CPU to protected mode and enable Cache-as-Ram. */ +/* Init code - Switch CPU to protected mode and enable Cache-as-Ram (CAR). */ #include "../macros.h" #include <amd_geodelx.h> @@ -31,20 +31,20 @@ /* This is where the DCache will be mapped and be used as stack. It would be * cool if it was the same base as LinuxBIOS normal stack. */ -#define LX_STACK_BASE DCACHE_RAM_BASE -#define LX_STACK_END LX_STACK_BASE+(DCACHE_RAM_SIZE-4) +#define LX_STACK_BASE DCACHE_RAM_BASE +#define LX_STACK_END LX_STACK_BASE + (DCACHE_RAM_SIZE - 4) -#define LX_NUM_CACHELINES 0x080 /* There are 128 lines per way. */ -#define LX_CACHELINE_SIZE 0x020 /* There are 32 bytes per line. */ -#define LX_CACHEWAY_SIZE (LX_NUM_CACHELINES * LX_CACHELINE_SIZE) -#define CR0_CD 0x40000000 /* Bit 30 = Cache Disable */ -#define CR0_NW 0x20000000 /* Bit 29 = Not Write Through */ +#define LX_NUM_CACHELINES 0x080 /* There are 128 lines per way. */ +#define LX_CACHELINE_SIZE 0x020 /* There are 32 bytes per line. */ +#define LX_CACHEWAY_SIZE (LX_NUM_CACHELINES * LX_CACHELINE_SIZE) +#define CR0_CD 0x40000000 /* Bit 30 = Cache Disable */ +#define CR0_NW 0x20000000 /* Bit 29 = Not Write Through */ -#define ROM_CODE_SEG 0x08 -#define ROM_DATA_SEG 0x10 +#define ROM_CODE_SEG 0x08 +#define ROM_DATA_SEG 0x10 -#define CACHE_RAM_CODE_SEG 0x18 -#define CACHE_RAM_DATA_SEG 0x20 +#define CACHE_RAM_CODE_SEG 0x18 +#define CACHE_RAM_DATA_SEG 0x20 .code16 .globl _stage0 @@ -54,21 +54,19 @@ /* Save the BIST result. */ movl %eax, %ebp; - /* Thanks to kmliu(a)sis.com.tw for this TLB fix. */ - /* IMMEDIATELY invalidate the translation lookaside buffer before + /* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before * executing any further code. Even though paging is disabled we * could still get false address translations due to the TLB if we * didn't invalidate it. */ - xorl %eax, %eax - movl %eax, %cr3 /* Invalidate TLB */ + movl %eax, %cr3 /* Invalidate TLB. */ /* Switch to protected mode. */ /* NOTE: With GNU assembler version 2.15.94.0.2.2 (i386-redhat-linux) * using BFD version 2.15.94.0.2.2 20041220 this works fine without - * all the ld hackery and so on. So leave it as is with this comment. + * all the ld hackery and so on. So leave it as is with this comment. */ data32 lgdt %cs:gdtptr @@ -84,18 +82,19 @@ // port80_post(0x23) /* Now we are in protected mode. Jump to a 32 bit code segment. */ - data32 ljmp $ROM_CODE_SEG, $protected_stage0 + data32 ljmp $ROM_CODE_SEG, $protected_stage0 + /* I am leaving this weird jump in here in the event that future gas * bugs force it to be used. */ - #.byte 0x66 + /* .byte 0x66 */ .code32 - #ljmp $ROM_CODE_SEG, $protected_stage0 + /* ljmp $ROM_CODE_SEG, $protected_stage0 */ - #.code16 - .align 4 + /* .code16 */ + .align 4 .globl gdt16 -gdt16 = . - _stage0 +gdt16 = . - _stage0 gdt16x: .word gdt16xend - gdt16x -1 /* Compute the table limit. */ .long gdt16x @@ -118,22 +117,22 @@ * Let's not worry about this -- optimizing gdt is pointless since * we're only in it for a little bit. * - * BTW note the trick below: The GDT points to ITSELF, and the first + * Btw. note the trick below: The GDT points to ITSELF, and the first * good descriptor is at offset 8. So you word-align the table, and * then because you chose 8, you get a nice 64-bit aligned GDT entry, * which is good as this is the size of the entry. * - * Just in case you ever wonder why people do this. + * Just in case you ever wonder why people do this. */ - .align 4 + .align 4 .globl gdtptr .globl gdt_limit -gdt_limit = gdt_end - gdt - 1 /* Compute the table limit. */ +gdt_limit = gdt_end - gdt - 1 /* Compute the table limit. */ gdt: gdtptr: - .word gdt_end - gdt -1 /* Compute the table limit. */ - .long gdt /* We know the offset. */ + .word gdt_end - gdt -1 /* Compute the table limit. */ + .long gdt /* We know the offset. */ .word 0 /* selgdt 0x08, flat code segment */ @@ -153,21 +152,20 @@ .byte 0x00, 0x93, 0xcf, 0x00 gdt_end: - /* - * When we come here we are in protected mode. We expand the stack + /* When we come here we are in protected mode. We expand the stack * and copy the data segment from ROM to the memory. * * After that, we call the chipset bootstrap routine that * does what is left of the chipset initialization. * - * NOTE: Aligned to 4 so that we are sure that the prefetch + * Note: Aligned to 4 so that we are sure that the prefetch * cache will be reloaded. */ .align 4 .globl protected_stage0 protected_stage0: - // This code was used by v2. TODO + /* This code was used by v2. TODO. */ lgdt %cs:gdtptr ljmp $ROM_CODE_SEG, $__protected_stage0 @@ -188,17 +186,18 @@ /* Restore the BIST value to %eax. */ movl %ebp, %eax -.align 4 + .align 4 /* Here begins CAR support. */ - /* This particular code is straight from LinuxBIOS V2. */ + /* This particular code is straight from LinuxBIOS v2. */ /* DCacheSetup: Setup data cache for use as RAM for a stack. */ DCacheSetup: + invd - invd /* Set cache properties. */ movl $CPU_RCONF_DEFAULT, %ecx rdmsr + /* 1MB system memory in write back 1|00100|00. */ movl $0x010010000, %eax wrmsr @@ -208,6 +207,7 @@ */ movl CPU_DM_CONFIG0,%ecx rdmsr + /* TODO: Make consistent with i$ init, either whole reg = 0, or just * this bit... */ @@ -258,17 +258,18 @@ movl $CPU_DC_INDEX, %ecx wrmsr - /* Startaddress for tag of Way0: ebp will hold the incrementing - * address. dont destroy! + /* Start address for tag of Way0: ebp will hold the incrementing + * address. Don't destroy! */ movl $LX_STACK_BASE, %ebp /* Init to start address. */ - /* Set valid bit and tag for this Way (B[31:12] : Cache tag value for + + /* Set valid bit and tag for this Way (B[31:12]: Cache tag value for * line/way curr. selected by CPU_DC_INDEX. */ orl $1, %ebp /* Start tag Ways 0 with 128 lines with 32 bytes each: edi will hold - * the line counter. dont destroy! + * the line counter. Don't destroy! */ movl $LX_NUM_CACHELINES, %edi @@ -298,12 +299,13 @@ movl $CPU_DC_TAG, %ecx wrmsr - /* Switch to next line. Lines are in Bits10:4. */ + /* Switch to next line. Lines are in bits 10:4. */ /* When index is crossing 0x7F -> 0x80 writing a RSVD bit as 0x80 is * not a valid CL anymore! */ movl $CPU_DC_INDEX, %ecx rdmsr + /* TODO: Probably would be more elegant to calculate this from * counter var edi... */ @@ -325,7 +327,8 @@ movl $CPU_DC_INDEX, %ecx rdmsr addl $0x01, %eax - /* Let's be sure: reset line index Bits10:4. */ + + /* Let's be sure: reset line index bits 10:4. */ andl $0xFFFFF80F, %eax wrmsr @@ -371,6 +374,7 @@ */ /* Clear the cache, the following code from crt0.S.lb will setup * a new stack. + * TODO: There is no crt0.S.lb (anymore?). */ wbinvd @@ -387,6 +391,7 @@ lout: /* Restore the BIST result. */ movl %ebp, %eax + /* We need to set ebp? No need. */ movl %esp, %ebp pushl %eax /* BIST */ @@ -394,40 +399,43 @@ /* We will not go back. */ fixed_mtrr_msr: - .long 0x250, 0x258, 0x259 - .long 0x268, 0x269, 0x26A - .long 0x26B, 0x26C, 0x26D - .long 0x26E, 0x26F + .long 0x250, 0x258, 0x259 + .long 0x268, 0x269, 0x26A + .long 0x26B, 0x26C, 0x26D + .long 0x26E, 0x26F var_mtrr_msr: - .long 0x200, 0x201, 0x202, 0x203 - .long 0x204, 0x205, 0x206, 0x207 - .long 0x208, 0x209, 0x20A, 0x20B - .long 0x20C, 0x20D, 0x20E, 0x20F - .long 0x000 /* NULL, end of table */ + .long 0x200, 0x201, 0x202, 0x203 + .long 0x204, 0x205, 0x206, 0x207 + .long 0x208, 0x209, 0x20A, 0x20B + .long 0x20C, 0x20D, 0x20E, 0x20F + .long 0x000 /* NULL, end of table */ -# Reset vector. +/* Reset vector. */ /* - * RVECTOR: size of reset vector, default is 0x10 - * RESRVED: size of vpd code, default is 0xf0 - * BOOTBLK: size of bootblock code, default is 0x1f00 (8k-256b) + * RVECTOR: Size of reset vector, default is 0x10. + * RESRVED: Size of vpd code, default is 0xf0. + * BOOTBLK: Size of bootblock code, default is 0x1f00 (8k-256b). */ SEGMENT_SIZE = 0x10000 RVECTOR = 0x00010 -# Due to YET ANOTHER BUG in GNU bintools, you can NOT have a code16 here. -# I think we should leave it this way forever, as the bugs come and -# go -- and come again. -# .code16 -# .section ".rom.text" +/* Due to YET ANOTHER BUG in GNU bintools, you can NOT have a code16 here. + * I think we should leave it this way forever, as the bugs come and + * go -- and come again. + * + * .code16 + * .section ".rom.text" + */ .section ".reset", "ax" .globl _resetjump _resetjump: /* GNU bintools bugs again. This jumps to stage0 - 2. Sigh. */ -# jmp _stage0 - .byte 0xe9 - .int _stage0 - ( . + 2 ) + /* jmp _stage0 */ + .byte 0xe9 + .int _stage0 - ( . + 2 ) + /* Note: The above jump is hand coded to work around bugs in binutils. * 5 bytes are used for a 3 byte instruction. This works because x86 * is little endian and allows us to use supported 32 bit relocations @@ -436,8 +444,8 @@ */ .byte 0 -# Date? ID string? We might want to put something else in here. +/* Date? ID string? We might want to put something else in here. */ .ascii DATE -# Checksum. -#.word 0 +/* Checksum. */ +/* .word 0 */ Modified: LinuxBIOSv3/arch/x86/geodelx/stage1.c =================================================================== --- LinuxBIOSv3/arch/x86/geodelx/stage1.c 2007-07-07 19:19:44 UTC (rev 437) +++ LinuxBIOSv3/arch/x86/geodelx/stage1.c 2007-07-07 21:18:47 UTC (rev 438) @@ -32,13 +32,15 @@ #include <spd.h> /** - * geodelx_msr_init Set up Geode LX registers for sane behaviour. Set - * all low memory (under 1MB) to write back. Do some setup for cache - * as ram as well. - */ + * Set up Geode LX registers for sane behaviour. + * + * Set all low memory (under 1MB) to write back. Do some setup for Cache + * as Ram (CAR) as well. + */ void geodelx_msr_init(void) { - struct msr msr; + struct msr msr; + /* Setup access to the cache for under 1MB. */ msr.hi = 0x24fffc02; msr.lo = 0x1000A000; /* 0-A0000 write back */ @@ -51,7 +53,7 @@ wrmsr(CPU_RCONF_E0_FF, msr); /* Setup access to the cache for under 640K. */ - /* Note memory controler not setup yet. */ + /* Note: Memory controller not setup yet. */ msr.hi = 0x20000000; msr.lo = 0x000fff80; /* 0-0x7FFFF */ wrmsr(MSR_GLIU0_BASE1, msr); @@ -67,6 +69,4 @@ msr.hi = 0x20000000; msr.lo = 0x080fffe0; /* 0x80000-0x9FFFF */ wrmsr(MSR_GLIU0_BASE2, msr); - } -

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[LinuxBIOS] [PATCH][v3] Drop superfluous round()
by Uwe Hermann July 7, 2007

July 7, 2007

See patch. Do we want align_up()/align_down() in lib.c maybe? Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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