coreboot July 2007

coreboot@coreboot.org

73 participants
208 discussions

Re: [LinuxBIOS] r447 - in LinuxBIOSv3: include/device mainboard/emulation/qemu-x86
by Stefan Reinauer 12 Jul '07

12 Jul '07

* svn(a)openbios.org <svn(a)openbios.org> [070712 03:03]: > Some minor cosmetic fixes (trivial). > -/* no printk allowed until hardware is ready; hardware is ready */ > /** > - * start up hardware needed for stage1 > + * Start up hardware needed for stage1. > + * > + * No printk() allowed until hardware is ready; hardware is ready. > + * TODO: Fix above comment? It's unclear. > */ I don't think it is. Without hardware to print on, no printk. What's unclear with that? I also think this should not go into the doxygen comment. -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/

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[LinuxBIOS] Acer TravelMate 660
by Gerhard Gappmeier 12 Jul '07

12 Jul '07

Hi, has anyone LinuxBIOS running on an Acer TravelMate 660 laptop? Or can tell me if it will work? I'm a LinuxBIOS newbie, but I hope the following information can help. cat /proc/cpuinfo: processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 9 model name : Intel(R) Pentium(R) M processor 1400MHz stepping : 5 cpu MHz : 1400.000 cache size : 1024 KB fdiv_bug : no hlt_bug : no f00f_bug : no coma_bug : no fpu : yes fpu_exception : yes cpuid level : 2 wp : yes flags : fpu vme de pse tsc msr mce cx8 sep mtrr pge mca cmov pat clflush dts acpi mmx fxsr sse sse2 tm pbe est tm2 bogomips : 2791.77 clflush size : 64 lspci -v: 00:00.0 Host bridge: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to I/O Controller (rev 02) Subsystem: Acer Incorporated [ALI] Unknown device 0035 Flags: bus master, fast devsel, latency 0 Memory at <unassigned> (32-bit, prefetchable) Capabilities: [40] Vendor Specific Information 00:00.1 System peripheral: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to I/O Controller (rev 02) Subsystem: Acer Incorporated [ALI] Unknown device 0035 Flags: bus master, fast devsel, latency 0 00:00.3 System peripheral: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to I/O Controller (rev 02) Subsystem: Acer Incorporated [ALI] Unknown device 0035 Flags: bus master, fast devsel, latency 0 00:02.0 VGA compatible controller: Intel Corporation 82852/855GM Integrated Graphics Device (rev 02) (prog-if 00 [VGA]) Subsystem: Acer Incorporated [ALI] Unknown device 0035 Flags: bus master, fast devsel, latency 0, IRQ 11 Memory at e8000000 (32-bit, prefetchable) [size=128M] Memory at e0000000 (32-bit, non-prefetchable) [size=512K] I/O ports at 1800 [size=8] Capabilities: [d0] Power Management version 1 00:02.1 Display controller: Intel Corporation 82852/855GM Integrated Graphics Device (rev 02) Subsystem: Acer Incorporated [ALI] Unknown device 0035 Flags: bus master, fast devsel, latency 0 Memory at f0000000 (32-bit, prefetchable) [disabled] [size=128M] Memory at e0080000 (32-bit, non-prefetchable) [disabled] [size=512K] Capabilities: [d0] Power Management version 1 00:1d.0 USB Controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #1 (rev 03) (prog-if 00 [UHCI]) Subsystem: Acer Incorporated [ALI] Unknown device 0035 Flags: bus master, medium devsel, latency 0, IRQ 11 I/O ports at 1820 [size=32] 00:1d.1 USB Controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #2 (rev 03) (prog-if 00 [UHCI]) Subsystem: Acer Incorporated [ALI] Unknown device 0035 Flags: bus master, medium devsel, latency 0, IRQ 11 I/O ports at 1840 [size=32] 00:1d.2 USB Controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #3 (rev 03) (prog-if 00 [UHCI]) Subsystem: Acer Incorporated [ALI] Unknown device 0035 Flags: bus master, medium devsel, latency 0, IRQ 10 I/O ports at 1860 [size=32] 00:1d.7 USB Controller: Intel Corporation 82801DB/DBM (ICH4/ICH4-M) USB2 EHCI Controller (rev 03) (prog-if 20 [EHCI]) Subsystem: Acer Incorporated [ALI] Unknown device 0035 Flags: bus master, medium devsel, latency 0, IRQ 10 Memory at e0100000 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Capabilities: [58] Debug port 00:1e.0 PCI bridge: Intel Corporation 82801 Mobile PCI Bridge (rev 83) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=02, subordinate=02, sec-latency=64 I/O behind bridge: 00003000-00003fff Memory behind bridge: e0200000-e07fffff Prefetchable memory behind bridge: 30000000-37ffffff 00:1f.0 ISA bridge: Intel Corporation 82801DBM (ICH4-M) LPC Interface Bridge (rev 03) Flags: bus master, medium devsel, latency 0 00:1f.1 IDE interface: Intel Corporation 82801DBM (ICH4-M) IDE Controller (rev 03) (prog-if 8a [Master SecP PriP]) Subsystem: Acer Incorporated [ALI] Unknown device 0035 Flags: bus master, medium devsel, latency 0, IRQ 10 I/O ports at 01f0 [size=8] I/O ports at 03f4 [size=1] I/O ports at 0170 [size=8] I/O ports at 0374 [size=1] I/O ports at 1810 [size=16] Memory at 38000000 (32-bit, non-prefetchable) [size=1K] 00:1f.3 SMBus: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) SMBus Controller (rev 03) Subsystem: Acer Incorporated [ALI] Unknown device 0035 Flags: medium devsel, IRQ 10 I/O ports at 1880 [size=32] 00:1f.5 Multimedia audio controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Audio Controller (rev 03) Subsystem: Acer Incorporated [ALI] Unknown device 0035 Flags: bus master, medium devsel, latency 0, IRQ 10 I/O ports at 1c00 [size=256] I/O ports at 18c0 [size=64] Memory at e0100c00 (32-bit, non-prefetchable) [size=512] Memory at e0100800 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2 00:1f.6 Modem: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Modem Controller (rev 03) (prog-if 00 [Generic]) Subsystem: Acer Incorporated [ALI] Unknown device 0035 Flags: medium devsel, IRQ 10 I/O ports at 2400 [size=256] I/O ports at 2000 [size=128] Capabilities: [50] Power Management version 2 02:02.0 Ethernet controller: Broadcom Corporation BCM4401 100Base-T (rev 01) Subsystem: Acer Incorporated [ALI] Unknown device 0035 Flags: bus master, fast devsel, latency 64, IRQ 11 Memory at e0204000 (32-bit, non-prefetchable) [size=8K] Capabilities: [40] Power Management version 2 02:04.0 Network controller: Intel Corporation PRO/Wireless LAN 2100 3B Mini PCI Adapter (rev 04) Subsystem: Intel Corporation MIM2000/Centrino Flags: bus master, medium devsel, latency 64, IRQ 11 Memory at e0206000 (32-bit, non-prefetchable) [size=4K] Capabilities: [dc] Power Management version 2 02:06.0 CardBus bridge: O2 Micro, Inc. OZ711EC1 SmartCardBus Controller (rev 20) Subsystem: Acer Incorporated [ALI] Unknown device 0035 Flags: bus master, stepping, slow devsel, latency 64, IRQ 10 Memory at e0207000 (32-bit, non-prefetchable) [size=4K] Bus: primary=02, secondary=03, subordinate=06, sec-latency=176 Memory window 0: 30000000-33fff000 (prefetchable) Memory window 1: 3c000000-3ffff000 (prefetchable) I/O window 0: 00003000-000030ff I/O window 1: 00003400-000034ff 16-bit legacy interface ports at 0001 02:06.1 CardBus bridge: O2 Micro, Inc. OZ711EC1 SmartCardBus Controller (rev 20) Subsystem: Acer Incorporated [ALI] Unknown device 0035 Flags: bus master, slow devsel, latency 64, IRQ 10 Memory at e0208000 (32-bit, non-prefetchable) [size=4K] Bus: primary=02, secondary=07, subordinate=0a, sec-latency=176 Memory window 0: 34000000-37fff000 (prefetchable) Memory window 1: 40000000-43fff000 I/O window 0: 00003800-000038ff I/O window 1: 00003c00-00003cff 16-bit legacy interface ports at 0001 02:07.0 FireWire (IEEE 1394): Texas Instruments TSB43AB21 IEEE-1394a-2000 Controller (PHY/Link) (prog-if 10 [OHCI]) Subsystem: Acer Incorporated [ALI] Unknown device 0035 Flags: bus master, medium devsel, latency 64, IRQ 10 Memory at e0209000 (32-bit, non-prefetchable) [size=2K] Memory at e0200000 (32-bit, non-prefetchable) [size=16K] Capabilities: [44] Power Management version 2 BIOS: Phoenix VGA-BIOS: Montara-GM 2965 (displayed in the info section of Phoenix BIOS, I don't know if this is important) The display has a special resoltion of 1400x1050 and there is a known problem of the BIOS to not support this resolution. So I have to use the i915resolution tool on linux to be able to use this resolution. Can LinuxBIOS initialize the VGA controller? Or can the original VGA BIOS be used in any way for that? I have seen something mentioned in other artices. On the Acer site there is also a flash tool available. But only for windows. (WinPhlash). Maybe this can help if the LinuxBIOS flash tool doesn't work. http://support.acer-euro.com/drivers/notebook/tm_660.html I understand why initialization of chipset, pci bus, etc is important. Otherwise the OS could not be started. But how important is the initialization of other peripherie like modems, USB controller, VGA, etc.? Isn't this done by the OS driver anyway after LinuxBIOS has started the kernel? regards, Gerhard.

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Re: [LinuxBIOS] r431 - in LinuxBIOSv3: . include include/arch/x86/arch
by Stefan Reinauer 12 Jul '07

12 Jul '07

Please do not remove license headers. All files must have a valid license header, also the imported ones. If we can not determine the license, we can not use the code. * svn(a)openbios.org <svn(a)openbios.org> [070703 18:58]: > Author: uwe > Date: 2007-07-03 18:58:16 +0200 (Tue, 03 Jul 2007) > New Revision: 431 > > Modified: > LinuxBIOSv3/HACKING > LinuxBIOSv3/include/arch/x86/arch/spinlock.h > LinuxBIOSv3/include/spinlock.h > Log: > Document origin of include/arch/x86/arch/spinlock.h and use proper > header. Some other minor fixes (trivial). > > Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> > Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> > > > > Modified: LinuxBIOSv3/HACKING > =================================================================== > --- LinuxBIOSv3/HACKING 2007-07-02 20:57:45 UTC (rev 430) > +++ LinuxBIOSv3/HACKING 2007-07-03 16:58:16 UTC (rev 431) > @@ -95,6 +95,11 @@ > Files: include/asm-i386/processor.h, arch/i386/kernel/cpu/mtrr/state.c > Current version we use: 297d9c035edd04327fedc0d1da27c2b112b66fcc (06/2007) > > +* include/arch/x86/arch/spinlock.h: GPLv2 > + Source: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6 > + Files: include/asm-i386/spinlock.h, include/asm-i386/spinlock_types.h > + Current version we use: 139ec7c416248b9ea227d21839235344edfee1e0 (12/2006) > + > * include/arch/x86/swab.h: GPLv2 > Source: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6 > Current version we use: ? > > Modified: LinuxBIOSv3/include/arch/x86/arch/spinlock.h > =================================================================== > --- LinuxBIOSv3/include/arch/x86/arch/spinlock.h 2007-07-02 20:57:45 UTC (rev 430) > +++ LinuxBIOSv3/include/arch/x86/arch/spinlock.h 2007-07-03 16:58:16 UTC (rev 431) > @@ -1,35 +1,26 @@ > /* > * This file is part of the LinuxBIOS project. > * > + * It is based on the Linux kernel file include/asm-i386/spinlock.h. > + * > + * Modifications are: > * Copyright (C) 2001 Linux Networx > + * (Written by Eric Biederman <ebiederman(a)lnxi.com> for Linux Networx) > * Copyright (C) 2007 coresystems GmbH > - * > - * This program is free software; you can redistribute it and/or modify > - * it under the terms of the GNU General Public License as published by > - * the Free Software Foundation; version 2 of the License. > - * > - * This program is distributed in the hope that it will be useful, > - * but WITHOUT ANY WARRANTY; without even the implied warranty of > - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > - * GNU General Public License for more details. > - * > - * You should have received a copy of the GNU General Public License > - * along with this program; if not, write to the Free Software > - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + * (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) > */ > > #ifndef ARCH_SPINLOCK_H > #define ARCH_SPINLOCK_H > > /* > - * Your basic SMP spinlocks, allowing only a single CPU anywhere > + * Your basic SMP spinlocks, allowing only a single CPU anywhere. > */ > > struct spinlock { > volatile unsigned int lock; > }; > > - > #define SPIN_LOCK_UNLOCKED (struct spinlock) { 1 } > > /* > @@ -38,7 +29,7 @@ > * > * We make no fairness assumptions. They have a cost. > */ > -#define barrier() __asm__ __volatile__("": : :"memory") > +#define barrier() __asm__ __volatile__("": : :"memory") > #define spin_is_locked(x) (*(volatile char *)(&(x)->lock) <= 0) > #define spin_unlock_wait(x) do { barrier(); } while(spin_is_locked(x)) > > @@ -76,5 +67,4 @@ > > #define spin_define(spin) static struct spinlock spin = SPIN_LOCK_UNLOCKED > > - > #endif /* ARCH_SPINLOCK_H */ > > Modified: LinuxBIOSv3/include/spinlock.h > =================================================================== > --- LinuxBIOSv3/include/spinlock.h 2007-07-02 20:57:45 UTC (rev 430) > +++ LinuxBIOSv3/include/spinlock.h 2007-07-03 16:58:16 UTC (rev 431) > @@ -2,20 +2,22 @@ > * This file is part of the LinuxBIOS project. > * > * Copyright (C) 2001 Linux Networx > + * (Written by Eric Biederman <ebiederman(a)lnxi.com> for Linux Networx) > * Copyright (C) 2007 coresystems GmbH > + * (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) > * > * This program is free software; you can redistribute it and/or modify > * it under the terms of the GNU General Public License as published by > * the Free Software Foundation; version 2 of the License. > - * > + * > * This program is distributed in the hope that it will be useful, > * but WITHOUT ANY WARRANTY; without even the implied warranty of > * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > * GNU General Public License for more details. > - * > + * > * You should have received a copy of the GNU General Public License > * along with this program; if not, write to the Free Software > - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > */ > > #ifndef SPINLOCK_H > @@ -32,7 +34,8 @@ > #define spin_unlock_wait(lock) do {} while(0) > #define spin_lock(lock) do {} while(0) > #define spin_unlock(lock) do {} while(0) > -#define spin_define(lock) /* empty */ > +#define spin_define(lock) /* empty */ > + > #endif > > #endif /* SPINLOCK_H */ > > > -- > linuxbios mailing list > linuxbios(a)linuxbios.org > http://www.linuxbios.org/mailman/listinfo/linuxbios > -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

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[LinuxBIOS] [PATCH] Add support for 17 new SMSC Super I/O devices
by Uwe Hermann 12 Jul '07

12 Jul '07

Hi, here's a new generic driver for SMSC Super I/O chips which should put an end to the copy+paste style of development when it comes to Super I/O code in LinuxBIOS and massively reduce the amount of duplicated code. This single piece of code should be able to (currently) handle 17 different SMSC Super I/O chips, more can be added with minimal amount of work (two lines of code). This patch replaces a bunch of v2 Super I/Os, basically "ports" some of the yet unported v1 Super I/Os, and adds support for a bunch of totally new Super I/Os, all in one. The following devices may or may not be (fully) supported by the driver: - FDC37b80x - FDC37m70x - FDC37b78x - FDC37b72x - FDC37m81x - FDC37m60x - LPC47b27x - LPC47m10x - LPC47m112 - LPC47m13x - LPC47m15x - LPC47m192 - LPC47s45x - LPC47b397 - A8000 - DME1737 - SCH5307 The floppy disk controller, the parallel port, the serial ports, and the keyboard controller should work with all the chips. For the more advanced stuff (e.g. HWM, ACPI, SMBus) more work is probably required. So far only the ASUS A8000 has been tested on real hardware (and it works :) The current lpc47b272 and lpc47m10x in v2 can probably be dropped immediately, AFAICS my driver handles everything those two did. Some other devices in v2 do a bit more at the moment and cannot be dropped, yet. As I cannot test all of this on hardware, it would be nice if somebody with a supported board using one of these Super I/Os could replace the respective driver with this new 'smscsuperio' driver and test whether everything works ok. I'm planning similar patches for all other Super I/O vendors, I think we can easily handle 95% of all Super I/Os of each vendor with one such generic driver. I also plan to use the same technique in v3, so we only need very few, generic drivers there, too. Open issues: I don't know if or how we can handle boards with multiple Super I/Os on them. Ideas welcome! Technically the driver reads the device ID of the Super I/O and then initializes only those devices which are supported by that Super I/O. The code is a bit clumsy in parts, suggestions for improvements are welcome! Thanks, Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[LinuxBIOS] r2734 - in trunk/LinuxBIOSv2/src/superio/smsc: . smscsuperio
by svn＠openbios.org 12 Jul '07

12 Jul '07

Author: uwe Date: 2007-07-12 15:13:56 +0200 (Thu, 12 Jul 2007) New Revision: 2734 Added: trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/ trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/Config.lb trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/chip.h trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/superio.c Log: [Arg! Forgot to 'svn add', sorry] Generic driver for pretty much all known Standard Microsystems Corporation (SMSC) Super I/O chips. Most of the SMSC Super I/O chips seem to be similar enough (for our purposes) so that we can handle them with a unified driver. So far only the ASUS A8000 has been tested on real hardware! Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Added: trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/Config.lb 2007-07-12 13:13:56 UTC (rev 2734) @@ -0,0 +1,23 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config chip.h +object superio.o + Added: trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/chip.h (rev 0) +++ trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/chip.h 2007-07-12 13:13:56 UTC (rev 2734) @@ -0,0 +1,30 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <pc80/keyboard.h> +#include <uart8250.h> + +extern struct chip_operations superio_smsc_smscsuperio_ops; + +struct superio_smsc_smscsuperio_config { + struct uart8250 com1, com2; + struct pc_keyboard keyboard; +}; Added: trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c =================================================================== --- trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c (rev 0) +++ trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c 2007-07-12 13:13:56 UTC (rev 2734) @@ -0,0 +1,45 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/romcc_io.h> + +/* All known/supported SMSC Super I/Os have the same logical device IDs + * for the serial ports (COM1, COM2). + */ +#define SMSCSUPERIO_SP1 4 /* Com1 */ +#define SMSCSUPERIO_SP2 5 /* Com2 */ + +/** + * Enable the specified serial port. + * + * @param dev The device to use. + * @param dev The I/O base of the serial port (usually 0x3f8/0x2f8). + */ +static inline void smscsuperio_enable_serial(device_t dev, uint16_t iobase) +{ + uint16_t port = dev >> 8; + + outb(0x55, port); /* Enter the configuration state. */ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + outb(0xaa, port); /* Exit the configuration state. */ +} Added: trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/superio.c =================================================================== --- trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/superio.c (rev 0) +++ trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/superio.c 2007-07-12 13:13:56 UTC (rev 2734) @@ -0,0 +1,335 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Generic driver for pretty much all known Standard Microsystems Corporation + * (SMSC) Super I/O chips. + * + * Datasheets are available from: http://www.smsc.com/main/datasheet.html + * + * Most of the SMSC Super I/O chips seem to be similar enough (for our + * purposes) so that we can handle them with a unified driver. + * + * So far only the ASUS A8000 has been tested on real hardware! + * + * The floppy disk controller, the parallel port, the serial ports, and the + * keyboard controller should work with all the chips. For the more advanced + * stuff (e.g. HWM, ACPI, SMBus) more work is probably required. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <console/console.h> +#include <uart8250.h> +#include <pc80/keyboard.h> +#include "chip.h" + +/* The following Super I/O chips are currently supported by this driver: */ +#define FDC37B80X 0x42 /* Same ID: FDC37M70X (a.k.a. FDC37M707) */ +#define FDC37B78X 0x44 +#define FDC37B72X 0x4c +#define FDC37M81X 0x4d +#define FDC37M60X 0x47 +#define LPC47B27X 0x51 /* a.k.a. LPC47B272 */ +#define LPC47M10X 0x59 /* Same ID: LPC47M112, LPC47M13X */ +#define LPC47M15X 0x60 /* Same ID: LPC47M192 */ +#define LPC47S45X 0x62 +#define LPC47B397 0x6f +#define A8000 0x77 /* ASUS A8000, a rebranded DME1737(?) */ +#define DME1737 0x78 +#define SCH5307 0x81 /* Rebranded LPC47B397(?) */ + +/* Register defines */ +#define DEVICE_ID_REG 0x20 /* Device ID register */ +#define DEVICE_REV_REG 0x21 /* Device revision register */ + +/* Static variables for the Super I/O device ID and revision. */ +static int first_time = 1; +static uint8_t superio_id = 0; +static uint8_t superio_rev = 0; + +/* TODO: Move somewhere else, but where? */ +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +/** + * A list of all possible logical devices which may be supported by at least + * one of the Super I/O chips. These values are used as index into the + * logical_device_table[i].devs array(s). + * + * If you change this enum, you must also adapt the logical_device_table[] + * array and MAX_LOGICAL_DEVICES! + */ +enum { + LD_FDC, /* Floppy disk controller */ + LD_PP, /* Parallel port */ + LD_SP1, /* Serial port 1 (COM1) */ + LD_SP2, /* Serial port 2 (COM2) */ + LD_RTC, /* Real-time clock */ + LD_KBC, /* Keyboard controller */ + LD_AUX, /* Auxiliary I/O */ + LD_XBUS, /* X-Bus */ + LD_HWM, /* Hardware monitor */ + LD_GAME, /* Game port */ + LD_PME, /* Power management events */ + LD_MPU401, /* MPU-401 MIDI UART */ + LD_RT, /* Runtime registers / security key registers */ + LD_ACPI, /* ACPI */ + LD_SMB, /* SMBus */ +}; + +/* Note: This value must match the number of items in the enum above! */ +#define MAX_LOGICAL_DEVICES 15 + +/** + * A table describing the logical devices which are present on the + * supported Super I/O chips. + * + * The first entry (superio_id) is the device ID of the Super I/O chip + * as stored in the (read-only) DEVICE_ID_REG register. + * + * The second entry (devs) is the list of logical device IDs which are + * present on that particular Super I/O chip. A value of -1 means the + * device is not present on that chip. + * + * Note: Do _not_ list chips with different name but same device ID twice! + * The result would be that the init code would be executed twice! + */ +const static struct logical_devices { + uint8_t superio_id; + int devs[MAX_LOGICAL_DEVICES]; +} logical_device_table[] = { + // Chip FDC PP SP1 SP2 RTC KBC AUX XBUS HWM GAME PME MPU RT ACPI SMB + {FDC37B80X,{0, 3, 4, 5, -1, 7, 8, -1, -1, -1, -1, -1, -1, -1, -1}}, + {FDC37B78X,{0, 3, 4, 5, 6, 7, 8, -1, -1, -1, -1, -1, -1, 10, -1}}, + {FDC37B72X,{0, 3, 4, 5, -1, 7, 8, -1, -1, -1, -1, -1, -1, 10, -1}}, + {FDC37M81X,{0, 3, 4, 5, -1, 7, 8, -1, -1, -1, -1, -1, -1, -1, -1}}, + {FDC37M60X,{0, 3, 4, 5, -1, 7, 8, -1, -1, -1, -1, -1, -1, -1, -1}}, + {LPC47B27X,{0, 3, 4, 5, -1, 7, -1, -1, -1, 9, -1, 11, 10, -1, -1}}, + {LPC47M10X,{0, 3, 4, 5, -1, 7, -1, -1, -1, 9, 10, 11, -1, -1, -1}}, + {LPC47M15X,{0, 3, 4, 5, -1, 7, -1, -1, -1, 9, 10, 11, -1, -1, -1}}, + {LPC47S45X,{0, 3, 4, 5, 6, 7, -1, 8, -1, -1, -1, -1, 10, -1, 11}}, + {LPC47B397,{0, 3, 4, 5, -1, 7, -1, -1, 8, -1, -1, -1, 10, -1, -1}}, + {A8000, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}}, + {DME1737, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}}, + {SCH5307, {0, 3, 4, 5, -1, 7, -1, -1, 8, -1, -1, -1, 10, -1, -1}}, +}; + +/** + * Enter the configuration state by writing 0x55 to the config port. + * + * The Super I/O configuration registers can only be modified when the chip + * is in the configuration state. Thus, to program the registers you have + * to a) enter config mode, b) program the registers, c) exit config mode. + * + * @param dev The device to use. + */ +static inline void smsc_pnp_enter_conf_state(device_t dev) +{ + outb(0x55, dev->path.u.pnp.port); +} + +/** + * Exit the configuration state by writing 0xaa to the config port. + * + * This puts the chip into the 'run' state again. + * + * @param dev The device to use. + */ +static inline void smsc_pnp_exit_conf_state(device_t dev) +{ + outb(0xaa, dev->path.u.pnp.port); +} + +/** Wrapper for pnp_set_resources(). */ +static void smsc_pnp_set_resources(device_t dev) +{ + smsc_pnp_enter_conf_state(dev); + pnp_set_resources(dev); + smsc_pnp_exit_conf_state(dev); +} + +/** Wrapper for pnp_enable_resources(). */ +static void smsc_pnp_enable_resources(device_t dev) +{ + smsc_pnp_enter_conf_state(dev); + pnp_enable_resources(dev); + smsc_pnp_exit_conf_state(dev); +} + +/** + * If so configured, enable the specified device, otherwise + * explicitly disable it. + * + * @param dev The device to use. + */ +static void smsc_pnp_enable(device_t dev) +{ + smsc_pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + (dev->enabled) ? pnp_set_enable(dev, 1) : pnp_set_enable(dev, 0); + smsc_pnp_exit_conf_state(dev); +} + +/** + * Initialize those logical devices which need a special init. + * + * @param dev The device to use. + */ +static void smsc_init(device_t dev) +{ + struct superio_smsc_smscsuperio_config *conf = dev->chip_info; + struct resource *res0, *res1; + int i, ld; + + /* Do not initialize disabled devices. */ + if (!dev->enabled) + return; + + /* Find the correct Super I/O. */ + for (i = 0; i < ARRAY_SIZE(logical_device_table); i++) + if (logical_device_table[i].superio_id == superio_id) + break; + + /* If no Super I/O was found, return. */ + if (i == ARRAY_SIZE(logical_device_table)) + return; + + /* A Super I/O was found, so initialize the respective device. */ + ld = dev->path.u.pnp.device; + if (ld == logical_device_table[i].devs[LD_SP1]) { + res0 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com1); + } else if (ld == logical_device_table[i].devs[LD_SP2]) { + res0 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com2); + } else if (ld == logical_device_table[i].devs[LD_KBC]) { + res0 = find_resource(dev, PNP_IDX_IO0); + res1 = find_resource(dev, PNP_IDX_IO1); + init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + } +} + +/** Standard device operations. */ +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = smsc_pnp_set_resources, + .enable_resources = smsc_pnp_enable_resources, + .enable = smsc_pnp_enable, + .init = smsc_init, +}; + +/** + * TODO. + * + * This table should contain all possible entries for any of the supported + * Super I/O chips, even if some of them don't have the respective logical + * devices. That will be handled correctly by our code. + * + * The LD_FOO entries are device markers which tell you the type of the logical + * device (e.g. whether it's a floppy disk controller or a serial port etc.). + * + * Before using pnp_dev_info[] in pnp_enable_devices() these markers have + * to be replaced with the real logical device IDs of the respective + * Super I/O chip. This is done in enable_dev(). + * + * TODO: FDC, PP, SP1, SP2, and KBC should work, the rest probably not (yet). + */ +static struct pnp_info pnp_dev_info[] = { + { &ops, LD_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, }, + { &ops, LD_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, }, + { &ops, LD_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, LD_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, LD_RTC, }, + { &ops, LD_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, + { 0x7ff, 4 },}, + { &ops, LD_AUX, }, + { &ops, LD_XBUS, }, + { &ops, LD_HWM, PNP_IO0, { 0x7f0, 0 }, }, + { &ops, LD_GAME, }, + { &ops, LD_PME, }, + { &ops, LD_MPU401, }, + { &ops, LD_RT, PNP_IO0, { 0x780, 0 }, }, + { &ops, LD_ACPI, }, + { &ops, LD_SMB, }, +}; + +/** + * Enable the logical devices of the Super I/O chip. + * + * TODO: Think about how to handle the case when a mainboard has multiple + * Super I/O chips soldered on. + * TODO: Can this code be simplified a bit? + * + * @param dev The device to use. + */ +static void enable_dev(device_t dev) +{ + int i, j, fn; + int tmp[MAX_LOGICAL_DEVICES]; + + if (first_time) { + /* Read the device ID and revision of the Super I/O chip. */ + smsc_pnp_enter_conf_state(dev); + superio_id = pnp_read_config(dev, DEVICE_ID_REG); + superio_rev = pnp_read_config(dev, DEVICE_REV_REG); + smsc_pnp_exit_conf_state(dev); + + /* TODO: Error handling? */ + + printk_info("Found SMSC Super I/O (ID=0x%02x, rev=0x%02x)\n", + superio_id, superio_rev); + first_time = 0; + } + + /* Find the correct Super I/O. */ + for (i = 0; i < ARRAY_SIZE(logical_device_table); i++) + if (logical_device_table[i].superio_id == superio_id) + break; + + /* If no Super I/O was found, return. */ + if (i == ARRAY_SIZE(logical_device_table)) + return; + + /* Temporarily save the LD_FOO values. */ + for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++) + tmp[j] = pnp_dev_info[j].function; + + /* Replace the LD_FOO markers in pnp_dev_info[] with + * the real logical device IDs of this Super I/O chip. + */ + for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++) { + fn = pnp_dev_info[j].function; + pnp_dev_info[j].function = logical_device_table[i].devs[fn]; + } + + /* Enable the specified devices (if present on the chip). */ + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), + &pnp_dev_info); + + /* Restore LD_FOO values. */ + for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++) + pnp_dev_info[j].function = tmp[j]; +} + +struct chip_operations superio_smsc_smscsuperio_ops = { + CHIP_NAME("Various SMSC Super I/Os") + .enable_dev = enable_dev +};

1 0

[LinuxBIOS] r2733 - trunk/LinuxBIOSv2/src/devices
by svn＠openbios.org 12 Jul '07

12 Jul '07

Author: uwe Date: 2007-07-12 15:12:47 +0200 (Thu, 12 Jul 2007) New Revision: 2733 Modified: trunk/LinuxBIOSv2/src/devices/pnp_device.c Log: Generic driver for pretty much all known Standard Microsystems Corporation (SMSC) Super I/O chips. Most of the SMSC Super I/O chips seem to be similar enough (for our purposes) so that we can handle them with a unified driver. So far only the ASUS A8000 has been tested on real hardware! Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Modified: trunk/LinuxBIOSv2/src/devices/pnp_device.c =================================================================== --- trunk/LinuxBIOSv2/src/devices/pnp_device.c 2007-07-04 17:51:49 UTC (rev 2732) +++ trunk/LinuxBIOSv2/src/devices/pnp_device.c 2007-07-12 13:12:47 UTC (rev 2733) @@ -240,6 +240,10 @@ /* Setup the ops and resources on the newly allocated devices */ for(i = 0; i < functions; i++) { + /* Skip logical devices this Super I/O doesn't have. */ + if (info[i].function == -1) + continue; + path.u.pnp.device = info[i].function; dev = alloc_find_dev(base_dev->bus, &path);

1 0

[LinuxBIOS] r450 - LinuxBIOSv3/arch/x86
by svn＠openbios.org 12 Jul '07

12 Jul '07

Author: stepan Date: 2007-07-12 15:03:53 +0200 (Thu, 12 Jul 2007) New Revision: 450 Modified: LinuxBIOSv3/arch/x86/stage1.c Log: Ensure correct linking independent from compiler settings Signed-off-by: Juergen Beisert <juergen(a)kreuzholzen.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: LinuxBIOSv3/arch/x86/stage1.c =================================================================== --- LinuxBIOSv3/arch/x86/stage1.c 2007-07-12 13:01:42 UTC (rev 449) +++ LinuxBIOSv3/arch/x86/stage1.c 2007-07-12 13:03:53 UTC (rev 450) @@ -52,7 +52,11 @@ post_code(0xf2); } -void stage1_main(u32 bist) +/* + * This function is called from assembler code whith its argument on the + * stack. Force the compiler to generate always correct code for this case. + */ +void __attribute__((stdcall)) stage1_main(u32 bist) { int ret; struct mem_file archive, result;

1 0

[LinuxBIOS] r449 - in LinuxBIOSv3: arch/x86/geodelx include/arch/x86 lib northbridge/amd/geodelx
by svn＠openbios.org 12 Jul '07

12 Jul '07

Author: uwe Date: 2007-07-12 15:01:42 +0200 (Thu, 12 Jul 2007) New Revision: 449 Removed: LinuxBIOSv3/include/arch/x86/hlt.h Modified: LinuxBIOSv3/arch/x86/geodelx/geodelx.c LinuxBIOSv3/include/arch/x86/cpu.h LinuxBIOSv3/lib/console.c LinuxBIOSv3/lib/ram.c LinuxBIOSv3/northbridge/amd/geodelx/raminit.c Log: Merge hlt() into cpu.h where it belongs. Add some documentation. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: LinuxBIOSv3/arch/x86/geodelx/geodelx.c =================================================================== --- LinuxBIOSv3/arch/x86/geodelx/geodelx.c 2007-07-12 01:26:43 UTC (rev 448) +++ LinuxBIOSv3/arch/x86/geodelx/geodelx.c 2007-07-12 13:01:42 UTC (rev 449) @@ -25,7 +25,7 @@ #include <console.h> #include <msr.h> #include <io.h> -#include <hlt.h> +#include <cpu.h> #include <amd_geodelx.h> #include <spd.h> #include <legacy.h> Modified: LinuxBIOSv3/include/arch/x86/cpu.h =================================================================== --- LinuxBIOSv3/include/arch/x86/cpu.h 2007-07-12 01:26:43 UTC (rev 448) +++ LinuxBIOSv3/include/arch/x86/cpu.h 2007-07-12 13:01:42 UTC (rev 449) @@ -181,9 +181,21 @@ */ static inline void cpu_relax(void) { - __asm__ __volatile__("rep;nop" : : : "memory"); + __asm__ __volatile__("rep; nop" : : : "memory"); } +/** + * Shut down the CPU. + * + * This function is '__attribute__((always_inline))' because it might be + * called before RAM is set up, thus pushing stuff on stack (for a function + * call) will not work. + */ +static inline __attribute__((always_inline)) void hlt(void) +{ + __asm__ __volatile__("hlt" : : : "memory"); +} + /* Random other functions. These are not architecture-specific, except they * really are in many ways. Seperate the PC from the "X86" is hard. */ Deleted: LinuxBIOSv3/include/arch/x86/hlt.h =================================================================== --- LinuxBIOSv3/include/arch/x86/hlt.h 2007-07-12 01:26:43 UTC (rev 448) +++ LinuxBIOSv3/include/arch/x86/hlt.h 2007-07-12 13:01:42 UTC (rev 449) @@ -1,29 +0,0 @@ -/* - * This file is part of the LinuxBIOS project. - * - * Copyright (C) 2007 Stefan Reinauer <stepan(a)coresystems.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef ARCH_X86_HLT_H -#define ARCH_X86_HLT_H - -static inline __attribute__((always_inline)) void hlt(void) -{ - asm("hlt"); -} - -#endif /* ARCH_X86_HLT_H */ Modified: LinuxBIOSv3/lib/console.c =================================================================== --- LinuxBIOSv3/lib/console.c 2007-07-12 01:26:43 UTC (rev 448) +++ LinuxBIOSv3/lib/console.c 2007-07-12 13:01:42 UTC (rev 449) @@ -1,5 +1,5 @@ #include <types.h> -#include <hlt.h> +#include <cpu.h> #include <console.h> #include <uart8250.h> #include <stdarg.h> @@ -57,13 +57,11 @@ " starting...\n"; printk(BIOS_INFO, console_test); - } void die(const char *str) { printk(BIOS_EMERG, str); - do { + while (1) hlt(); - } while (1); } Modified: LinuxBIOSv3/lib/ram.c =================================================================== --- LinuxBIOSv3/lib/ram.c 2007-07-12 01:26:43 UTC (rev 448) +++ LinuxBIOSv3/lib/ram.c 2007-07-12 13:01:42 UTC (rev 449) @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <hlt.h> +#include <cpu.h> #include <console.h> /** Modified: LinuxBIOSv3/northbridge/amd/geodelx/raminit.c =================================================================== --- LinuxBIOSv3/northbridge/amd/geodelx/raminit.c 2007-07-12 01:26:43 UTC (rev 448) +++ LinuxBIOSv3/northbridge/amd/geodelx/raminit.c 2007-07-12 13:01:42 UTC (rev 449) @@ -25,7 +25,7 @@ #include <msr.h> #include <spd.h> #include <io.h> -#include <hlt.h> +#include <cpu.h> #include <amd_geodelx.h> #include <southbridge/amd/cs5536/cs5536.h>

1 0

[LinuxBIOS] Virtual Iron and AMD Pacifica
by Savchenko Mikhail 12 Jul '07

12 Jul '07

Any ideas about running Virtual Iron virtual machines hypervisor via LinuxBIOS is it possible, and what about hardware virtualization (Pacifica) of AMD64 CPUs support in LinuxBIOS, is it works?

2 1

Re: [LinuxBIOS] r447 - in LinuxBIOSv3: include/device mainboard/emulation/qemu-x86
by Stefan Reinauer 12 Jul '07

12 Jul '07

* svn(a)openbios.org <svn(a)openbios.org> [070712 03:03]: > Some minor cosmetic fixes (trivial). > -/* > - * PCI Class, Vendor and Device IDs > - * > - * Please keep sorted. > - */ > - Why is removing comments considered a cosmetic fix? -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/

2 1

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coreboot July 2007