coreboot December 2007

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[LinuxBIOS] r3026 - trunk/util/flashrom
by svn＠openbios.org 29 Dec '07

29 Dec '07

Author: hailfinger Date: 2007-12-29 11:15:58 +0100 (Sat, 29 Dec 2007) New Revision: 3026 Modified: trunk/util/flashrom/spi.c Log: Print the chip status register for all SPI chips on probe if verbose output is specified. Pretty-print the chip status register (including block lock information) for ST M25P family and Macronix MX25L family chips. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Modified: trunk/util/flashrom/spi.c =================================================================== --- trunk/util/flashrom/spi.c 2007-12-29 10:14:38 UTC (rev 3025) +++ trunk/util/flashrom/spi.c 2007-12-29 10:15:58 UTC (rev 3026) @@ -78,6 +78,8 @@ uint16_t it8716f_flashport = 0; +void generic_spi_prettyprint_status_register(struct flashchip *flash); + /* Generic Super I/O helper functions */ uint8_t regval(uint16_t port, uint8_t reg) { @@ -220,7 +222,7 @@ { if (it8716f_flashport) return it8716f_spi_command(it8716f_flashport, writecnt, readcnt, writearr, readarr); - printf("%s called, but no SPI chipset detected\n", __FUNCTION__); + printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__); return 1; } @@ -230,7 +232,7 @@ if (generic_spi_command(JEDEC_RDID_OUTSIZE, JEDEC_RDID_INSIZE, cmd, readarr)) return 1; - printf("RDID returned %02x %02x %02x.\n", readarr[0], readarr[1], readarr[2]); + printf_debug("RDID returned %02x %02x %02x.\n", readarr[0], readarr[1], readarr[2]); return 0; } @@ -260,8 +262,14 @@ manuf_id = readarr[0]; model_id = (readarr[1] << 8) | readarr[2]; printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, manuf_id, model_id); - if (manuf_id == flash->manufacture_id && model_id == flash->model_id) + if (manuf_id == flash->manufacture_id && model_id == flash->model_id) { + /* Print the status register before erase to tell the + * user about possible write protection. + */ + generic_spi_prettyprint_status_register(flash); + return 1; + } } return 0; @@ -277,13 +285,48 @@ return readarr[0]; } +/* Prettyprint the status register. Works for + * ST M25P series + * MX MX25L series + */ +void generic_spi_prettyprint_status_register_st_m25p(uint8_t status) +{ + printf_debug("Chip status register: Status Register Write Disable " + "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); + printf_debug("Chip status register: Bit 6 is " + "%sset\n", (status & (1 << 6)) ? "" : "not "); + printf_debug("Chip status register: Bit 5 is " + "%sset\n", (status & (1 << 5)) ? "" : "not "); + printf_debug("Chip status register: Block Protect 2 (BP2) is " + "%sset\n", (status & (1 << 4)) ? "" : "not "); + printf_debug("Chip status register: Block Protect 1 (BP1) is " + "%sset\n", (status & (1 << 3)) ? "" : "not "); + printf_debug("Chip status register: Block Protect 0 (BP0) is " + "%sset\n", (status & (1 << 2)) ? "" : "not "); + printf_debug("Chip status register: Write Enable Latch (WEL) is " + "%sset\n", (status & (1 << 1)) ? "" : "not "); + printf_debug("Chip status register: Write In Progress (WIP) is " + "%sset\n", (status & (1 << 0)) ? "" : "not "); +} + +void generic_spi_prettyprint_status_register(struct flashchip *flash) +{ + uint8_t status; + + status = generic_spi_read_status_register(); + printf_debug("Chip status register is %02x\n", status); + switch (flash->manufacture_id) { + case ST_ID: + case MX_ID: + if ((flash->model_id & 0xff00) == 0x2000) + generic_spi_prettyprint_status_register_st_m25p(status); + break; + } +} + int generic_spi_chip_erase_c7(struct flashchip *flash) { const unsigned char cmd[] = JEDEC_CE_C7; - uint8_t statusreg; - - statusreg = generic_spi_read_status_register(); - printf("chip status register before erase is %02x\n", statusreg); generic_spi_write_enable(); /* Send CE (Chip Erase) */

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[LinuxBIOS] r3025 - trunk/util/flashrom
by svn＠openbios.org 29 Dec '07

29 Dec '07

Author: hailfinger Date: 2007-12-29 11:14:38 +0100 (Sat, 29 Dec 2007) New Revision: 3025 Modified: trunk/util/flashrom/flashchips.c Log: Add 25VF016B support to flashrom. Untested, but verified against the data sheet. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2007-12-28 00:23:29 UTC (rev 3024) +++ trunk/util/flashrom/flashchips.c 2007-12-29 10:14:38 UTC (rev 3025) @@ -48,6 +48,8 @@ probe_29f002, erase_29f002, write_29f002}, {"MX25L4005", MX_ID, MX_25L4005, 512, 4 * 1024, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + {"SST25VF016B", SST_ID, SST_25VF016B, 2048, 256, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, {"SST29EE020A", SST_ID, SST_29EE020A, 256, 128, probe_jedec, erase_chip_jedec, write_jedec}, {"SST28SF040A", SST_ID, SST_28SF040, 512, 256,

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[LinuxBIOS] problem about dram init
by aaron lwe 28 Dec '07

28 Dec '07

On Dec 27, 2007 1:22 PM, ron minnich <rminnich(a)gmail.com> wrote: > yes I think you are probably right but how are the fixed mtrr's set? > > I don't know, This still seems like memory timing issues to me but who > knows. > > ron > ron, you're right, it's a dram configuration problem. after I set the dram clocking control and signal timing control registers, it worked well after enabling memory cache. Hmm...these registers have nothing to do when cache disabled? and they are not mentioned in the bios porting guide either

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Re: [LinuxBIOS] [AMD690G] : Newbies asking => How to get support for a new chipset ?
by Carl-Daniel Hailfinger 28 Dec '07

28 Dec '07

Hello Cedric, On 28.12.2007 15:26, cedric.rivera(a)externe.bnpparibas.com wrote: > What do we need to add support for a new system board or chipset ? > > lspci -v # ok, I can do that ;-) > lspci -vvnnx # yes, there's no mistake superiotool -d # see http://linuxbios.org/Superiotool flashrom -V # see http://linuxbios.org/Flashrom Superiotool and Flashrom are in our LinuxBIOS v2 code repository. > Can we get some information from AMD about chipset ? > Usually yes, but most of the time you don't need this information if the chipset is already supported. Regards, Carl-Daniel

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[LinuxBIOS] [AMD690G] : Newbies asking => How to get support for a new chipset ?
by cedric.rivera＠externe.bnpparibas.com 28 Dec '07

28 Dec '07

Hello everybody, I am quite new to LinuxBios and I want to help this wonderful project but I don't know how so here I am asking : What do we need to add support for a new system board or chipset ? lspci -v # ok, I can do that ;-) and what else ? Can we get some information from AMD about chipset ? Thank you for your attention. I'm sorry for the signature but it comes from the corporation ... This message and any attachments (the "message") is intended solely for the addressees and is confidential. If you receive this message in error, please delete it and immediately notify the sender. Any use not in accord with its purpose, any dissemination or disclosure, either whole or partial, is prohibited except formal approval. The internet can not guarantee the integrity of this message. BNP PARIBAS (and its subsidiaries) shall (will) not therefore be liable for the message if modified. Do not print this message unless it is necessary, consider the environment. --------------------------------------------- Ce message et toutes les pieces jointes (ci-apres le "message") sont etablis a l'intention exclusive de ses destinataires et sont confidentiels. Si vous recevez ce message par erreur, merci de le detruire et d'en avertir immediatement l'expediteur. Toute utilisation de ce message non conforme a sa destination, toute diffusion ou toute publication, totale ou partielle, est interdite, sauf autorisation expresse. L'internet ne permettant pas d'assurer l'integrite de ce message, BNP PARIBAS (et ses filiales) decline(nt) toute responsabilite au titre de ce message, dans l'hypothese ou il aurait ete modifie. N'imprimez ce message que si necessaire, pensez a l'environnement.

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[LinuxBIOS] Change BIOS option for end-user?
by Jun Koi 28 Dec '07

28 Dec '07

Hi, In normal computer, end-users can change the BIOS options when they turn on their computer (like press DEL, enter BIOS screen, change options, then "Exit and Save"....). How can we do that with LinuxBIOS? Clearly we can change the source code, recompile and reflash back to the BIOS, but that is not supposed to do for the end-users. There must be easier way.... Thanks, Jun

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[LinuxBIOS] Intel 3100 chipset
by Ed Swierk 27 Dec '07

27 Dec '07

The attached patch includes preliminary support for the Intel 3100 integrated northbridge/southbridge/superio (http://www.intel.com/design/chipsets/embedded/3100.htm). So far the code has been tested only on the Mt. Arvon development board (http://www.intel.com/design/intarch/devkits/pm3100.htm), which includes a 1.8GHz Pentium M and DDR2-400 ECC DRAM. The code works well enough to boot Linux 2.6.23.1 with serial console (on the 3100's UART), IOAPIC, working USB, and working DRAM (memtest86 passes). The kernel reports the CPU is running at 600MHz; haven't figured out how to crank it up to full speed. A number of features are incomplete or untested, including PCI Express and IDE/SATA. The southbridge code was adapted from 6300esb, the northbridge from e7520, and I forget where the mainboard code came from. Kudos to whoever implemented those. I'm working with a fairly old version of LinuxBIOSv2 so the patch probably breaks the latest svn. Nevertheless: Signed-off-by: Ed Swierk <eswierk(a)arastra.com> --Ed

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[LinuxBIOS] Lightning talk at FSCONS 2007
by joe＠smittys.pointclark.net 27 Dec '07

27 Dec '07

So how did the Lightning talk at FSCONS 2007 in Gothenburg go? Do you have any video's for us Peter?? Thanks - Joe

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[LinuxBIOS] r3024 build service
by LinuxBIOS information 27 Dec '07

27 Dec '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "hailfinger" checked in revision 3024 to the LinuxBIOS source repository and caused the following changes: Change Log: Add Intel 3100 integrated northbridge/southbridge/superio PCI IDs. Signed-off-by: Ed Swierk <eswierk(a)arastra.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=3024&device=serengeti_che… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

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[LinuxBIOS] r3024 - trunk/LinuxBIOSv2/src/include/device
by svn＠openbios.org 27 Dec '07

27 Dec '07

Author: hailfinger Date: 2007-12-28 01:23:29 +0100 (Fri, 28 Dec 2007) New Revision: 3024 Modified: trunk/LinuxBIOSv2/src/include/device/pci_ids.h Log: Add Intel 3100 integrated northbridge/southbridge/superio PCI IDs. Signed-off-by: Ed Swierk <eswierk(a)arastra.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/LinuxBIOSv2/src/include/device/pci_ids.h =================================================================== --- trunk/LinuxBIOSv2/src/include/device/pci_ids.h 2007-12-21 17:21:03 UTC (rev 3023) +++ trunk/LinuxBIOSv2/src/include/device/pci_ids.h 2007-12-28 00:23:29 UTC (rev 3024) @@ -2326,6 +2326,17 @@ #define PCI_DEVICE_ID_INTEL_6300ESB_PCI_X 0x25ae #define PCI_DEVICE_ID_INTEL_6300ESB_WDT 0x25ab +/* Intel 3100 */ +#define PCI_DEVICE_ID_INTEL_3100_ISA 0x2670 +#define PCI_DEVICE_ID_INTEL_3100_EHCI 0x268c +#define PCI_DEVICE_ID_INTEL_3100_PCI 0x244e +#define PCI_DEVICE_ID_INTEL_3100_USB 0x2688 +#define PCI_DEVICE_ID_INTEL_3100_SMB 0x269b +#define PCI_DEVICE_ID_INTEL_3100_USB2 0x2689 +#define PCI_DEVICE_ID_INTEL_3100_USB3 0x268c +#define PCI_DEVICE_ID_INTEL_3100_SATA 0x2680 +#define PCI_DEVICE_ID_INTEL_3100_SATA_R 0x2681 + #define PCI_DEVICE_ID_INTEL_80310 0x530d #define PCI_DEVICE_ID_INTEL_82810_MC1 0x7120 #define PCI_DEVICE_ID_INTEL_82810_IG1 0x7121 @@ -2352,6 +2363,8 @@ #define PCI_DEVICE_ID_INTEL_PCIE_PA1 0x3596 #define PCI_DEVICE_ID_INTEL_PCIE_PB 0x3597 #define PCI_DEVICE_ID_INTEL_PCIE_PC 0x3599 +#define PCI_DEVICE_ID_INTEL_PCIE_QA 0x35b6 +#define PCI_DEVICE_ID_INTEL_PCIE_QA1 0x35b7 #define PCI_VENDOR_ID_COMPUTONE 0x8e0e #define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291

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coreboot December 2007