On Dec 27, 2007 1:22 PM, ron minnich <rminnich(a)gmail.com> wrote:
> yes I think you are probably right but how are the fixed mtrr's set?
>
> I don't know, This still seems like memory timing issues to me but who
> knows.
>
> ron
>
ron, you're right, it's a dram configuration problem.
after I set the dram clocking control and signal timing
control registers, it worked well after enabling memory
cache. Hmm...these registers have nothing to do when
cache disabled? and they are not mentioned in the
bios porting guide either
Hello Cedric,
On 28.12.2007 15:26, cedric.rivera(a)externe.bnpparibas.com wrote:
> What do we need to add support for a new system board or chipset ?
>
> lspci -v # ok, I can do that ;-)
>
lspci -vvnnx # yes, there's no mistake
superiotool -d # see http://linuxbios.org/Superiotool
flashrom -V # see http://linuxbios.org/Flashrom
Superiotool and Flashrom are in our LinuxBIOS v2 code repository.
> Can we get some information from AMD about chipset ?
>
Usually yes, but most of the time you don't need this information if the
chipset is already supported.
Regards,
Carl-Daniel
Hello everybody,
I am quite new to LinuxBios and I want to help this wonderful project
but I don't know how so here I am asking :
What do we need to add support for a new system board or chipset ?
lspci -v # ok, I can do that ;-)
and what else ?
Can we get some information from AMD about chipset ?
Thank you for your attention.
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Hi,
In normal computer, end-users can change the BIOS options when they
turn on their computer (like press DEL, enter BIOS screen, change
options, then "Exit and Save"....). How can we do that with LinuxBIOS?
Clearly we can change the source code, recompile and reflash back to
the BIOS, but that is not supposed to do for the end-users. There must
be easier way....
Thanks,
Jun
The attached patch includes preliminary support for the Intel 3100
integrated northbridge/southbridge/superio
(http://www.intel.com/design/chipsets/embedded/3100.htm). So far the
code has been tested only on the Mt. Arvon development board
(http://www.intel.com/design/intarch/devkits/pm3100.htm), which
includes a 1.8GHz Pentium M and DDR2-400 ECC DRAM.
The code works well enough to boot Linux 2.6.23.1 with serial console
(on the 3100's UART), IOAPIC, working USB, and working DRAM (memtest86
passes). The kernel reports the CPU is running at 600MHz; haven't
figured out how to crank it up to full speed. A number of features are
incomplete or untested, including PCI Express and IDE/SATA.
The southbridge code was adapted from 6300esb, the northbridge from
e7520, and I forget where the mainboard code came from. Kudos to
whoever implemented those.
I'm working with a fairly old version of LinuxBIOSv2 so the patch
probably breaks the latest svn. Nevertheless:
Signed-off-by: Ed Swierk <eswierk(a)arastra.com>
--Ed
Dear LinuxBIOS readers!
This is the automated build check service of LinuxBIOS.
The developer "hailfinger" checked in revision 3024 to
the LinuxBIOS source repository and caused the following
changes:
Change Log:
Add Intel 3100 integrated northbridge/southbridge/superio PCI IDs.
Signed-off-by: Ed Swierk <eswierk(a)arastra.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
Build Log:
Compilation of amd:serengeti_cheetah_fam10 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=3024&device=serengeti_che…
If something broke during this checkin please be a pain
in hailfinger's neck until the issue is fixed.
If this issue is not fixed within 24h the revision should
be backed out.
Best regards,
LinuxBIOS automatic build system