coreboot December 2007

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[LinuxBIOS] [patch] MSI MS-7135 (this time with attachment)

by jakllsch＠kollasch.net

Initial support for MSI MS-7135 (K8N Neo3) mainboard. Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net>

13 years, 7 months

[LinuxBIOS] Qemu compile for LinuxBIOSV2

by Marc Karasek

I am trying to get up to speed on LinuxBIOS and to that end have tried to compile both v3 & v2 for qemu. I have successfully compiled and run v3 with a filo package on my Fedora 8 system. When I try to compile v2 with a filo.elf payload I get the : collect2: ld terminated with signal 11 [Segmentation fault] Error In looking at the compile it has gotten through the compile part and is linking. rm -f linuxbios.a ar cr linuxbios.a malloc.o pci_ops.o smbus_ops.o memset.o pci_ops_auto.o linuxbios_table.o fallback_boot.o pciexp_device.o keyboard.o pnp_device.o printk.o irq_tables.o pcix_device.o i8259.o pci_device.o console.o elfboot.o hardwaremain.o boot.o exception.o delay.o version.o pci_ops_mmconf.o memcmp.o isa-dma.o hypertransport.o vtxprintf.o tables.o root_device.o cardbus_device.o uart8250.o device_util.o ./option_table.o compute_ip_checksum.o device.o northbridge.o memcpy.o agp_device.o vgabios.o clog2.o pirq_routing.o memmove.o pci_ops_conf2.o pci_ops_conf1.o mc146818rtc.o rom_stream.o c_start.o vsprintf.o cpu.o static.o gcc -m32 -nostdlib -r -o linuxbios_ram.o c_start.o mainboard.o uart8250_console.o linuxbios.a /usr/lib/gcc/i386-redhat-linux/4.1.2/libgcc.a gcc -m32 -nostdlib -nostartfiles -static -o linuxbios_ram -T /home/mk216460/src/LinuxBIOSv2-2988/src/config/linuxbios_ram.ld linuxbios_ram.o collect2: ld terminated with signal 11 [Segmentation fault] make[1]: *** [linuxbios_ram] Error 1 make[1]: Leaving directory `/home/mk216460/src/LinuxBIOSv2-2988/targets/emulation/qemu-i386/qemu-i386/image' In looking at the /var/log/messages you see Nov 30 14:37:02 dhcp-uatl04-156-163 kernel: ld[3691]: segfault at 00000030 eip 08068b2c esp bfc6a0f0 error 4 Any help/pointers for what to look at would be helpful. -- /********************* Marc Karasek MTS Sun Microsystems mailto:marc.karasek@sun.com ph:770.360.6415 *********************/

13 years, 7 months

[LinuxBIOS] [PATCH] flashrom: add support for the ST M25P family

by Carl-Daniel Hailfinger

Add support for ST M25P05-A, M25P10-A, M25P20, M25P40, M25P16, M25P32, M25P64, M25P128 to flashrom. ST M25P80 support is already there. Not tested, but conforming to data sheets. Pretty-print the chip status register (including block lock information) for ST M25P family chips on erase. Print the chip status register for all SPI chips on erase. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-m25p/flash.h =================================================================== --- flashrom-m25p/flash.h (Revision 3009) +++ flashrom-m25p/flash.h (Arbeitskopie) @@ -172,7 +172,15 @@ * byte of device ID is related to log(bitsize) at least for some chips. */ #define ST_ID 0x20 /* ST */ +#define ST_M25P05A 0x2010 +#define ST_M25P10A 0x2011 +#define ST_M25P20 0x2012 +#define ST_M25P40 0x2013 #define ST_M25P80 0x2014 +#define ST_M25P16 0x2015 +#define ST_M25P32 0x2016 +#define ST_M25P64 0x2017 +#define ST_M25P128 0x2018 #define ST_M50FLW040A 0x08 #define ST_M50FLW040B 0x28 #define ST_M50FLW080A 0x80 Index: flashrom-m25p/flashchips.c =================================================================== --- flashrom-m25p/flashchips.c (Revision 3009) +++ flashrom-m25p/flashchips.c (Arbeitskopie) @@ -140,8 +140,24 @@ probe_jedec, erase_chip_jedec, write_jedec}, {"M29F040B", ST_ID, ST_M29F040B, 512, 64 * 1024, probe_29f040b, erase_29f040b, write_29f040b}, + {"M25P05-A", ST_ID, ST_M25P05A, 64, 32 * 1024, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + {"M25P10-A", ST_ID, ST_M25P10A, 128, 32 * 1024, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + {"M25P20", ST_ID, ST_M25P20, 256, 64 * 1024, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + {"M25P40", ST_ID, ST_M25P40, 512, 64 * 1024, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, {"M25P80", ST_ID, ST_M25P80, 1024, 64 * 1024, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + {"M25P16", ST_ID, ST_M25P16, 2048, 64 * 1024, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + {"M25P32", ST_ID, ST_M25P32, 4096, 64 * 1024, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + {"M25P64", ST_ID, ST_M25P64, 8192, 64 * 1024, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + {"M25P128", ST_ID, ST_M25P128, 16384, 256 * 1024, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, {"82802ab", 137, 173, 512, 64 * 1024, probe_82802ab, erase_82802ab, write_82802ab}, {"82802ac", 137, 172, 1024, 64 * 1024, Index: flashrom-m25p/spi.c =================================================================== --- flashrom-m25p/spi.c (Revision 3009) +++ flashrom-m25p/spi.c (Arbeitskopie) @@ -277,14 +277,45 @@ return readarr[0]; } +void generic_spi_prettyprint_status_register_st_m25p(uint8_t status) +{ + printf("Chip status register: Status Register Write Disable (SRWD) is " + "%sset\n", (status & (1 << 7)) ? "" : "not "); + printf("Chip status register: Block Protect 2 (BP2) is " + "%sset\n", (status & (1 << 4)) ? "" : "not "); + printf("Chip status register: Block Protect 1 (BP1) is " + "%sset\n", (status & (1 << 3)) ? "" : "not "); + printf("Chip status register: Block Protect 0 (BP0) is " + "%sset\n", (status & (1 << 2)) ? "" : "not "); + printf("Chip status register: Write Enable Latch (WEL) is " + "%sset\n", (status & (1 << 1)) ? "" : "not "); + printf("Chip status register: Write In Progress (WIP) is " + "%sset\n", (status & (1 << 7)) ? "" : "not "); +} + +void generic_spi_prettyprint_status_register(struct flashchip *flash) +{ + uint8_t status; + + status = generic_spi_read_status_register(); + printf("Chip status register is %02x\n", status); + switch (flash->manufacture_id) { + case ST_ID: + if ((flash->model_id & 0xff00) == 0x2000) + generic_spi_prettyprint_status_register_st_m25p(status); + break; + } +} + int generic_spi_chip_erase_c7(struct flashchip *flash) { const unsigned char cmd[] = JEDEC_CE_C7; - uint8_t statusreg; + + /* Print the status register before erase to tell the user about + * possible write protection. + */ + generic_spi_prettyprint_status_register(flash); - statusreg = generic_spi_read_status_register(); - printf("chip status register before erase is %02x\n", statusreg); - generic_spi_write_enable(); /* Send CE (Chip Erase) */ generic_spi_command(JEDEC_CE_C7_OUTSIZE, JEDEC_CE_C7_INSIZE, cmd, NULL);

13 years, 7 months

[LinuxBIOS] Intel 3100 chipset, version 2

by Ed Swierk

Here is an updated patch against the latest snapshot. I fixed a bunch of bugs and verified that SATA, PCI slot, and PCI Express (port A) slot are working. --Ed

13 years, 7 months

[LinuxBIOS] [PATCH] Fix FireWire on GA M57 SLI-S4

by Torsten Duwe

Now I have a FireWire disk to play with. Adding an interrupt description vastly improves its performance under LinuxBIOS ;-) Potential ACKers please verify 01:0a.0 is not assigned any APIC pin so far. Comment and sign-off in the attachment. This file is quite messy. Torsten

13 years, 7 months

[LinuxBIOS] [Fwd: Re: AMD 690G chipset support in LinuxBIOS v2]

by Marc Jones

Meant to send this to the list. Marc -------- Original Message -------- Subject: Re: [LinuxBIOS] AMD 690G chipset support in LinuxBIOS v2 Date: Mon, 10 Sep 2007 21:05:47 -0600 From: Marc Jones <Marc.Jones(a)AMD.com> To: Darmawan Salihun <darmawan.salihun(a)gmail.com> References: <46893e740709101937j32a4f32bu6dc296a628d36dc6(a)mail.gmail.com> Darmawan Salihun wrote: > Hi all, > I've grepped through the source code last night but haven't found > code for board that uses this chipset. Is there any support coming > down the road? I'm planning to buy a new system for BIOS experiments > in the next few days. This chipset is a candidate for me. I want a > chipset with onboard video and K8 processor. > I choose K8 because the datasheet for the memory controller is > readily available. I'm open for any suggestion(s). Basically, I just > want a system that can run Vista, support multicore processor and can > be used for LinuxBIOS experiments (preferably without soldering stuff > needed). > Anyway, one further question: hot-flashing can be done on SPI > chips as well, right? > > > Regards, > > Darmawan Salihun > -------------------------------------------------------------------- > -= Human knowledge belongs to the world =- Hi Darmawan, Currently there is no support in LinuxBIOS for any ATI(now AMD) chipsets. We do plan to work on this in the next six months but I don't have a specific release date. == Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors

13 years, 7 months

[LinuxBIOS] Fwd: rdcmos

by ron minnich

Here from the author (Eric Hendriks) are the tools to read and write cmos. Thanks ron

13 years, 8 months

[LinuxBIOS] r3021 build service

by LinuxBIOS information

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "cozzie" checked in revision 3021 to the LinuxBIOS source repository and caused the following changes: Change Log: More abuild fixes, this should be the last (trivial) Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=3021&device=serengeti_che… If something broke during this checkin please be a pain in cozzie's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

13 years, 8 months

Re: [LinuxBIOS] different versions of the GA-M57SLI-S4 (PLCC vs SPI)

by Carl-Daniel Hailfinger

On 23.09.2007 23:16, echelon(a)free.fr wrote: > Quoting Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>: >> OK, I have the 0.2 and 0.3 datasheet of IT8716F and I can't find any >> difference in interfaces between the datasheets. Please be more specific >> what you think has been replaced (including page numbers). > Simply the pinout.. (please compare the pin-out diagram btw the 2 version of > the DS). I did. Pages 7-23 (Pin configuration) are exactly the same for 0.2 and 0.3. Please tell me the page number where you see any differences. > In fact, there could be another explanation : I talked about this issue with a > hardware specialist at my work (he has worked into the IC design..) and his > hypothesis is that the component which is actually used on this motherboard is a > "custom" revision especially crafted by ITE for Gigabyte.. (yes, they had > "volume" so they could afford to make a deal for a custom revision..) Maybe. I still want to find out why your data sheet seems to differ from mine. Regards, Carl-Daniel

13 years, 8 months

[LinuxBIOS] [PATCH] remove duplicated microcode updates for some Intel processors

by Carl-Daniel Hailfinger

The following mainboards had a file named microcode_updates.c in their mainboard directories, but the code was not referenced anywhere. intel/jarrell dell/s1850 supermicro/x6dhr_ig2 supermicro/x6dhr_ig supermicro/x6dhe_g2 supermicro/x6dhe_g Besides that, the contents of these files were either duplicates of src/cpu/intel/model_f3x/microcode_M1DF340E.h or src/cpu/intel/model_f3x/microcode_M1DF3413.h. To apply this removal, execute svn remove for the following files: src/mainboard/supermicro/x6dhe_g/microcode_updates.c src/mainboard/supermicro/x6dhe_g2/microcode_updates.c src/mainboard/supermicro/x6dhr_ig/microcode_updates.c src/mainboard/supermicro/x6dhr_ig2/microcode_updates.c src/mainboard/dell/s1850/microcode_updates.c src/mainboard/intel/jarrell/microcode_updates.c Abuild tested, as expected no failures. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> No patch attached because a pure removal patch sized 148 kB is a bit too large to be sent without a need for code review.

13 years, 8 months

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coreboot December 2007