coreboot December 2007

coreboot@coreboot.org

78 participants
271 discussions

[LinuxBIOS] [PATCH] rewrite generic x86 CAR code
by Carl-Daniel Hailfinger 08 Jan '08

08 Jan '08

This patch is an attempt at introducing 4k CAR size granularity for the generic x86 code. For the old supported CAR sizes, the newly generated code is equivalent, so it should be a no-brainer. Add a copyright header to the code, the header is derived from the one found in the same piece of code in v3. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-CARx86/src/cpu/x86/car/cache_as_ram.inc =================================================================== --- LinuxBIOSv2-CARx86/src/cpu/x86/car/cache_as_ram.inc (Revision 3026) +++ LinuxBIOSv2-CARx86/src/cpu/x86/car/cache_as_ram.inc (Arbeitskopie) @@ -1,3 +1,28 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2005 Eswar Nallusamy, LANL + * Copyright (C) 2005 Tyan + * (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan) + * Copyright (C) 2007 coresystems GmbH + * (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) + * Copyright (C) 2007 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + /* We will use 4K bytes only */ /* disable HyperThreading is done by eswar*/ /* other's is the same as AMD except remove amd specific msr */ @@ -106,39 +131,61 @@ jmp clear_fixed_var_mtrr clear_fixed_var_mtrr_out: -#if CacheSize == 0x10000 - /* enable caching for 64K using fixed mtrr */ +/* 0x06 is the WB IO type for a given 4k segment. + * segs is the number of 4k segments we want to use for CAR. + * subpart is the nth 32-bit window into IO type configuration. + * reg is the register where the IO type should be stored. + */ +.macro extractmask segs, subpart, reg +.if \segs - (\subpart * 4) <= 0 + xorl \reg, \reg +.elseif \segs - (\subpart * 4) == 1 + movl $0x06000000, \reg +.elseif \segs - (\subpart * 4) == 2 + movl $0x06060000, \reg +.elseif \segs - (\subpart * 4) == 3 + movl $0x06060600, \reg +.elseif \segs - (\subpart * 4) >= 4 + movl $0x06060606, \reg +.endif +.endm +.macro simplemask_helper segs, subpart +.if \subpart & 0x1 + extractmask \segs, \subpart, %eax +.else + extractmask \segs, \subpart, %edx +.endif +.endm +/* size is the cache size in bytes we want to use for CAR. + * part is the nth 64-bit window into IO type configuration. + */ +.macro simplemask size, part + simplemask_helper (\size / 0x1000), (\part * 2 + 1) + simplemask_helper (\size / 0x1000), (\part * 2) +.endm + +#if CacheSize > 0x10000 +#error Invalid CAR size, must be at most 64k. +#endif +#if CacheSize < 0x1000 +#error Invalid CAR size, must be at least 4k. This is a processor limitation. +#endif +#if (CacheSize & (0x1000 - 1)) +#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation. +#endif + +#if CacheSize > 0x8000 + /* enable caching for 32K-64K using fixed mtrr */ movl $0x268, %ecx /* fix4k_c0000*/ - movl $0x06060606, %eax /* WB IO type */ - movl %eax, %edx + simplemask CacheSize, 1 wrmsr - movl $0x269, %ecx - wrmsr #endif -#if CacheSize == 0x8000 - /* enable caching for 32K using fixed mtrr */ + /* enable caching for 0-32K using fixed mtrr */ movl $0x269, %ecx /* fix4k_c8000*/ - movl $0x06060606, %eax /* WB IO type */ - movl %eax, %edx + simplemask CacheSize, 0 wrmsr -#endif - /* enable caching for 16K/8K/4K using fixed mtrr */ - movl $0x269, %ecx /* fix4k_cc000*/ -#if CacheSize == 0x4000 - movl $0x06060606, %edx /* WB IO type */ -#endif -#if CacheSize == 0x2000 - movl $0x06060000, %edx /* WB IO type */ -#endif -#if CacheSize == 0x1000 - movl $0x06000000, %edx /* WB IO type */ -#endif - xorl %eax, %eax - wrmsr - - #else /* disable cache */ movl %cr0, %eax

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[LinuxBIOS] Kino LX800 AMD Geode based board
by markw 03 Jan '08

03 Jan '08

Ok, talking to guys on IRC and they said to post up here. I've been challenged to see if I can come up with a system that boots in sub 10 seconds to a command prompt with networking. I'm sitting on a few Kino LX800 boards that we use for other projects, but I'm willing to sacrifice one for this. The board has sata onboard using an ALI M5281 controller. It also uses the geode CS5536 ide controller, so the sata stuff may not be an issue. >From reading/talking to people, this board should be minimal prompt at around 7 seconds. I've got access to device programmers and 2m repair stuff, so flashing isn't a huge issue. Would this be a good board for a proof of concept, or should I look at something else. The board is a Kino LX800, AMD GEODE 500mhz, sata/pata, onboard amd video, onboard realtek 8139 ethernet. I'd like to to LB and kernel in flash, but if the hardware won't suppor a 16mbit flash, then I'll do lb/filo and boot from CF over the standard ide channel. The board currently has a 49fl004 socketed flash. Plan on using a stripped down debian install, since that's the only one I can reliably shrink. Thanks, Mark Here's all the specs: http://tinyurl.com/3ajv9l Here's the output of lspci. 00:01.0 Host bridge: Advanced Micro Devices [AMD] Unknown device 2080 (rev 31) 00:01.1 VGA compatible controller: Advanced Micro Devices [AMD] Geode LX Video 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block 00:0e.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03) 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01) 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01) 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02) 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02) 00:10.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) 00:11.0 Mass storage controller: ALi Corporation ALi M5281 Serial ATA / RAID Host Controller (rev a4) 00:11.1 Mass storage controller: ALi Corporation M5228 ALi ATA/RAID Controller (rev c6) 00:12.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) Here's the more verbose lspci output recommend by the guys on irc. 00:01.0 0600: 1022:2080 (rev 31) Subsystem: 1022:2080 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 248, Cache Line Size: 32 bytes Region 0: I/O ports at ac1c [size=4] Region 1: I/O ports at 9e00 [size=8] 00: 22 10 80 20 05 00 20 02 31 00 00 06 08 f8 80 00 10: 1d ac 00 00 01 9e 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 80 20 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:01.1 0300: 1022:2081 Subsystem: 1022:2081 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 11 Region 0: Memory at ee000000 (32-bit, non-prefetchable) [size=16M] Region 1: Memory at efff4000 (32-bit, non-prefetchable) [size=16K] Region 2: Memory at efff0000 (32-bit, non-prefetchable) [size=16K] Region 3: Memory at effec000 (32-bit, non-prefetchable) [size=16K] Region 4: Memory at effe8000 (32-bit, non-prefetchable) [size=16K] 00: 22 10 81 20 07 00 20 02 00 00 00 03 08 00 00 00 10: 00 00 00 ee 00 40 ff ef 00 00 ff ef 00 c0 fe ef 20: 00 80 fe ef 00 00 00 00 00 00 00 00 22 10 81 20 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00 00:01.2 1010: 1022:2082 Subsystem: 1022:2082 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 11 Region 0: Memory at effe4000 (32-bit, non-prefetchable) [size=16K] 00: 22 10 82 20 06 00 a0 02 00 00 10 10 08 00 00 00 10: 00 40 fe ef 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 82 20 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00 00:0e.0 0200: 10ec:8139 (rev 10) Subsystem: 10ec:8139 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR+ Latency: 32 (8000ns min, 16000ns max) Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at f200 [size=256] Region 1: Memory at effff000 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: ec 10 39 81 07 00 90 82 10 00 00 02 00 20 00 00 10: 01 f2 00 00 00 f0 ff ef 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 20 40 00:0f.0 0601: 1022:2090 (rev 03) Subsystem: 1022:2090 Control: I/O+ Mem- BusMaster- SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Region 0: I/O ports at 6000 [size=8] Region 1: I/O ports at 6100 [size=256] Region 2: I/O ports at 6200 [size=64] Region 3: I/O ports at 1000 [size=32] Region 4: I/O ports at 9d00 [size=128] Region 5: I/O ports at 9c00 [size=64] 00: 22 10 90 20 09 00 a0 02 03 00 01 06 08 40 80 00 10: 01 60 00 00 01 61 00 00 01 62 00 00 01 10 00 00 20: 01 9d 00 00 01 9c 00 00 00 00 00 00 22 10 90 20 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0f.2 0101: 1022:209a (rev 01) (prog-if 80) Subsystem: 1022:209a Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 248, Cache Line Size: 32 bytes Region 0: [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [disabled] [size=8] Region 1: [virtual] Memory at 000003f0 (type 3, non-prefetchable) [disabled] [size=1] Region 2: [virtual] Memory at 00000170 (32-bit, non-prefetchable) [disabled] [size=8] Region 3: [virtual] Memory at 00000370 (type 3, non-prefetchable) [disabled] [size=1] Region 4: I/O ports at ff00 [size=16] 00: 22 10 9a 20 05 00 a0 02 01 80 01 01 08 f8 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 ff 00 00 00 00 00 00 00 00 00 00 22 10 9a 20 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0f.3 0401: 1022:2093 (rev 01) Subsystem: 1022:2093 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin B routed to IRQ 11 Region 0: I/O ports at fe00 [size=128] 00: 22 10 93 20 05 00 a0 02 01 00 01 04 08 00 00 00 10: 01 fe 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 93 20 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 02 00 00 00:0f.4 0c03: 1022:2094 (rev 02) (prog-if 10) Subsystem: 1022:2094 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin D routed to IRQ 11 Region 0: Memory at efffe000 (32-bit, non-prefetchable) [size=4K] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 22 10 94 20 06 00 30 02 02 10 03 0c 08 00 00 00 10: 00 e0 ff ef 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 94 20 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 04 00 00 00:0f.5 0c03: 1022:2095 (rev 02) (prog-if 20) Subsystem: 1022:2095 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin D routed to IRQ 11 Region 0: Memory at efffd000 (32-bit, non-prefetchable) [size=4K] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 22 10 95 20 06 00 30 02 02 20 03 0c 08 00 00 00 10: 00 d0 ff ef 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 95 20 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 04 00 00 00:10.0 0200: 10ec:8139 (rev 10) Subsystem: 10ec:8139 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (8000ns min, 16000ns max) Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at f000 [size=256] Region 1: Memory at efffc000 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: ec 10 39 81 07 00 90 02 10 00 00 02 00 20 00 00 10: 01 f0 00 00 00 c0 ff ef 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 20 40 00:11.0 0180: 10b9:5281 (rev a4) (prog-if 85) Subsystem: 10b9:5281 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 128, Cache Line Size: 512 bytes Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at fd00 [size=8] Region 1: I/O ports at fc00 [size=4] Region 2: I/O ports at fb00 [size=8] Region 3: I/O ports at fa00 [size=4] Region 4: I/O ports at f900 [size=16] [virtual] Expansion ROM at 20000000 [disabled] [size=64K] 00: b9 10 81 52 05 00 a0 02 a4 85 80 01 80 80 80 00 10: 01 fd 00 00 01 fc 00 00 01 fb 00 00 01 fa 00 00 20: 01 f9 00 00 00 00 00 00 00 00 00 00 b9 10 81 52 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00 00:11.1 0180: 10b9:5228 (rev c6) (prog-if 85) Subsystem: 10b9:5281 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 128 Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at f800 [size=8] Region 1: I/O ports at f700 [size=4] Region 2: I/O ports at f600 [size=8] Region 3: I/O ports at f500 [size=4] Region 4: I/O ports at f400 [size=16] 00: b9 10 28 52 05 00 a0 02 c6 85 80 01 00 80 80 00 10: 01 f8 00 00 01 f7 00 00 01 f6 00 00 01 f5 00 00 20: 01 f4 00 00 00 00 00 00 a0 00 00 00 b9 10 81 52 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00 00:12.0 0200: 10ec:8139 (rev 10) Subsystem: 10ec:8139 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (8000ns min, 16000ns max) Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at ee00 [size=256] Region 1: Memory at efffb000 (32-bit, non-prefetchable) [size=256] [virtual] Expansion ROM at 20010000 [disabled] [size=64K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1+,D2+,D3hot+,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: ec 10 39 81 07 00 90 02 10 00 00 02 00 20 00 00 10: 01 ee 00 00 00 b0 ff ef 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 20 40

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[LinuxBIOS] [lbv2][patch]Support i18n'd GCCs
by Patrick Georgi 03 Jan '08

03 Jan '08

Hi, attached patch fixes build on i18n'd GCCs which might not emit "install:" as expected. Regards, Patrick Georgi

2 1

Re: [LinuxBIOS] RES: VGA Support on AMD DB800
by Jordan Crouse 02 Jan '08

02 Jan '08

On 26/12/07 10:50 -0200, Omar Esteves Duarte Filho wrote: > Jordan, > > Thank you again! > > I removed splash and quiet form the menu.lst and added "console=tty0 > console=ttyS0,115200", as you can see below: > > title Ubuntu 7.10, kernel 2.6.23.9-geodelx-fb > root (hd0,0) > kernel /boot/vmlinuz-2.6.23.9-geodelx-fb > root=UUID=a4e4ac87-c677-45e1-a > a21-1e4654feac95 ro vga=771 console=tty0 console=ttyS0,115200 > initrd /boot/initrd.img-2.6.23.9-geodelx-fb > > I got some success here: startx works, but there's still no vga console > before X starts. I think there is some problem with the lxfb driver because, > if i switch the line " Device "AMD" " by "Device "Generic Video Card"" in > the xorg.conf file, I get no result. lxfb and fbcon are built into the > kernel. This is starting to get off topic for the linuxbios list, but I'll answer it here since others might have the same problem. X and the kernel have nothing to do with one-another - they are completely seperate entities. If you do not see the text console (and the penguin) once the kernel has started, then something has gone wrong. Please send the dmesg output from your kernel, and your kernel config. Jordan

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[LinuxBIOS] problem about dram init
by aaron lwe 02 Jan '08

02 Jan '08

Dear All, I'm terribly sorry that I just found I've mistakenly configured the dram MA Map Type, and now memtest showed no errors. But I still have to reduce the mem size when reporting to system through ram_resource or filo couldn't be started. I have disabled the integrated graphics card and the agp, so I don't think the top memory should be reserved for frame buffer.

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[LinuxBIOS] Proposed changes to cpu/intel organization
by Corey Osgood 31 Dec '07

31 Dec '07

With the latest microcde update, there's one big problem: size. I haven't gotten to work yet on the model_f* cpus, but with the model_6xx cpus, we're way over the size barrier. So, I'd like to propose some changes to the organization, mostly for the better. The directory structure, in the end, would look something like this: cpu/intel/: /intel_generic/: contains generic intel init code, used by all intel cpus. Also contains a generic driver, with no microcode updates and _all_ intel CPU IDs, for using an OS microcode update. /microcode/: contains all microcode files from the most recent update (20070907), along with current microcode update code. /slot_1_p2/: contains CPU IDs and microcode updates for Slot 1 P2s, P2-based Celerons, and mobile P2/P2-based Celerons /slot_1_p3/: Same as above, except for P3s, no mobiles /socket_370/: Same as above, for Socket 370 and mobile CPUs etc, etc. Benefits: * We gain the latest microcode updates and support for every current Intel CPU, including Core/Core 2 (on an experimental, but it should work, basis). * Removal of a bunch of repeated code, no more model_xxx folders/confusion, just select a socket Side Effects: * The end user needs to select between p2 and p3 cpus for slot 1 systems. This may also come up in LGA775-based systems, due to size constraints * The code looks somewhat ugly I've attached intel_init.c, which is the generic intel CPU init, and slot_1_p2.c, which uses it, so you can see what I'm talking about. slot_1_p2.c was formerly just slot_1.c, so commented microcode updates and the appropriate CPU IDs will be removed. Feedback greatly appreciated! Thanks, Corey

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[LinuxBIOS] r3031 build service
by LinuxBIOS information 31 Dec '07

31 Dec '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "hailfinger" checked in revision 3031 to the LinuxBIOS source repository and caused the following changes: Change Log: Unfortunately, EN29F002T, EN29F002AT, EN29F002ANT, EN29F002NT all have exactly the same ID. Improve model number printing. Add EN29F002(A)(N)B support while I'm at it. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Markus Boas <bios(a)ryven.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=3031&device=serengeti_che… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

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Re: [LinuxBIOS] [PATCH] flashrom: Support EON EN29F002(A)(N)B, improve naming for the EN29F002 series
by Carl-Daniel Hailfinger 31 Dec '07

31 Dec '07

On 31.12.2007 08:24, Markus wrote: > Am Mon, 31 Dec 2007 03:07:15 +0100 > schrieb Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>: > >> On 30.12.2007 21:09, Markus wrote: >> >>> The Chip is an EN29F002NT. >>> >>> >> What do you think about this patch? >> >> Unfortunately, EN29F002T, EN29F002AT, EN29F002ANT, EN29F002NT all have >> exactly the same ID. Improve model number printing. >> Add EN29F002(A)(N)B support while I'm at it. >> Signed-off-by: Carl-Daniel Hailfinger >> <c-d.hailfinger.devel.2006(a)gmx.net> >> >> Index: flashrom-eon/flash.h >> =================================================================== >> --- flashrom-eon/flash.h (Revision 3030) >> +++ flashrom-eon/flash.h (Arbeitskopie) >> @@ -109,8 +109,8 @@ >> #define EN_29F040A 0x7F04 >> #define EN_29LV010 0x7F6E >> #define EN_29LV040A 0x7F4F /* EN_29LV040(A) */ >> -#define EN_29F002AT 0x7F92 >> -#define EN_29F002AB 0x7F97 >> +#define EN_29F002T 0x7F92 >> +#define EN_29F002B 0x7F97 >> >> #define FUJITSU_ID 0x04 /* Fujitsu */ >> /* MBM29F400TC_STRANGE has a value not mentioned in the data sheet >> and we Index: flashrom-eon/flashchips.c >> =================================================================== >> --- flashrom-eon/flashchips.c (Revision 3030) >> +++ flashrom-eon/flashchips.c (Arbeitskopie) >> @@ -42,9 +42,10 @@ >> probe_jedec, erase_chip_jedec, write_jedec}, >> {"At49F002(N)T",ATMEL_ID, AT_49F002NT, 256, >> 256, probe_jedec, erase_chip_jedec, write_jedec}, >> - /* The EN29F002AT can do byte program at arbitrary >> boundaries. */ >> - {"EN29F002AT", EON_ID, >> EN_29F002AT, 256, 256, >> + {"EN29F002(A)(N)T", EON_ID, EN_29F002T, >> 256, 256, probe_jedec, erase_chip_jedec, write_jedec}, >> + {"EN29F002(A)(N)B", EON_ID, EN_29F002B, >> 256, 256, >> + probe_jedec, erase_chip_jedec, write_jedec}, >> {"MBM29F400TC", FUJITSU_ID, >> MBM29F400TC_STRANGE, 512, 64 * 1024, probe_m29f400bt, >> erase_m29f400bt, write_linuxbios_m29f400bt}, {"MX29F002", >> MX_ID, MX_29F002, 256, 64 * 1024, >> >> >> >> > I think the patch is okay. > > Acked-by: Markus Boas bios(a)ryven.de > Thanks, r3031. Regards, Carl-Daniel

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[LinuxBIOS] r3031 - trunk/util/flashrom
by svn＠openbios.org 31 Dec '07

31 Dec '07

Author: hailfinger Date: 2007-12-31 15:05:08 +0100 (Mon, 31 Dec 2007) New Revision: 3031 Modified: trunk/util/flashrom/flash.h trunk/util/flashrom/flashchips.c Log: Unfortunately, EN29F002T, EN29F002AT, EN29F002ANT, EN29F002NT all have exactly the same ID. Improve model number printing. Add EN29F002(A)(N)B support while I'm at it. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Markus Boas <bios(a)ryven.de> Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2007-12-31 01:49:00 UTC (rev 3030) +++ trunk/util/flashrom/flash.h 2007-12-31 14:05:08 UTC (rev 3031) @@ -109,8 +109,8 @@ #define EN_29F040A 0x7F04 #define EN_29LV010 0x7F6E #define EN_29LV040A 0x7F4F /* EN_29LV040(A) */ -#define EN_29F002AT 0x7F92 -#define EN_29F002AB 0x7F97 +#define EN_29F002T 0x7F92 +#define EN_29F002B 0x7F97 #define FUJITSU_ID 0x04 /* Fujitsu */ /* MBM29F400TC_STRANGE has a value not mentioned in the data sheet and we Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2007-12-31 01:49:00 UTC (rev 3030) +++ trunk/util/flashrom/flashchips.c 2007-12-31 14:05:08 UTC (rev 3031) @@ -42,9 +42,10 @@ probe_jedec, erase_chip_jedec, write_jedec}, {"At49F002(N)T",ATMEL_ID, AT_49F002NT, 256, 256, probe_jedec, erase_chip_jedec, write_jedec}, - /* The EN29F002AT can do byte program at arbitrary boundaries. */ - {"EN29F002AT", EON_ID, EN_29F002AT, 256, 256, + {"EN29F002(A)(N)T", EON_ID, EN_29F002T, 256, 256, probe_jedec, erase_chip_jedec, write_jedec}, + {"EN29F002(A)(N)B", EON_ID, EN_29F002B, 256, 256, + probe_jedec, erase_chip_jedec, write_jedec}, {"MBM29F400TC", FUJITSU_ID, MBM29F400TC_STRANGE, 512, 64 * 1024, probe_m29f400bt, erase_m29f400bt, write_linuxbios_m29f400bt}, {"MX29F002", MX_ID, MX_29F002, 256, 64 * 1024,

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[LinuxBIOS] r3030 build service
by LinuxBIOS information 30 Dec '07

30 Dec '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "hailfinger" checked in revision 3030 to the LinuxBIOS source repository and caused the following changes: Change Log: Add continuation ID support to jedec.c The continuation ID code does not go further than checking for IDs of the type 0x7fXX, but does this for vendor and product ID. The current published JEDEC spec has a list where the largest vendor ID is 7 bytes long, but all leading bytes are 0x7f. The list will grow in the future, and using a 64bit variable will not be enough anymore. Besides that, it seems that the location of the ID byte after the first continuation ID byte is very vendor specific, so we may have to revisit that code some time in the future. (Suggestion for a new encoding: Use a two-byte data type for the ID, the lower byte contains the only non-0x7f byte, the upper byte contains the number of 0x7f bytes used as prefix, which is the bank number minus 1 the vendor ID appears in.) Add support for EON EN29F002AT. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=3030&device=serengeti_che… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

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coreboot December 2007