September 2017 - coreboot - mail.coreboot.org

Re: [coreboot] How is depreciating 95% of coreboot boards worth it for such minor improvements?
by Kyösti Mälkki Sept. 21, 2017

Sept. 21, 2017

On Thu, Sep 21, 2017 at 10:16 AM, David Hendricks <david.hendricks(a)gmail.com> wrote: > > > On Sun, Sep 10, 2017 at 1:42 PM, Piotr Król <piotr.krol(a)3mdeb.com> wrote: >> >> 2. Is cbmem required ? (Geode LX do not have support for cpufreq - >> cbmem complains) > I can help you to get these to EARLY_CBMEM_INIT. That's the first obstacle with Geode. It's recommended that coreboot would store the timebase / TSC information so that cpufreq support is not needed in kernel. I have some on-going work on AMD timestamps anyways. > > Yes, though hopefully we can patch cbmem to deal with this. I am only > guessing but it seems it will fail in arch_tick_frequency()? Is there a way > of differentiating Geode from other architectures and determining ticks per > second? > >> >> 3. There is seem to be some glitches in the system - not sure if >> triggered by us eg. alix.6 bootlog link seems to be broken. > > > More details will help. Do you mean supported boards table, and the 3rd column from left for ALIX 2C or ALIX 6 has invalid links? That would not be your fault. When alix.2d was pushed to board_status, it also refreshes .2c and .6 entries even when they don't exist as individual updates on the wiki. Kyösti

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SPI Flash debug console on H8SCM
by Fabian Sept. 21, 2017

Sept. 21, 2017

Hi everyone, I try to get coreboot run on my H8SCM. Sadly I get no log over serial or USB. So I want to give SPI console a try. It seems to be a very new feature introduced here [1]. When I compile coreboot it fails with this warning: warning: (CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CONSOLE_SPI_FLASH) selects BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY which has unmet direct dependencies (SPI_FLASH && BOOT_DEVICE_SPI_FLASH_RW_NOMMAP) As written in [1] it's only tested for Skylake. How much effort is necessary to port it to my board? Are there more Information about SPI console? Or is there an other way to get log from my board? One more question to the AMD experts: There are two motherboard models "H8SCM" and "H8SCM (Fam10)". Whats the difference? Greetings, Fabian [1] https://mail.coreboot.org/pipermail/coreboot/2017-June/084538.html

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64 UEFI payload boot fail on Denverton platform but 32 UEFI payload works
by Melissa Yi Sept. 21, 2017

Sept. 21, 2017

Hi I want to know whether coreboot supports 64bit UEFI payload on denverton platform? Attached the fail log. Thanks. Regards, Melissa Yi

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Re: [coreboot] How is depreciating 95% of coreboot boards worth it for such minor improvements?
by Piotr Król Sept. 21, 2017

Sept. 21, 2017

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 On 08/24/2017 04:31 AM, Kyösti Mälkki wrote: > On Thu, Aug 24, 2017 at 12:29 AM, Taiidan(a)gmx.com <Taiidan(a)gmx.com> > wrote: Hi Kyösti, (...) > > Now, this applies to everyone: please push status updates for the > boards you have access to, otherwise majority of AGESA boards just > hit that deprecation in the next cycle of board removals. Also, > when you create a board port and you go through all the trouble of > getting it past (my strict or someone else's less strict) review > policy, is it REALLY that hard to run board_status script? You know > who you are. Is there something we need to do better here? Provide > OS boot images just for this purpose? > > As for binaryPI boards, those are at EARLY_CBMEM_INIT starting from > August 2. I'm not sure if it helps, but we can commit to test all PC Engines platform. 3 weeks ago we obtained all ALIX platforms. Unfortunately things like ALIX.1C are no longer in production (replaced by ALIX.1E). Development recovery for platforms not touched for 3 years takes time. We are confused about various pieces when trying to upload recent board status: 1. How to handle situation when hardware was replaced by new revision ? 2. Is cbmem required ? (Geode LX do not have support for cpufreq - cbmem complains) 3. There is seem to be some glitches in the system - not sure if triggered by us eg. alix.6 bootlog link seems to be broken. We feel responsible for PC Engines platforms and keeping them in coreboot tree. Things that I think we can do better is: 1. Adding missing wiki pages for PC Engines platforms. 2. Adding people from 3mdeb as official maintainers of PC Engines platforms - would that be accepted ? Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com -----BEGIN PGP SIGNATURE----- iQIzBAEBCAAdFiEE4DCbLYWmfoRjKeNLsu5x6WeqnkwFAlm1o6UACgkQsu5x6Weq nkwMvxAAgOijbfWN9Q40h3y6XTJ67M7fe6EoZSkbM225waWnBTkDXoXMUYhpYOZ5 OvKU2bDsVrcQdcorKD7giA36/SXnDTRqdmNfCxNNmIruc+J65DIopcX3MzYUpb7S LyA/Jnb3dQXPE3Wb14sGG7bj74keDXUsMJGIb3AG7xNEgPvBzSzEX5AuZBQzn8DJ 48ffbIzZHNLDebZw7M3q4D/pnxcEaEWm8vG6bRfpT3UHyj7iOMnKN8kpK0KGtGN5 PXT9SkqeX75D2I72eO/TzGSUSDcxbBLozWIDoeEBXZ0Hslu5blyDl9gINb7F0U5s 2SokXUEMNpokHzPP0w21j5dX0xN5yC8QqMOMDna6M6ACeNpS4+MS23DPG0bb6jwc 3yfaMpK0t1UxdArOoMdRBZdqxeemHdp9M3z+FlwWe2QonmPQXpdRWtma3ptKQgSX 4YaiCgNYj47elo9nryX4k7g5gNkNoCAcUNHnHw5Odm8tWjAf6Y5g7Kz+ZqCaWsdL uZlDbNnEYkOUHZ8amZYIEB1cgMHebF+ESaO4fhgcdQUdGWBirB96+Lnmgjxiqw2x fbuwlt8vA1gS77VDJ1lU3GqO0XQnYfRscEXv7AJdmzIbmOexnnB0sAhUCt71BANV qcBNZ7qcGV7o+BPZgtl78r5xpNdKIopEjb09ZcBx/qjcnVyAQjY= =qiF7 -----END PGP SIGNATURE-----

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Re: [coreboot] How is depreciating 95% of coreboot boards worth it for such minor improvements?
by David Hendricks Sept. 21, 2017

Sept. 21, 2017

On Fri, Aug 25, 2017 at 4:41 PM, David Hendricks <david.hendricks(a)gmail.com> wrote: > On Thu, Aug 24, 2017 at 11:12 AM, Renze Nicolai <renze(a)rnplus.nl> wrote: > >> Another thing: I don't understand the workflow for putting my >> boardstatus on the wiki yet. Could someone explain to me how I can >> publish on the wiki that my board works with a certain version of >> Coreboot? > > I took a swing at updating documentation on the wiki (so it's searchable): https://www.coreboot.org/Board_Status Note: The wiki is a bit ahead at the moment and assumes the following patch set is applied: https://review.coreboot.org/#/c/21566/ Also: how can I add a wiki page for my board? >> > Go to the wiki, click "Log In", and request an account from the admins.

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Re: [coreboot] Coreboot support for atom c3000
by Piotr Król Sept. 18, 2017

Sept. 18, 2017

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA512 On 09/17/2017 03:08 AM, Martin Roth wrote: Hi Martin, > Hi Tirumalesh, The patch for the main code is here: > https://review.coreboot.org/#/c/20861/ SOC code: > https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/denve rton_ns > > The only board that uses it right now is the CRB: > https://review.coreboot.org/#/c/20862/ Mainboard code: > https://review.coreboot.org/cgit/coreboot.git/tree/src/mainboard/intel /harcuvar I > can't see any information about FSP. Is there FSP binary used for this platform ? Both with Tirumalesh we asked Intel, but they point to documentation that I have no access to. I would at least want to know what are the plans with Denverton support. Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com -----BEGIN PGP SIGNATURE----- iQIzBAEBCgAdFiEE4DCbLYWmfoRjKeNLsu5x6WeqnkwFAlnAIb8ACgkQsu5x6Weq nkx99g//TnSQ0UQsmHBm7ydyHfW1mEyjbdTPe1v/9mcQWyR2G8n3+WWd+KB/3bFX ZwlTX/UpKmom3WJweKfjT5mDd+1BM/6fqNrGPTxfqm2mYK90o7kxqBLE5HzD0v1u Fa6ps+sEzU3RolZEbs6kVpPfz6e6IXM1lqBbfeDIXB92Jm3B9YUA4/NMHwrKYNjG VvfttR9R0wjrtCbni7qSV5GbzYAlkawuklEnmzxAn/N8QWRW6ndrrDXDBUuLPBAA RN3jG326WUQ50IFig1+1L9pw/a6edfhUh//+REeTrf8Ko+MZ5Pji2AWD9HScjLzW c493B0ccZm3B8o7b7lykaSHNiPdmrqsI7UfxsjeOzqVl57oNBsdj9LtLANwpdypI 88D/1/0+6X1BGqneIdfcul6Xwt7dSJ4JojEa03UFVT59lQMYqWE7Mt+v58SN+i5B zz6ORsXftmVAi48wnjPvteRo01K2mdi7OK/g+Gu4oQu5S9VTQJok5qf++Un8o9Ry 7T08Qecd/samnKfarfgK1MBM0ysASgmB7EDwpd3k/hWubpkFnVEtXpU8zSuZZzdE N8o8SwnqGUUhleyrcGRWNE1LdQ0KVR+OCOhVaFpncD91i2EJWfTQo978TEqfQGDG HwmeKl0OahjddHOXViUFgfb5MDPa2q7xPMRBWeLOqcvqI56Tc08= =O2U9 -----END PGP SIGNATURE-----

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Re: [coreboot] Coreboot support for atom c3000
by Tirumalesh Sept. 18, 2017

Sept. 18, 2017

Thanks Martin. On Sat, Sep 16, 2017 at 6:08 PM, Martin Roth <gaumless(a)gmail.com> wrote: > Hi Tirumalesh, The patch for the main code is here: https://review.coreboot.org/#/c/20861/ SOC code: https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/denverton_… The only board that uses it right now is the CRB: https://review.coreboot.org/#/c/20862/ Mainboard code: https://review.coreboot.org/cgit/coreboot.git/tree/src/mainboard/intel/harc… Martin On Wed, Sep 13, 2017 at 8:02 PM, Tirumalesh wrote: > Hi Martin, > > Thanks for the info, > where can i find list of boards supported with c2000. > > Also is the c3000 patches available in mailing list/source tree? > > Thanks, > Tirumalesh. > > -------- Original Message -------- > Subject: Re: [coreboot] Coreboot support for atom c3000 > Local Time: September 13, 2017 5:42 PM > UTC Time: September 14, 2017 12:42 AM > From: gaumless(a)gmail.com > To: Tirumalesh > coreboot(a)coreboot.org > > Hi Tirumalesh, > Coreboot does support c2000 - "Rangeley", and there are patches in > review for c3000 currently. > > Martin > > On Tue, Sep 12, 2017 at 2:48 PM, Tirumalesh > wrote: >> Hi, >> >> I am new to coreboot, could someone help me understand >> >> 1. Does coreboot support atom c2000 and in future c3000 once intel fsp is >> available? >> 2. Is there any limitations of intel atom support. >> 3. How much effort is it to port coreboot to new board based on intel Atom >> >> Thanks in advance. >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://mail.coreboot.org/mailman/listinfo/coreboot > > @chalamarla.com> @coreboot.org> @chalamarla.com> @chalamarla.com>

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doubts on FSP
by 王翔 Sept. 17, 2017

Sept. 17, 2017

I try to understand coreboot source for x86 (intel/kblrvp). But I have encountered some difficulties. In romstage fsp_memory_init, try to find fspm.bin. ``` if (cbfs_boot_locate(&file_desc, name, NULL)) { printk(BIOS_CRIT, "Could not locate %s in CBFS\n", name); die("FSPM not available!\n"); } ``` But my firmware not contain. ``` ➜ coreboot git:(master) build/cbfstool build/coreboot.rom print Name Offset Type Size cbfs master header 0x0 cbfs header 32 fallback/romstage 0x80 stage 36876 cpu_microcode_blob.bin 0x9100 microcode 0 fallback/ramstage 0x9180 stage 75335 vgaroms/seavgabios.bin 0x1b800 raw 27648 config 0x22480 raw 107 revision 0x22540 raw 570 spd.bin 0x227c0 spd 2048 cmos_layout.bin 0x23000 cmos_layout 1132 fallback/postcar 0x234c0 stage 24932 fallback/dsdt.aml 0x29680 raw 16738 fallback/payload 0x2d840 payload 63916 payload_config 0x3d240 raw 1652 payload_revision 0x3d900 raw 234 (empty) 0x3da40 null 1713240 mrc.cache 0x1dfec0 mrc_cache 65536 (empty) 0x1eff00 null 16280 bootblock 0x1f3ec0 bootblock 49152 ➜ coreboot git:(master) build/cbfstool build/coreboot.rom layout -w This image contains the following sections that can be accessed with this tool: 'BIOS' (read-only, size 2097152) 'FMAP' (read-only, size 256) 'COREBOOT' (CBFS, size 2096896) It is at least possible to perform the read action on every section listed above. ``` ------------------ 王翔安全研究员广州市腾御安信息科技有限公司广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024

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Re: [coreboot] Berlin Meeting 21. Sep Thursday @afra_berlin
by Taiidan＠gmx.com Sept. 17, 2017

Sept. 17, 2017

On 09/17/2017 04:39 AM, One7two99 via coreboot wrote: > If possible I'd like to, but in a less agressive way (afraid to remove the Bios-Chip physically). > I also would like to setup Coreboot with vga-blob/SeaBios which seems to be a bit more complicated. > > If needed I can figure out the Type of BiosChip in advance. > > Kind regards > > - O7 The X230 doesn't need a VGA blob and you don't remove the SOIC-8 chip you simply attach a clip to it.

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Berlin Usergroup Meeting 10. August Thursday (different location)
by Alexander Couzens Sept. 17, 2017

Sept. 17, 2017

tldr; 10.08.2017 18:30 (open end) AfRA (different location!) Hi, the Berlin Usergroup Meeting in August will taken place on 10.08.2017 in the rooms of the Department Of Redundancy Department (AfRA). Abteilung für Redundanz Abteilung Margaretenstraße 30 10317 Berlin https://afra-berlin.de/ best, lynxis Ps. If you want to flash your laptop, send me a notice in advance. Certain things might need to prepared for your device. -- Alexander Couzens mail: lynxis(a)fe80.eu jabber: lynxis(a)fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604

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