Hello Martin,
> -------- Original Message --------
> Subject: Re: [coreboot] Coreboot+SeaBios Boot speed: ~12sec till Grub Boot Screen
> Local Time: 25 September 2017 3:53 AM
> From: gaumless(a)gmail.com
>
> Is serial console enabled? If so, disabling that will speed things up
> immensely.
To which position in the menuconfig tree are you referencing?
Have disabled all entries under "Console" in menuconfig but still get the boot delay.
I've thecoreboot .config in case that this is helpfull, see attached file.
> Can you post a miniconfig? Run "make savedefconfig" and post the file
> "defconfig"?
Sure, at your service:
$ make savedefconfig && cat defconfig
CONFIG_USE_OPTION_TABLE=y
CONFIG_COLLECT_TIMESTAMPS=y
CONFIG_VENDOR_LENOVO=y
CONFIG_CBFS_SIZE=0x400000
CONFIG_VGA_BIOS=y
CONFIG_VGA_BIOS_FILE="~/my-coreboot/MyROMs/original/vga.rom"
# CONFIG_POST_IO is not set
# CONFIG_POST_DEVICE is not set
CONFIG_BOARD_LENOVO_X230=y
CONFIG_DRIVERS_PS2_KEYBOARD=y
# CONFIG_CONSOLE_CBMEM is not set
CONFIG_CPU_MICROCODE_CBFS_NONE=y
CONFIG_SEABIOS_PS2_TIMEOUT=10
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_LPC_TPM=y
# CONFIG_SQUELCH_EARLY_SMP is not set
CONFIG_SEABIOS_MASTER=y
CONFIG_SEABIOS_THREAD_OPTIONROMS=y
CONFIG_COREINFO_SECONDARY_PAYLOAD=y
> Can you post timestamp information so we can see what"s using all the time?
Unfortunately not as I haven't been able to create a 2nd payload in order to read the timstamps from coreinfo.
Coreinfo is shown in the boot menu when hitting ESC, but after launching, the screen goes blank and nothing happens.
Maybe this is related to the fact, that I flashed only 4 MB of the Chip(s) and as such some part of the code is missing (whoch would be in the 8 MB part of the rom-file)?
[799]
Hello,
I tried to flash the 8 MB Chip on my X230, but it didn't worked out.
> Me: what do I need to do to flash the 2nd (8MB) chip.
> If the 1st chip contains the last 4MB of the file, I assume the correct command could be:
> dd of=chip8mb.rom bs=1M if=build/coreboot.rom count=8
>
> Is this correct? If this is right I'll add this to the wiki as soon as I have write permissions.
I've dd'ed the first 8MB of the coreboot.rom file with the above command and flashed it on the 8MB chip, but when booting my machine only illuminated the on-off-button for a second before it dies.
When reflashing the 8MB chip with the stock image which I grabbed before will bring my laptop back to life. As such it seems that there must be another was two flash both chips and to strip the coreboot.rom image.
Any ideas what went wrong?
As all howto's I've found so far, which cover the flashing of only the upper 4 MB Chip, the question is also, if someone has already flashed both chips and what (s)he did to make it work.
[799]
(Please reply only to the list, rather than Cc:ing me. Your mailer
may have a list-reply plugin to automate that. Thanks a lot!)
One7two99 via coreboot wrote:
> One additional general question regarding the flashing on X230s.
As you document your experience, please investigate what is specific
for the X230, and what is not - and be clear in what you write.
(Most things are in no way X230-specific.)
> Most howtos include that it is sufficient to flash only the upper
> 4MB BIOS Chip and leave the 2nd 8 MB BIOS Chip untouched.
I would consider that bad advice, if coreboot.rom is 12 MB.
There are not "two BIOSes" just because there are two memory chips.
The two memory chips are mapped after each other and function as one
unit. The CPU sees them as one, and so should you.
> After creating my 12 MB Coreboot.rom I split it and use only 4MB
> for flashing.
So you flash only the last third of the CBFS, and ignore the beginning.
I think it is just luck that your system boots at all. If you used a
larger payload such as a kernel then your method will likely cut the
payload in half and end up writing incomplete junk to your flash.
You can compare it to deleting the first two thirds of a .zip file.
> As far as I understand the 2nd Chip include the Intel Mangement
> Engine (ME), shouldn't this chip also touched and (at least party)
> ME'cleaned?
There is no relation between coreboot and the ME. The main CPU and
the ME CPU are not very close to each other, and their respective
firmware have little to do with each other. They interface through
HECI. Neither will care what you do to the other.
> Or is the 2nd BIOS not used at all after flashing Coreboot to the
> top 4MB chip?
Please study the hardware you are working with. What software you put
in either memory is not relevant for how the hardware works, for how
the two memories are mapped to physical CPU addresses.
//Peter
Hello,
I'd like to upgrade my CPUs (I have 2 x Opteron 6276) and I'm now
sure which one should I choose? Will I see a difference? Does the
upgrade worth?
Yours,
BogDan.
,
Hi guys,
First off, I'm still looking for testers for my early CBMEM work on
440BX mainboards. [1]
I've actually added asus/p2b-ds to the mix [2] but because of a
previously documented issue I'm not able to get a complete
board_status report, so again more testing help is appreciated.
Meanwhile, I moved to adding ACPI support to these boards and pushed a
series of 3 patches for review, together they form a complete ACPI
DSDT coding for my asus/p2b-ls board, built from a remix of ACPI stuff
found in asus/p2b and elsewhere in tree and the DSDT extracted from
factory bios. I'll need this in place before I can make soft-off and
suspend/resume work.
https://review.coreboot.org/c/21670/https://review.coreboot.org/c/21671/https://review.coreboot.org/c/21672/
I did check the contents against the DSDT table extracted from OEM
BIOS and have adapted these to reuse as much in-tree ACPI stuff as
possible, and they are written with reuse and sharing in mind. They
haven't been boot tested yet, but I wanted to throw this out here as
this is my first real ACPI work and there must be something wrong in
there, so please whip me softly if you have to. :) All I have achieved
at this stage is that the DSDT compiles without errors, but there are
still warnings so I can use some help clearing them as well.
Thanks again
Keith
[1] https://mail.coreboot.org/pipermail/coreboot/2017-September/085116.html
[2] https://review.coreboot.org/c/21646/
ps. There was only ACPI 1.0 when these boards were released.
pps. The patch broke asus/p2b. But "make what-jenkins-does" didn't
catch it. I'd expect it to literally do exactly as what Jenkins does
and catch the breakage. Or do I need to go back to abuild?
Hello,
Booting to my Grub Selection screen takes ~12sec on my X230, loosing lots of second from pressing the Power Button to the "Hit Escape Key" message from SeaBios.
Are there any options to accelerate this and what are you Booting times to the Grub OS selection screen?
[799]
Hello Matt,
> -------- Original Message --------
> Subject: Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work
> Local Time: September 23, 2017 10:59 PM
> From: matt.devillier(a)gmail.com
> coreboot + Tianocore/CorebootPayloadPkg works perfectly well to run Windows on everything from SandyBridge to Skylake
I'll stick to coreboot + SeaBios as I can boot linux/windows which perfectly fine and the installation seems to be easier and I can't see any reason why switching from (Sea)BIOS to UEFI.
One additional general question regarding the flashing on X230s.
Most howtos include that it is sufficient to flash only the upper 4MB BIOS Chip and leave the 2nd 8 MB BIOS Chip untouched.
After creating my 12 MB Coreboot.rom I split it and use only 4MB for flashing.
See also the Coreboot Wiki at https://www.coreboot.org/Board:lenovo/x230#Hardware_Flashring
"(...) Write the flash. Since you have to write only top 4M, first split out those 4M:
dd of=top.rom bs=1M if=build/coreboot.rom skip=8
Use flashrom to flash top.rom (...)"
As far as I understand the 2nd Chip include the Intel Mangement Engine (ME), shouldn't this chip also touched and (at least party) ME'cleaned?
Or is the 2nd BIOS not used at all after flashing Coreboot to the top 4MB chip?
[799]
One7two99 via coreboot wrote:
> add which location should I place my extracted vga blob, so that it
> can be found during the Coreboot Build process
Paths entered during configuration reference the source root directory.
> What other settings are suggested to get proper vga initialization
> to be able to boot windows:
VGA init can be proper without Windows being able to boot.
Windows will require SeaBIOS. (In theory perhaps TianoCore+CorebootPkg
works too, but I wouldn't bet on that.)
Windows will also require the VGA BIOS.
If you have SeaBIOS then I recommend letting SeaBIOS run the VGA BIOS.
> 1) Devices > Add a Video Bios Table (VBT) binary to CBFS (yes or no?)
No - the VGA BIOS creates a VBT. Is that not documented sufficiently?
> 2) Devices > Graphic initialization (currently: use native graphics init)
> (should I switch this to: Run VGA Option Roms?)
No - disable graphics init in coreboot and let SeaBIOS run your VGA BIOS.
As you can find in SeaBIOS docs, that requires the VGA BIOS to be
stored with the correct name in CBFS, which coreboot may or may not
do automatically. (It should, but bugs.)
If you store the VGA BIOS with a name in CBFS containing a special
subdirectory (I think vgaroms/) then the rest of the filename doesn't
matter.
You can of course always add the VGA BIOS file to CBFS manually, if you
want it to have a particular name in CBFS. It is not neccessary that the
coreboot build system adds it.
//Peter
Hello Peter,
-------- Original Message --------
> Subject: Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work
> Local Time: September 23, 2017 10:01 PM
>
>>> VGA init can be proper without Windows being able to boot.
I know, this was the setup I had before, but having a PC which is unable to run windows is sometimes a no-go :-)
> Windows will require SeaBIOS. (In theory perhaps TianoCore+CorebootPkg
> works too, but I wouldn"t bet on that.)
> Windows will also require the VGA BIOS.
I am currently only using SeaBIOS and the vga.rom and SUCCESS, I am able to boot into my Qubes 3.2 installation AND (!) my Windows 10 Enteprise, whis is great as this was broken after switching to Coreboot.
> If you have SeaBIOS then I recommend letting SeaBIOS run the VGA BIOS.
I don't really understand what this means, when I document my setup/coreboot configuration, I am happy for any suggestion how to improve it.
>> 1) Devices > Add a Video Bios Table (VBT) binary to CBFS (yes or no?)
> No - the VGA BIOS creates a VBT. Is that not documented sufficiently?
Maybe I don't get it, but in menuconfig I have disabled this option.
>> 2) Devices > Graphic initialization (currently: use native graphics init)
>> (should I switch this to: Run VGA Option Roms?)
> No - disable graphics init in coreboot and let SeaBIOS run your VGA BIOS.
Ok, I'll try that and will disable graphic initalization in coreboot.
As mentioned with the current setting I can boot into Linux and Windows 10.
Is there any benefit disabling native graphics init in coreboot?
> As you can find in SeaBIOS docs, that requires the VGA BIOS to be
> stored with the correct name in CBFS, which coreboot may or may not
> do automatically. (It should, but bugs.)
> If you store the VGA BIOS with a name in CBFS containing a special
> subdirectory (I think vgaroms/) then the rest of the filename doesn"t
> matter.
I think some documentation here would be great, as I am currently a bit lost.
What I got from your reply, it is possible that coreboot will use the vga.rom but it can also be handled by SeaBIOS, do I need to modify any additional things there (in SeaBIOS)?
> You can of course always add the VGA BIOS file to CBFS manually, if you
> want it to have a particular name in CBFS. It is not neccessary that the
> coreboot build system adds it.
I need to do some more reading about CBFS ... currently I am just happy that I got coreboot working for dualbooting Qubes and Win 10.
I'll do some more testing to see if everything works (external display / standby/resume / LTE/etc)
What has been improved already:
Booting up Qubes OS doesn't can also be done with graphical but, before including vga.rom into coreboot I had to edit grub.
In order to enter my passphrase to unlock my LUKS encrypted drive in Qubes I had to change grub to boot in "console mode" instead of relying on graphics:
sudo nano /etc/default/grub
GRUB_TERMINAL_OUTPUT="vga_text"
Remove rhgb quiet from GRUB_CMDLINE_LINUX
I've rolled back these changes and now I get the graphical splash screen during boot. Nice:-)
[799]
Hello Matt,
> -------- Original Message --------
> From: matt.devillier(a)gmail.com
> ME >> Question: Can I use this file for my X230?
>
> absolutely not. You need to use one which is for your GPU/platform, and configured to match the outputs on your x230. Which is why it's best to extract from the vendor firmware using UEFITool
Thank your, I (think at least) I have succesfully extracted the information from my BIOS Rom File.
This is was I did (running Ubuntu 16.04.3 LTS from USB):
- Install QMAKE as this is needed to build UEFIToool
sudo apt-get install qt5-default qt5-make
- Get UEFITool from GIT
git clone http://github.com/LongSoft/UEFITool.git
- Compile UEFITool
cd UEFITool/ && qmake && make
- Start: ./UEFITool
- File > Open BIOS Image File
Open the ROM-file from the 4MB BIOS-Chip
will generate the following (error?) messages - which I ignored:
"parseVolume: unknown file system FFF12B8D-7696-4C8B-A985-2747075B4F50
parseBios: volume size stored in header 61000h (397312) differs from calculated
using block map 40000h (262144)
parseVolume: unknown file system 00504624-8A59-4EEB-BD0F-6B36E96128E0
parseBios: volume size stored in header 2F000h (192512) differs from calculated using block map 30000h (196608)
parseFile: invalid data checksum"
- Hit CTRL+F (Search...), 3rd Tab (Text)
- Search for: VGA Compatible BIOS
(Uncheck Unicode)
- Will show the following message:
ASCII text "VGA Compatible BIOS" found in Raw section at offset 22h
- Double click on the line in the message windows which bring you to the raw section
- Right Click on "Raw section" and choose "Extract Body"
- Save file as vga.rom
If the above procedere is correct I would like to add it to the Coreboot Wiki as currently the documentation is present on other pages, but as newbie (like me) has to look at various pages - also how and what packages I need to install to compile UEFITool etc.
I guess the next step is to link to this vga BLOB when running make menuconfig in coreboot under DEVICES > ADD A VGA BIOS IMAGE.
QUESTION:
add which location should I place my extracted vga blob, so that it can be found during the Coreboot Build process, I am currently referencing the whole path, I tried to place into
3rdparty/blobs/mainboard/lenovo/x230 where I have also placed the other extracted blobs from my 8MB BIOS Chip (descriptor.bin gbe.bin me.bin) but it didn't work.
What other settings are suggested to get proper vga initialization to be able to boot windows:
1) Devices > Add a Video Bios Table (VBT) binary to CBFS (yes or no?)
2) Devices > Graphic initialization (currently: use native graphics init)
(should I switch this to: Run VGA Option Roms?)
[799]
