September 2017 - coreboot - mail.coreboot.org

Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work
by Nico Huber Sept. 29, 2017

Sept. 29, 2017

Hi 799, On 28.09.2017 00:38, One7two99 via coreboot wrote: > Hello, > > after reading the dd howtos it seems that the 12 MB coreboot.rom file can be split like this: > > # Split first 8MB of coreboot.rom (bottom-chip) > dd if=coreboot.rom of=x230-coreboot-8mb.rom bs=1024 count=$[1024*8] skip=0 That gives the same as `bs=1M count=8` it's just a weirder way to tell `dd`. > > # Split last 4MB of coreboot.rom (top-chip) > dd if=coreboot.rom of=x230-coreboot-4mb.rom bs=1024 count=$[1024*4] skip=$[1024*8] > > at least this is what I did - while it was good enough that my X230 is booting up I still can't boot the secondary payloads (I have choosen nvramcui and coreinfo). I suspect some misconfiguration or that something confuses the libpay- load VGA driver (which these two secondary payload rely on). > As mentioned I am writing a howto whch is target at a newbie user, who has basic linux skills and has just about coreboot and wants to try it out. > > I've run the following steps (I've already written the howto which covers more information about each step, but unfortunately I can't access the wiki as an editor, asked for it already). > > If you thing I've missed out important steps, I am happy to hear your comments. Don't think you missed anything and your ways to split the image seem fine. But you might do too much already. Especially flashing anything but the BIOS region when you want to track down coreboot issues makes things harder to reason about. --snip-- > 12) Configure Coreboot (make nconfig) > choose parameters/features and add the 4 binary blobs (step 8 and 11) Please attach your .config file. Nobody can say anything for sure with- out knowing what you chose. Nico

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Re: [coreboot] Intel Leaf Hill Coreboot Trouble
by Zoran Stojsavljevic Sept. 28, 2017

Sept. 28, 2017

What a mess, Good Lord! I am not entirely sure what you are trying to do, all of you trying to use IFWI, then Coreboot, and them U-boot. It seems to me way overkill, used for some academical purposes (as I managed to run Virtual Box VMM on Fedora VM, on the top of Virtual Box VMM on Fedora VM, on the top of VMWare Workstation, on WIN10 64). Three nested VMMs inside each other? What for (the purpose was to learn setup, and nothing more)?! Here is what I found on the net: https://github.com/al177/edbian/wiki/edison_boot_n_dfu Important points: IFWI is the Intel FirmWare Interface, a binary blob loaded from the eMMC boot partition that executes a secondary loader from the main eMMC. IFWI blobs for the APL-I are provided by Intel and are specific for different flavors of the MID silicon. In this lieu, what is written here, the following is my proposal (as stated in the article): Normal IFWI eMMC boot process 1. On-chip boot rom inits eMMC and loads IFWI from the MMC boot partitions 2. IFWI looks for OSIP header at top of eMMC (MBR boot block) 3. The header directs IFWI to the start, size, load address, and entry of U-Boot in eMMC 4. (need clarification) If u-boot is not found, try the alt u-boot image at 5MB into the eMMC 5. U-Boot is loaded into RAM and executed For you all, OSIP stands for OS Image Profile, and it is nothing more and less than INTEL name for very known old fashion MBR, considering DATA structure (INTEL always tend to complicate, in order to intimidate customers and force them to obey to some phony philosophy, thus making customers very dependent for the stuff which are normal and relative simplistic). # This is what a full OSIP header contains # Its size is 512 bytes # Offset Size (bytes) Description # 0x000 4 OSIP Signature "$OS$" # 0x004 1 Reserved # 0x005 1 Header minor revision # 0x006 1 Header major revision # 0x007 1 Header checksum # 0x008 1 Number of pointers # 0x009 1 Number of images # 0x00a 2 Header size # 0x00c 20 Reserved # 0x020 24 1st bootable image descriptor (OSII) # 0x038 24 2nd bootable image descriptor (OSII) # ... ... ... # 0x170 24 15th bootable image descriptor (OSII) # 0x188 48 Not used # 0x1B8 4 Disk signature # 0x1BC 2 Null (0x0000) # 0x1BE 16 1st primary partition descriptor # 0x1CE 16 2nd primary partition descriptor # 0x1DE 16 3rd primary partition descriptor # 0x1EE 16 4th primary partition descriptor # 0x1FE 1 0x55 # 0x1FF 1 0xaa Ron (Minnich), you are added to this email, since I finally start understanding from where you are coming from (I needed two years, really to clear some obstacles)! ;-) For the rest, someone can, while using APL-I with Coreboot, and U-Boot as payload, simply skip the Coreboot phase and make his/her life much easier! Said that, you can all conclude what is actually IFWI, and that the FSP blob is actually redundant, Coreboot is seconday bootloader in this case. Either use Coreboot, either U-boot, you do not need both! IMHO. Best Regards, Zoran Stojsavljevic _______ On Thu, Sep 28, 2017 at 6:13 PM, Cameron Craig <Cameron.Craig(a)exterity.com> wrote: > Hi Zoran, > > > > Thanks for the advice, I had a glimpse at your config and noticed a few > differences: > > -You target CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 rather than > CONFIG_BOARD_INTEL_LEAFHILL. Insignificant I think. > > -You include a TXE blob, I do not. This may be quite significant! I have > tried including a TXE blob, only to be presented with an error > (txe_error.txt) > > > > Once I get the FIT tool going I may be able to enable the Intel ME region > and fix that error. > > > > Cheers, > > Cameron > > > > *From:* Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] > *Sent:* 27 September 2017 20:11 > *To:* Cameron Craig; Martin Roth > *Cc:* coreboot(a)coreboot.org > *Subject:* Re: [coreboot] Intel Leaf Hill Coreboot Trouble > > > > Since I really want to help, and I do not have any time left for Coreboot > (since I am fully/200% devoted to Fedora/RHEL/kernel.org and YOCTO), > three kludge thinking from me (APL-I supposed to be my > get_to_the_rich_pals_vehicle in Y2015, but mortally crashed somewhere in > the process - For Good)!: > > > > [1] I did assemble APL-I Coreboot based upon www.intel.com/fsp (please, > choose APL-I FSP release) APL-I FSP blobs. I did at the very end very clean > compilation, but there are two catches 22 to what I did (significant > credits/courtesy to Martin Roth, Martin really pulled me up and survived me > in this weird FSP 2.0 crazy business of INTEL's)... ;-) > > [A] The Coreboot release I played with is: [user@localhost > coreboot]$ git describe ==>> 4.5-1029-g97535558f1 (NOT 4.6); > > [B] Never tested it on real HW, I do NOT have APL-I HW, Leaf Hill, > Deaf Hill or you name it... But I did attach my .config/CONFIG! > > [2] As my .config (attached CONFIG) suggests, please, try with some other > payload (SeaBIOS as for example, which I used); > > [3] You need to compare my .config with yours (I have neither any time, > neither any desire to do this). > > > > Good Luck, very much/totally INTEL 2.0 FSP (doomed to the bones) dependent > enthusiast (I can still advise out of desperation, if you investigate and > continue posting results here). > > > > P.S. Martin (Roth), once again, thank you for unselfish help (I do > remember)! :-) > > > > Zoran > > _______ > > > > On Wed, Sep 27, 2017 at 2:01 PM, Cameron Craig <Cameron.Craig(a)exterity.com> > wrote: > > Hi All, > > > > I’m currently trying to get coreboot working on an Intel Leaf Hill > development board, we are using U-Boot as a payload. > > > > I have managed to create a bootable image using an out of date copy of > coreboot and U-Boot, provided by Intel under NDA. > > The stitching process used to generate the image is a little ugly: a set > of Windows tools are provided (or pointed at) by Intel to stitch the > various blobs together to create an 8MB image. > > We would like to move away from this process. Using the cbfs tool it looks > like we are getting a legacy image composed entirely of a single CBFS. > > > > However, as far as I understand, the latest coreboot release (v4.6) should > be capable of producing a 16MB working image without the use of external > tools. > > This is of course dependent on the provision of the correct binary blobs > such as the FSP, flash descriptor and IFWI. > > I have attached the descriptor of the IFWI image being used. > > > > This is the process I have followed in order to generate a coreboot image: > > 1. Clone coreboot (v4.6) > > 2. Obtain Apollo Lake FSP from Intel (https://github.com/IntelFSP/ > FSP) > > 3. Split FSP into its constituent parts (https://raw. > githubusercontent.com/tianocore/edk2/master/IntelFsp2Pkg/Tools/ > SplitFspBin.py) > > 4. Extract Flash Descriptor from an existing Leaf Hill UEFI image > (./ifdtool --extract leaf_hill_ref_board_uefi.bin) > > 5. Obtain IFWI image from Intel (Apollo Lake Technical Library) > > 6. make menuconfig (config file is attached) > > a. Mainboard > > i. Mainboard > vendor (Intel) > > ii. Mainboard > model (Leafhill) > > iii. [*] > Use IFWI Stitching > > iv. (IFWI) > section in .fmd file to place IFWI blob > > v. (IFWI_SPI.bin) > Path to image coming from FIT Tool > > vi. (descriptor.bin) > path to descriptor.bin > > vii. (Fsp_M.fd) > path to FSP-M.Fv blob > > viii. (Fsp_S.fd) > path to FSP-S.Fv > > b. Payload > > i. Add > a payload (U-Boot (Experimental)) > > ii. U-Boot > version (v2016.1) > > iii. (coreboot-x86_defconfig) > U-Boot config file > > c. The rest are at Leaf Hill defaults. > > 7. make > > 8. Flash image to Leaf Hill SPI flash > > > > As far as I can tell, this process should produce a working image. > > However it does not. My most recent attempt has managed to blink the > PWR_OK LED, suggesting the PMIC/PMC is working, but no serial messages. > > Other than that, I currently have no working theories as to what the root > cause is L > > > > Is there anything obviously wrong with this process? > > Are there any bugs that I should be aware of relating to coreboot on an > Apollo Lake platform? > > I haven’t found a lot of documentation online to describe the exact > configuration and blob usage, are there any relevant sources of > documentation you could point me towards? > > > > Any help to answer the above, or any other advice would be greatly > appreciated. > > > > Cheers, > > Cameron > > > > *Cameron Craig* | Graduate Software Engineer | *Exterity Limited* > tel: +44 1383 828 250 <+44%201383%20828250> | fax: > e: Cameron.Craig(a)exterity.com | w: www.exterity.com > > <http://www.exterity.com> > > [image: ISO9001] <http://www.exterity.com/iso9001> > > [image: LinkedIn] <http://www.linkedin.com/company/exterity> > > [image: Twitter] <http://www.twitter.com/exterity> > > [image: YouTube] <http://www.youtube.com/user/exterityiptv> > > > Exterity is a leading provider of IP Video and Digital Signage solutions > that helps organizations to harness the power of video to communicate, > educate and entertain. Our end-to-end solutions enable you to take TV and > video content directly from any source and manage its delivery, live or on > demand, to any connected device via your existing network. For more > information or to schedule a product demonstration, contact Exterity on +44(0)1383 > 828 250 <+44%201383%20828250> or visit www.exterity.com > > Legal Notice > Unless expressly stated otherwise, this message is confidential and may be > privileged. It is intended for the addressee(s) only. Access to this e-mail > by anyone else is unauthorized. If you are not an addressee, any disclosure > or copying of the contents of this e-mail or any action taken (or not > taken) in reliance on it is unauthorized and may be unlawful. If you are > not an addressee, please inform the sender immediately. > > Exterity Limited is registered in Scotland under No. 225313 with its > registered office at St Davids House, St Davids Drive, Dalgety Bay, KY11 9NB > > > > > Cameron Craig | Graduate Software Engineer | Exterity Limited > tel: +44 1383 828 250 <+44%201383%20828250> | fax: > e: Cameron.Craig(a)exterity.com | w: www.exterity.com > > > > > ______________________________________________________________________ > This email has been scanned by the Symantec Email Security.cloud service. > For more information please visit http://www.symanteccloud.com > ______________________________________________________________________ > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot > > > > > ______________________________________________________________________ > This email has been scanned by the Symantec Email Security.cloud service. > For more information please visit http://www.symanteccloud.com > ______________________________________________________________________ > > > ______________________________________________________________________ > This email has been scanned by the Symantec Email Security.cloud service. > For more information please visit http://www.symanteccloud.com > ______________________________________________________________________ >

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Re: [coreboot] Intel Leaf Hill Coreboot Trouble
by Cameron Craig Sept. 28, 2017

Sept. 28, 2017

Hi Zoran, Thanks for the advice, I had a glimpse at your config and noticed a few differences: -You target CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 rather than CONFIG_BOARD_INTEL_LEAFHILL. Insignificant I think. -You include a TXE blob, I do not. This may be quite significant! I have tried including a TXE blob, only to be presented with an error (txe_error.txt) Once I get the FIT tool going I may be able to enable the Intel ME region and fix that error. Cheers, Cameron From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] Sent: 27 September 2017 20:11 To: Cameron Craig; Martin Roth Cc: coreboot(a)coreboot.org Subject: Re: [coreboot] Intel Leaf Hill Coreboot Trouble Since I really want to help, and I do not have any time left for Coreboot (since I am fully/200% devoted to Fedora/RHEL/kernel.org<http://kernel.org> and YOCTO), three kludge thinking from me (APL-I supposed to be my get_to_the_rich_pals_vehicle in Y2015, but mortally crashed somewhere in the process - For Good)!: [1] I did assemble APL-I Coreboot based upon www.intel.com/fsp<http://www.intel.com/fsp> (please, choose APL-I FSP release) APL-I FSP blobs. I did at the very end very clean compilation, but there are two catches 22 to what I did (significant credits/courtesy to Martin Roth, Martin really pulled me up and survived me in this weird FSP 2.0 crazy business of INTEL's)... ;-) [A] The Coreboot release I played with is: [user@localhost coreboot]$ git describe ==>> 4.5-1029-g97535558f1 (NOT 4.6); [B] Never tested it on real HW, I do NOT have APL-I HW, Leaf Hill, Deaf Hill or you name it... But I did attach my .config/CONFIG! [2] As my .config (attached CONFIG) suggests, please, try with some other payload (SeaBIOS as for example, which I used); [3] You need to compare my .config with yours (I have neither any time, neither any desire to do this). Good Luck, very much/totally INTEL 2.0 FSP (doomed to the bones) dependent enthusiast (I can still advise out of desperation, if you investigate and continue posting results here). P.S. Martin (Roth), once again, thank you for unselfish help (I do remember)! :-) Zoran _______ On Wed, Sep 27, 2017 at 2:01 PM, Cameron Craig <Cameron.Craig(a)exterity.com<mailto:Cameron.Craig@exterity.com>> wrote: Hi All, I’m currently trying to get coreboot working on an Intel Leaf Hill development board, we are using U-Boot as a payload. I have managed to create a bootable image using an out of date copy of coreboot and U-Boot, provided by Intel under NDA. The stitching process used to generate the image is a little ugly: a set of Windows tools are provided (or pointed at) by Intel to stitch the various blobs together to create an 8MB image. We would like to move away from this process. Using the cbfs tool it looks like we are getting a legacy image composed entirely of a single CBFS. However, as far as I understand, the latest coreboot release (v4.6) should be capable of producing a 16MB working image without the use of external tools. This is of course dependent on the provision of the correct binary blobs such as the FSP, flash descriptor and IFWI. I have attached the descriptor of the IFWI image being used. This is the process I have followed in order to generate a coreboot image: 1. Clone coreboot (v4.6) 2. Obtain Apollo Lake FSP from Intel (https://github.com/IntelFSP/FSP) 3. Split FSP into its constituent parts (https://raw.githubusercontent.com/tianocore/edk2/master/IntelFsp2Pkg/Tools/…) 4. Extract Flash Descriptor from an existing Leaf Hill UEFI image (./ifdtool --extract leaf_hill_ref_board_uefi.bin) 5. Obtain IFWI image from Intel (Apollo Lake Technical Library) 6. make menuconfig (config file is attached) a. Mainboard i. Mainboard vendor (Intel) ii. Mainboard model (Leafhill) iii. [*] Use IFWI Stitching iv. (IFWI) section in .fmd file to place IFWI blob v. (IFWI_SPI.bin) Path to image coming from FIT Tool vi. (descriptor.bin) path to descriptor.bin vii. (Fsp_M.fd) path to FSP-M.Fv blob viii. (Fsp_S.fd) path to FSP-S.Fv b. Payload i. Add a payload (U-Boot (Experimental)) ii. U-Boot version (v2016.1) iii. (coreboot-x86_defconfig) U-Boot config file c. The rest are at Leaf Hill defaults. 7. make 8. Flash image to Leaf Hill SPI flash As far as I can tell, this process should produce a working image. However it does not. My most recent attempt has managed to blink the PWR_OK LED, suggesting the PMIC/PMC is working, but no serial messages. Other than that, I currently have no working theories as to what the root cause is ☹ Is there anything obviously wrong with this process? Are there any bugs that I should be aware of relating to coreboot on an Apollo Lake platform? I haven’t found a lot of documentation online to describe the exact configuration and blob usage, are there any relevant sources of documentation you could point me towards? Any help to answer the above, or any other advice would be greatly appreciated. Cheers, Cameron Cameron Craig | Graduate Software Engineer | Exterity Limited tel: +44 1383 828 250<tel:+44%201383%20828250> | fax: e: Cameron.Craig(a)exterity.com<mailto:Cameron.Craig@exterity.com> | w: www.exterity.com<http://www.exterity.com> [cid:image001.png@01D3387B.23489AD0]<http://www.exterity.com> [ISO9001]<http://www.exterity.com/iso9001> [LinkedIn]<http://www.linkedin.com/company/exterity> [Twitter]<http://www.twitter.com/exterity> [YouTube]<http://www.youtube.com/user/exterityiptv> Exterity is a leading provider of IP Video and Digital Signage solutions that helps organizations to harness the power of video to communicate, educate and entertain. Our end-to-end solutions enable you to take TV and video content directly from any source and manage its delivery, live or on demand, to any connected device via your existing network. For more information or to schedule a product demonstration, contact Exterity on +44(0)1383 828 250<tel:+44%201383%20828250> or visit www.exterity.com<http://www.exterity.com> Legal Notice Unless expressly stated otherwise, this message is confidential and may be privileged. It is intended for the addressee(s) only. Access to this e-mail by anyone else is unauthorized. If you are not an addressee, any disclosure or copying of the contents of this e-mail or any action taken (or not taken) in reliance on it is unauthorized and may be unlawful. If you are not an addressee, please inform the sender immediately. Exterity Limited is registered in Scotland under No. 225313 with its registered office at St Davids House, St Davids Drive, Dalgety Bay, KY11 9NB Cameron Craig | Graduate Software Engineer | Exterity Limited tel: +44 1383 828 250 | fax: e: Cameron.Craig(a)exterity.com | w: www.exterity.com ______________________________________________________________________ This email has been scanned by the Symantec Email Security.cloud service. For more information please visit http://www.symanteccloud.com ______________________________________________________________________ -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://mail.coreboot.org/mailman/listinfo/coreboot ______________________________________________________________________ This email has been scanned by the Symantec Email Security.cloud service. For more information please visit http://www.symanteccloud.com ______________________________________________________________________ ______________________________________________________________________ This email has been scanned by the Symantec Email Security.cloud service. For more information please visit http://www.symanteccloud.com ______________________________________________________________________

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Re: [coreboot] Intel Leaf Hill Coreboot Trouble
by Cameron Craig Sept. 28, 2017

Sept. 28, 2017

Hi Paul, Great to hear I’m not the only one in this situation ☺ I’ve just been using the IWFI file from Intel with no modifications, so I’ll look out the FIT tool and give that a go. Thanks, Cameron Cameron Craig | Graduate Software Engineer | Exterity Limited tel: +44 1383 828 250 | fax: e: Cameron.Craig(a)exterity.com | w: www.exterity.com From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Paul Penz Sent: 28 September 2017 15:35 To: coreboot(a)coreboot.org Subject: Re: [coreboot] Intel Leaf Hill Coreboot Trouble Hi Cameron, I had the same problem. Had you modified the intel IFWI file ? If not, I had done this additional: Download 522538_apl txe hf 3.0.11.1131 (th2 & rs1).zip from intel Start fit.exe Load the IFWI file Change at Platform Protection/Platform Integrity OOEM Public Key Hash => 00..00 Change at Platform Protection/Boot Guard Configuration/ Boot profile 2 => 0 Save Now I get output on the console and postcodes, but during FSP_M a long pause of ca. 45s exists and it hangs later during FSP_P initialization. Good luck Paul Paul Penz Dipl.-Ing. (FH) Senior Hardware Engineer ELTEC Elektronik AG, Mainz _________________________ Fon +49 6131 918 335 Fax +49 6131 918 195 Email ppenz(a)eltec.de<mailto:ppenz@eltec.de> Web www.eltec.de<http://www.eltec.de/> ________________________________ ********************************************************* ELTEC Elektronik AG Galileo-Galilei-Straße 11 D-55129 Mainz Vorstand: Peter Albert Aufsichtsratsvorsitzender: Andreas Kochhäuser Registergericht: Amtsgericht Mainz Registernummer: HRB 7038 Ust-ID: DE 149 049 790 ********************************************************* Wichtiger Hinweis: Diese E-Mail kann Betriebs- oder Geschäftsgeheimnisse oder sonstige vertrauliche Informationen enthalten. Sollten Sie diese E-Mail irrtümlich erhalten haben, ist Ihnen eine Kenntnisnahme des Inhalts, eine Vervielfältigung oder Weitergabe der E-Mail ausdrücklich untersagt. Bitte benachrichtigen Sie uns und vernichten Sie die empfangene E-Mail. Evtl. Anhänge dieser Nachricht wurden auf Viren überprüft! Jede Form von Vervielfältigung, Abänderung, Verbreitung oder Veröffentlichung dieser E-Mail Nachricht ist untersagt! Das Verwenden von Informationen aus dieser Nachricht für irgendwelche Zwecke ist strengstens untersagt. Es gelten unsere Allgemeinen Geschäftsbedingungen, zu finden unter www.eltec.de<http://www.eltec.de>. ______________________________________________________________________ This email has been scanned by the Symantec Email Security.cloud service. For more information please visit http://www.symanteccloud.com ______________________________________________________________________ ______________________________________________________________________ This email has been scanned by the Symantec Email Security.cloud service. For more information please visit http://www.symanteccloud.com ______________________________________________________________________

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Re: [coreboot] Intel Leaf Hill Coreboot Trouble
by Paul Penz Sept. 28, 2017

Sept. 28, 2017

Hi Cameron, I had the same problem. Had you modified the intel IFWI file ? If not, I had done this additional: Download 522538_apl txe hf 3.0.11.1131 (th2 & rs1).zip from intel Start fit.exe Load the IFWI file Change at Platform Protection/Platform Integrity OOEM Public Key Hash => 00..00 Change at Platform Protection/Boot Guard Configuration/ Boot profile 2 => 0 Save Now I get output on the console and postcodes, but during FSP_M a long pause of ca. 45s exists and it hangs later during FSP_P initialization. Good luck Paul Paul Penz Dipl.-Ing. (FH) Senior Hardware Engineer ELTEC Elektronik AG, Mainz _________________________ Fon +49 6131 918 335 Fax +49 6131 918 195 Email ppenz(a)eltec.de<mailto:ppenz@eltec.de> Web www.eltec.de<http://www.eltec.de/> ________________________________ ********************************************************* ELTEC Elektronik AG Galileo-Galilei-Straße 11 D-55129 Mainz Vorstand: Peter Albert Aufsichtsratsvorsitzender: Andreas Kochhäuser Registergericht: Amtsgericht Mainz Registernummer: HRB 7038 Ust-ID: DE 149 049 790 ********************************************************* Wichtiger Hinweis: Diese E-Mail kann Betriebs- oder Geschäftsgeheimnisse oder sonstige vertrauliche Informationen enthalten. Sollten Sie diese E-Mail irrtümlich erhalten haben, ist Ihnen eine Kenntnisnahme des Inhalts, eine Vervielfältigung oder Weitergabe der E-Mail ausdrücklich untersagt. Bitte benachrichtigen Sie uns und vernichten Sie die empfangene E-Mail. Evtl. Anhänge dieser Nachricht wurden auf Viren überprüft! Jede Form von Vervielfältigung, Abänderung, Verbreitung oder Veröffentlichung dieser E-Mail Nachricht ist untersagt! Das Verwenden von Informationen aus dieser Nachricht für irgendwelche Zwecke ist strengstens untersagt. Es gelten unsere Allgemeinen Geschäftsbedingungen, zu finden unter www.eltec.de.

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how to implement variable read/write variable in coreboot
by Melissa Yi Sept. 27, 2017

Sept. 27, 2017

Hi All, Does anyone know how to implement variable read/write in coreboot? like: how to create a block nvram to be accessed by uefipayload? Thanks. Regards, Melissa Yi www.celestica.com Solid Partners, Flexible Solutions

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Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work
by One7two99 Sept. 27, 2017

Sept. 27, 2017

Hello, after reading the dd howtos it seems that the 12 MB coreboot.rom file can be split like this: # Split first 8MB of coreboot.rom (bottom-chip) dd if=coreboot.rom of=x230-coreboot-8mb.rom bs=1024 count=$[1024*8] skip=0 # Split last 4MB of coreboot.rom (top-chip) dd if=coreboot.rom of=x230-coreboot-4mb.rom bs=1024 count=$[1024*4] skip=$[1024*8] at least this is what I did - while it was good enough that my X230 is booting up I still can't boot the secondary payloads (I have choosen nvramcui and coreinfo). As mentioned I am writing a howto whch is target at a newbie user, who has basic linux skills and has just about coreboot and wants to try it out. I've run the following steps (I've already written the howto which covers more information about each step, but unfortunately I can't access the wiki as an editor, asked for it already). If you thing I've missed out important steps, I am happy to hear your comments. --- on your raspberry pi --- 0) Put External Flash Clip, female jumper cables and Raspberry pi together (kind of a lego thing) 1) Install Raspberian on Pi using Noobs 2) Update Pi and install additional packages including 'flashrom' 3) take keyboard and palmrest of your "coreboot target laptop" (target) off to access the BIOS Chip(s) 4) Connect the BIOS-Clip to BIOS-chips and read the content from your pi (x230-default-part2-4mb.rom / x230-default-part2-8mb.rom) 5) merge the two files into one 12 MB ROM file (x230-default-12mb.rom) --- on your build laptop --- 6) Copy all three files to your "build laptop" (laptop) Build Laptop must run Linux, this howto assumes you are using Ubuntu 16.04.3 LTS (could also be installed on an USB thumbdrive or external harddrive) 7) Download Coreboot from GIT 7) Install UEFITool on laptop 8) Extract VGA BLOB from the x230-default-12mb.rom file save the file in the coreboot/blobs directory (./coreboot/3rdparty/blobs/mainboard/lenovo/x230/pci8086,0166.rom) 9) Build Coreboot Toolchain 10) Compile ifdtool located in the coreboot/utils directory 11) Extract BLOBS from x230-default-12mb.rom using ifdtool save the files in the coreboot/blobs directory (./coreboot/3rdparty/blobs/mainboard/lenovo/x230/descriptor.bin) (./coreboot/3rdparty/blobs/mainboard/lenovo/x230/me.bin) (./coreboot/3rdparty/blobs/mainboard/lenovo/x230/gbe.bin) 11b) [Optionally] Use ME_Cleaner on me.bin file ) (also it seems that ME_Cleaner is included in Coreboot: Coreboot nconfig: Chipset > Add Intel descriptor.bin file > Add Intel ME/TXE firmware --> Strip down the Intel ME/TXE firmware ) I've choosen to leave the me.bin as is until everything is working. 12) Configure Coreboot (make nconfig) choose parameters/features and add the 4 binary blobs (step 8 and 11) 13) build coreboot image (./coreboot/build/coreboot.rom) 14) Split coreboot.rom into two separate files to flash them to your 2 chips (x230-coreboot-8mb.rom and x230-coreboot-4mb.rom) 15) copy both files to your Raspberry Pi --- on your Raspberry pi --- 16) flash both files using flashrom again 17) Reboot target laptop 18) should boot up with coreboot. [799]

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Re: [coreboot] Intel Leaf Hill Coreboot Trouble
by Zoran Stojsavljevic Sept. 27, 2017

Sept. 27, 2017

Since I really want to help, and I do not have any time left for Coreboot (since I am fully/200% devoted to Fedora/RHEL/kernel.org and YOCTO), three kludge thinking from me (APL-I supposed to be my get_to_the_rich_pals_vehicle in Y2015, but mortally crashed somewhere in the process - For Good)!: [1] I did assemble APL-I Coreboot based upon www.intel.com/fsp (please, choose APL-I FSP release) APL-I FSP blobs. I did at the very end very clean compilation, but there are two catches 22 to what I did (significant credits/courtesy to Martin Roth, Martin really pulled me up and survived me in this weird FSP 2.0 crazy business of INTEL's)... ;-) [A] The Coreboot release I played with is: [user@localhost coreboot]$ git describe ==>> 4.5-1029-g97535558f1 (NOT 4.6); [B] Never tested it on real HW, I do NOT have APL-I HW, Leaf Hill, Deaf Hill or you name it... But I did attach my .config/CONFIG! [2] As my .config (attached CONFIG) suggests, please, try with some other payload (SeaBIOS as for example, which I used); [3] You need to compare my .config with yours (I have neither any time, neither any desire to do this). Good Luck, very much/totally INTEL 2.0 FSP (doomed to the bones) dependent enthusiast (I can still advise out of desperation, if you investigate and continue posting results here). P.S. Martin (Roth), once again, thank you for unselfish help (I do remember)! :-) Zoran _______ On Wed, Sep 27, 2017 at 2:01 PM, Cameron Craig <Cameron.Craig(a)exterity.com> wrote: > Hi All, > > > > I’m currently trying to get coreboot working on an Intel Leaf Hill > development board, we are using U-Boot as a payload. > > > > I have managed to create a bootable image using an out of date copy of > coreboot and U-Boot, provided by Intel under NDA. > > The stitching process used to generate the image is a little ugly: a set > of Windows tools are provided (or pointed at) by Intel to stitch the > various blobs together to create an 8MB image. > > We would like to move away from this process. Using the cbfs tool it looks > like we are getting a legacy image composed entirely of a single CBFS. > > > > However, as far as I understand, the latest coreboot release (v4.6) should > be capable of producing a 16MB working image without the use of external > tools. > > This is of course dependent on the provision of the correct binary blobs > such as the FSP, flash descriptor and IFWI. > > I have attached the descriptor of the IFWI image being used. > > > > This is the process I have followed in order to generate a coreboot image: > > 1. Clone coreboot (v4.6) > > 2. Obtain Apollo Lake FSP from Intel (https://github.com/IntelFSP/ > FSP) > > 3. Split FSP into its constituent parts (https://raw. > githubusercontent.com/tianocore/edk2/master/IntelFsp2Pkg/Tools/ > SplitFspBin.py) > > 4. Extract Flash Descriptor from an existing Leaf Hill UEFI image > (./ifdtool --extract leaf_hill_ref_board_uefi.bin) > > 5. Obtain IFWI image from Intel (Apollo Lake Technical Library) > > 6. make menuconfig (config file is attached) > > a. Mainboard > > i. Mainboard > vendor (Intel) > > ii. Mainboard > model (Leafhill) > > iii. [*] > Use IFWI Stitching > > iv. (IFWI) > section in .fmd file to place IFWI blob > > v. (IFWI_SPI.bin) > Path to image coming from FIT Tool > > vi. (descriptor.bin) > path to descriptor.bin > > vii. (Fsp_M.fd) > path to FSP-M.Fv blob > > viii. (Fsp_S.fd) > path to FSP-S.Fv > > b. Payload > > i. Add > a payload (U-Boot (Experimental)) > > ii. U-Boot > version (v2016.1) > > iii. (coreboot-x86_defconfig) > U-Boot config file > > c. The rest are at Leaf Hill defaults. > > 7. make > > 8. Flash image to Leaf Hill SPI flash > > > > As far as I can tell, this process should produce a working image. > > However it does not. My most recent attempt has managed to blink the > PWR_OK LED, suggesting the PMIC/PMC is working, but no serial messages. > > Other than that, I currently have no working theories as to what the root > cause is L > > > > Is there anything obviously wrong with this process? > > Are there any bugs that I should be aware of relating to coreboot on an > Apollo Lake platform? > > I haven’t found a lot of documentation online to describe the exact > configuration and blob usage, are there any relevant sources of > documentation you could point me towards? > > > > Any help to answer the above, or any other advice would be greatly > appreciated. > > > > Cheers, > > Cameron > > > > Cameron Craig | Graduate Software Engineer | Exterity Limited > tel: +44 1383 828 250 <+44%201383%20828250> | fax: > e: Cameron.Craig(a)exterity.com | w: www.exterity.com > > <http://www.exterity.com> > [image: ISO9001] <http://www.exterity.com/iso9001> [image: LinkedIn] > <http://www.linkedin.com/company/exterity> [image: Twitter] > <http://www.twitter.com/exterity> [image: YouTube] > <http://www.youtube.com/user/exterityiptv> > Exterity is a leading provider of IP Video and Digital Signage solutions > that helps organizations to harness the power of video to communicate, > educate and entertain. Our end-to-end solutions enable you to take TV and > video content directly from any source and manage its delivery, live or on > demand, to any connected device via your existing network. For more > information or to schedule a product demonstration, contact Exterity on +44(0)1383 > 828 250 <+44%201383%20828250> or visit www.exterity.com > > Legal Notice > Unless expressly stated otherwise, this message is confidential and may be > privileged. It is intended for the addressee(s) only. Access to this e-mail > by anyone else is unauthorized. If you are not an addressee, any disclosure > or copying of the contents of this e-mail or any action taken (or not > taken) in reliance on it is unauthorized and may be unlawful. If you are > not an addressee, please inform the sender immediately. > > Exterity Limited is registered in Scotland under No. 225313 with its > registered office at St Davids House, St Davids Drive, Dalgety Bay, KY11 9NB > > > ______________________________________________________________________ > This email has been scanned by the Symantec Email Security.cloud service. > For more information please visit http://www.symanteccloud.com > ______________________________________________________________________ > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] Coreboot+SeaBios Boot speed: ~12sec till Grub Boot Screen
by One7two99 Sept. 27, 2017

Sept. 27, 2017

Hello Martin, >> You don"t have serial console enabled, so that"s not the issue. >> I would recommend going into the console menu and enabling "Send >> console output to a CBMEM buffer". >> Once you boot to an OS, you"ll be able to see that with cbmem, which >> needs to be run as root. Ok thank you for the idea, as I am running Qubes OS on my X230, I must install coreboot in dom0 (the core vm, where no other software should be running/installed). I think I'll try to use cbmem from an ubuntu which runs on a USB-drive, so that I don't have to touch my Qubes Installation. >> Everything looks ok in the config to me, so I"m not positive what >> the issue is. We"d need to get a bit deeper into things to figure it out. As mentioned my current configuration is far from beeing perfect, as my secondary payloads are shown in the coreboot (escape-key) menu but if I select them, they don't seem to work (blank screen). I think that I've made something wrong splitting the compiled Coreboot.rom on my two Chips (4MB + 12MB) or that I am missing some other configuration steps after I've changed my CBFS from 0x10000 to 0x40000. If you/someone can provide any guidance here, this would be great. Before I try to reduce the bootup time I'd like to get a fully working coreboot including secondary payloads (mainly to use the "View Timestamps" feature). kind regards [799] On Mon, Sep 25, 2017 at 6:30 PM, One7two99 via coreboot <coreboot(a)coreboot.org> wrote: > Hello Martin, > > > -------- Original Message -------- > Subject: Re: [coreboot] Coreboot+SeaBios Boot speed: ~12sec till Grub Boot > Screen > Local Time: 25 September 2017 3:53 AM > From: gaumless(a)gmail.com > > Is serial console enabled? If so, disabling that will speed things up > immensely. > > > To which position in the menuconfig tree are you referencing? > Have disabled all entries under "Console" in menuconfig but still get the > boot delay. > I"ve thecoreboot .config in case that this is helpfull, see attached file. > > > Can you post a miniconfig? Run "make savedefconfig" and post the file > "defconfig"? > > > Sure, at your service: > > $ make savedefconfig && cat defconfig > CONFIG_USE_OPTION_TABLE=y > CONFIG_COLLECT_TIMESTAMPS=y > CONFIG_VENDOR_LENOVO=y > CONFIG_CBFS_SIZE=0x400000 > CONFIG_VGA_BIOS=y > CONFIG_VGA_BIOS_FILE="~/my-coreboot/MyROMs/original/vga.rom" > # CONFIG_POST_IO is not set > # CONFIG_POST_DEVICE is not set > CONFIG_BOARD_LENOVO_X230=y > CONFIG_DRIVERS_PS2_KEYBOARD=y > # CONFIG_CONSOLE_CBMEM is not set > CONFIG_CPU_MICROCODE_CBFS_NONE=y > CONFIG_SEABIOS_PS2_TIMEOUT=10 > # CONFIG_DRIVERS_INTEL_WIFI is not set > CONFIG_LPC_TPM=y > # CONFIG_SQUELCH_EARLY_SMP is not set > CONFIG_SEABIOS_MASTER=y > CONFIG_SEABIOS_THREAD_OPTIONROMS=y > CONFIG_COREINFO_SECONDARY_PAYLOAD=y > > Can you post timestamp information so we can see what"s using all the time? > > > Unfortunately not as I haven"t been able to create a 2nd payload in order to > read the timstamps from coreinfo. > Coreinfo is shown in the boot menu when hitting ESC, but after launching, > the screen goes blank and nothing happens. > Maybe this is related to the fact, that I flashed only 4 MB of the Chip(s) > and as such some part of the code is missing (whoch would be in the 8 MB > part of the rom-file)? > > [799] > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot

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Intel Leaf Hill Coreboot Trouble
by Cameron Craig Sept. 27, 2017

Sept. 27, 2017

Hi All, I’m currently trying to get coreboot working on an Intel Leaf Hill development board, we are using U-Boot as a payload. I have managed to create a bootable image using an out of date copy of coreboot and U-Boot, provided by Intel under NDA. The stitching process used to generate the image is a little ugly: a set of Windows tools are provided (or pointed at) by Intel to stitch the various blobs together to create an 8MB image. We would like to move away from this process. Using the cbfs tool it looks like we are getting a legacy image composed entirely of a single CBFS. However, as far as I understand, the latest coreboot release (v4.6) should be capable of producing a 16MB working image without the use of external tools. This is of course dependent on the provision of the correct binary blobs such as the FSP, flash descriptor and IFWI. I have attached the descriptor of the IFWI image being used. This is the process I have followed in order to generate a coreboot image: 1. Clone coreboot (v4.6) 2. Obtain Apollo Lake FSP from Intel (https://github.com/IntelFSP/FSP) 3. Split FSP into its constituent parts (https://raw.githubusercontent.com/tianocore/edk2/master/IntelFsp2Pkg/Tools/…) 4. Extract Flash Descriptor from an existing Leaf Hill UEFI image (./ifdtool --extract leaf_hill_ref_board_uefi.bin) 5. Obtain IFWI image from Intel (Apollo Lake Technical Library) 6. make menuconfig (config file is attached) a. Mainboard i. Mainboard vendor (Intel) ii. Mainboard model (Leafhill) iii. [*] Use IFWI Stitching iv. (IFWI) section in .fmd file to place IFWI blob v. (IFWI_SPI.bin) Path to image coming from FIT Tool vi. (descriptor.bin) path to descriptor.bin vii. (Fsp_M.fd) path to FSP-M.Fv blob viii. (Fsp_S.fd) path to FSP-S.Fv b. Payload i. Add a payload (U-Boot (Experimental)) ii. U-Boot version (v2016.1) iii. (coreboot-x86_defconfig) U-Boot config file c. The rest are at Leaf Hill defaults. 7. make 8. Flash image to Leaf Hill SPI flash As far as I can tell, this process should produce a working image. However it does not. My most recent attempt has managed to blink the PWR_OK LED, suggesting the PMIC/PMC is working, but no serial messages. Other than that, I currently have no working theories as to what the root cause is ☹ Is there anything obviously wrong with this process? Are there any bugs that I should be aware of relating to coreboot on an Apollo Lake platform? I haven’t found a lot of documentation online to describe the exact configuration and blob usage, are there any relevant sources of documentation you could point me towards? Any help to answer the above, or any other advice would be greatly appreciated. Cheers, Cameron Cameron Craig | Graduate Software Engineer | Exterity Limited tel: +44 1383 828 250 | fax: e: Cameron.Craig(a)exterity.com | w: www.exterity.com [cid:image2640ac.PNG@354fb716.4f862c23]<www.exterity.com> [ISO9001]<http://www.exterity.com/iso9001> [LinkedIn] <http://www.linkedin.com/company/exterity> [Twitter] <http://www.twitter.com/exterity> [YouTube] <http://www.youtube.com/user/exterityiptv> Exterity is a leading provider of IP Video and Digital Signage solutions that helps organizations to harness the power of video to communicate, educate and entertain. Our end-to-end solutions enable you to take TV and video content directly from any source and manage its delivery, live or on demand, to any connected device via your existing network. For more information or to schedule a product demonstration, contact Exterity on +44(0)1383 828 250 or visit www.exterity.com Legal Notice Unless expressly stated otherwise, this message is confidential and may be privileged. It is intended for the addressee(s) only. Access to this e-mail by anyone else is unauthorized. If you are not an addressee, any disclosure or copying of the contents of this e-mail or any action taken (or not taken) in reliance on it is unauthorized and may be unlawful. If you are not an addressee, please inform the sender immediately. Exterity Limited is registered in Scotland under No. 225313 with its registered office at St Davids House, St Davids Drive, Dalgety Bay, KY11 9NB ______________________________________________________________________ This email has been scanned by the Symantec Email Security.cloud service. For more information please visit http://www.symanteccloud.com ______________________________________________________________________

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