coreboot September 2017

coreboot@coreboot.org

57 participants
132 discussions

Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work
by Matt DeVillier 24 Sep '17

24 Sep '17

On Sep 23, 2017 12:35 PM, "One7two99 via coreboot" <coreboot(a)coreboot.org> wrote: -------- Original-Nachricht -------- an 23. Sep. 2017, 16:56, Klemens Nanni schrieb: >> These are 4/8 *mebi*byte in size. Yes of course ;-) just a typo as I am more used working with GB than MB these days... >> Web search shows X230 uses UEFI >> so you'll need UEFITool instead. Thanks, I'll give this a try. The Coreboot Wiki states that it is also possible to get the VGA blob from Intel itself: "(...) For Intel onboard graphics you can download the vbios (vga bios) from Intel's download section. The vbios is included with some versions of the graphics driver. The summary will say something like "NOTE:These materials are intended for use by developers.Includes VBIOS". The actual vbios file is the *.dat file included with the graphics driver. (...)" Unfortunately a Link to the correct download page at Intels Website to get the VGA BIOS is the only missing information. I've searched for Intel VBIOS and found the following page: https://downloadcenter.intel.com/download/26069/Intel- Embedded-Media-and-Graphics-Driver-for-VBIOS-build-3967- v36-2-11-32-bit-Install-Package "(...) This install package downloads the Intel® Embedded Media and Graphics Driver for VBIOS (build #3967), 32-bit. This is the graphics driver installation package for the Intel® Atom™ Processor E3800 product family and the Intel® Celeron® Processor N2920/J1900, bundled with user guide and release notes text files. The 32-bit VBIOS supports legacy boot and could be used at both 32-bit or 64-bit operating system booting. (...)" As it only mentions the Intel Atom and Celeron CPUs I am unsure if I should try to use the VBIOS for my X230 which has a Core i5 CPU. Within the Zip-file you can find a file named "Vga.dat" (64k Size) in the folder IEMGD_HEAD_VBIOS\Release which is the VBIOS file according to the Coreboot wiki. Question: Can I use this file for my X230? absolutely not. You need to use one which is for your GPU/platform, and configured to match the outputs on your x230. Which is why it's best to extract from the vendor firmware using UEFITool

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Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work
by Klemens Nanni 24 Sep '17

24 Sep '17

On Sat, Sep 23, 2017 at 02:39:16PM +0000, One7two99 via coreboot wrote: > I tried to run bios_extract against both of my rom files (which I've read from both chips) but get the same error message: > > ./bios_extract ../MyROMs/original/x230-4GB.rom > and > ./bios_extract ../MyROMs/original/x230-8GB.rom These are 4/8 *mebi*byte in size. > in both cases I get the result: > > "Error: Unable to detect BIOS Image type" Web search shows X230 uses UEFI so you'll need UEFITool instead.

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Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work
by Klemens Nanni 24 Sep '17

24 Sep '17

On Sat, Sep 23, 2017 at 02:09:32PM +0000, One7two99 via coreboot wrote: > I would like to rebuild my Coreboot now so that it supports dualbooting (Linux / Windows). > > Most howtos for the X230 only cover the flashing without supporting graphical boot. > The wiki page http://www.coreboot.org/VGA_support seem to cover some part, but is not specific to the X230. Not sure if X230 is shipped with BIOS or UEFI, but either methods desribed on that page will work. Use the vendor image if possible to extract the VGA Option ROM. A valid dump will be exactly 64K in size, the first two bytes being `55 aa'. > Has someone build coreboot including the support for graphics from startup to be able to boot into windows? > > I'm interested in what to choose in "make menuconfig" and where to get the vga bios rom for the x230, I would then condense the information in a X230 How-to for Dualboot-Setup. I never booted Windows but here are my coreboot and SeaBIOS configurations used in a working build including the pci8086,0166.rom blob to initialise graphics.

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Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work
by One7two99 24 Sep '17

24 Sep '17

Some additional information what I tried already: -------- Original-Nachricht -------- An 23. Sep. 2017, 16:09, One7two99 via coreboot schrieb: >> The wiki page http://www.coreboot.org/VGA_support >> seem to cover some part, but is not specific to the X230. I downloaded and installed bios_extract via: git clone http://review.coreboot.org/p/bios_extract.git cd bios_extract make I tried to run bios_extract against both of my rom files (which I've read from both chips) but get the same error message: ./bios_extract ../MyROMs/original/x230-4GB.rom and ./bios_extract ../MyROMs/original/x230-8GB.rom in both cases I get the result: "Error: Unable to detect BIOS Image type" I have verified those files by reflashing them after flashing coreboot and as everything was working both files are ok. Do I need to combine them into one big file or why can't I use bios-extract to get the VGA ROM out of it? [799]

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Coreboot on X230 and Dualboot / How to make it work
by One7two99 24 Sep '17

24 Sep '17

Hello, After some initial help from Lynxis/AFRA Berlin I got my X230 initial flashed with coreboot. After getting the proper equipment I have now also reflashed several time both Chips to understand how the build and flashing process works. Booting Linux/Qubes is working great with Coreboot. Also no impact on Peripherals like LTE card, battery runtime. I would like to rebuild my Coreboot now so that it supports dualbooting (Linux / Windows). Most howtos for the X230 only cover the flashing without supporting graphical boot. The wiki page http://www.coreboot.org/VGA_support seem to cover some part, but is not specific to the X230. Has someone build coreboot including the support for graphics from startup to be able to boot into windows? I'm interested in what to choose in "make menuconfig" and where to get the vga bios rom for the x230, I would then condense the information in a X230 How-to for Dualboot-Setup. [799]

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Re: [coreboot] ME hacking @ BlackHat
by Timothy Pearson 23 Sep '17

23 Sep '17

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 09/22/2017 03:30 PM, Rene Shuster wrote: > https://www.blackhat.com/eu-17/briefings/schedule/index.html#how-to-hack-a-… We've been aware of this for a couple of days now. Most interesting is that this has been given zero coverage in the tech press, especially given that for datacenters and Linux / BSD users multiple other secure options exist (ARM, OpenPOWER, SPARC, etc.). I'll be very interested to see where this goes and what the scope of the breach actually is. - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQEcBAEBAgAGBQJZxXlMAAoJEK+E3vEXDOFbecoH/1UM2zdWcTmfZ0SgFyIehcUY 0Fr1C2zr5DQrmlIgwvygNOUD/1Rt/NPdTWKTQE7eBwa9r3viRTPrjJsMBWtFE4te 9FrH+21XEPue0zmUR5mTeiNErMYrebA1xArijIuVXWO6PlfHegSnd8PKiryXmLXR poYENshGhIxYLjh9L+e6UwHvTwk3z6WqZMAtxGLICXzaQ+KDaTAi4q5/TSvE/lRn 4ClXTKRs0FiQwTbaP3nZNz0TNEtPVt2OBZv0snuoe8HijLhrABsYVe3xNU6lb0BT dIFx3k9f2LUHlS6taQKMcL68qoLwpkHcZtRsOnJ2uauH1L8XjHlZs7lGh1VPrZY= =Zkn1 -----END PGP SIGNATURE-----

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ME hacking @ BlackHat
by Rene Shuster 23 Sep '17

23 Sep '17

https://www.blackhat.com/eu-17/briefings/schedule/index.html#how-to-hack-a-… -- Tech III * AppControl * Endpoint Protection * Server Maintenance Buncombe County Schools Technology Department Network Group ComicSans Awareness Campaign <http://comicsanscriminal.com>

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MacBook development
by Bryce Prescott 23 Sep '17

23 Sep '17

Wondering if support for 3, 1 / 4, 1 / 5, 2 is in the works.

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Re: [coreboot] ECC’17: Fund developer travel costs
by Zaolin 23 Sep '17

23 Sep '17

We can also help out to finding cheap hotels if needed. In order to do so, please contact Justine Spalik: justine.spalik(a)9elements.com <mailto:justine.spalik@9elements.com?subject=Contact%20from%20Website%3A%20ECC%2717> On 22.09.2017 08:44, Paul Menzel wrote: > Dear coreboot folks, > > > The European coreboot conference 2017 is around the corner and starts > on October 26th [1]. > > Are there developers who need funding of their travel costs? Kyösti, > Arthur, Patrick, …? Please tell the community and note the amount. > > Until we know for sure, it’d be great if the coreboot community members > would be willing to fund some of these costs. > > > Thanks, > > Paul > > > [1] https://ecc2017.coreboot.org/ > >

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 23 Sep '17

23 Sep '17

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 5 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 5 of 5 defect(s) ** CID 1381373: Control flow issues (MISSING_BREAK) /src/device/dram/ddr2.c: 197 in spd_decode_tRR_time() ________________________________________________________________________________________________________ *** CID 1381373: Control flow issues (MISSING_BREAK) /src/device/dram/ddr2.c: 197 in spd_decode_tRR_time() 191 switch (c) { 192 default: 193 printk(BIOS_WARNING, "Invalid tRR value 0x%x\n", c); 194 return CB_ERR; 195 case 0x80: 196 *tRR = 15625 << 8; >>> CID 1381373: Control flow issues (MISSING_BREAK) >>> The above case falls through to this one. 197 case 0x81: 198 *tRR = 15625 << 6; 199 case 0x82: 200 *tRR = 15625 << 7; 201 case 0x83: 202 *tRR = 15625 << 9; ** CID 1381372: Control flow issues (MISSING_BREAK) /src/device/dram/ddr2.c: 199 in spd_decode_tRR_time() ________________________________________________________________________________________________________ *** CID 1381372: Control flow issues (MISSING_BREAK) /src/device/dram/ddr2.c: 199 in spd_decode_tRR_time() 193 printk(BIOS_WARNING, "Invalid tRR value 0x%x\n", c); 194 return CB_ERR; 195 case 0x80: 196 *tRR = 15625 << 8; 197 case 0x81: 198 *tRR = 15625 << 6; >>> CID 1381372: Control flow issues (MISSING_BREAK) >>> The above case falls through to this one. 199 case 0x82: 200 *tRR = 15625 << 7; 201 case 0x83: 202 *tRR = 15625 << 9; 203 case 0x84: 204 *tRR = 15625 << 10; ** CID 1381371: Control flow issues (MISSING_BREAK) /src/device/dram/ddr2.c: 203 in spd_decode_tRR_time() ________________________________________________________________________________________________________ *** CID 1381371: Control flow issues (MISSING_BREAK) /src/device/dram/ddr2.c: 203 in spd_decode_tRR_time() 197 case 0x81: 198 *tRR = 15625 << 6; 199 case 0x82: 200 *tRR = 15625 << 7; 201 case 0x83: 202 *tRR = 15625 << 9; >>> CID 1381371: Control flow issues (MISSING_BREAK) >>> The above case falls through to this one. 203 case 0x84: 204 *tRR = 15625 << 10; 205 case 0x85: 206 *tRR = 15625 << 11; 207 } 208 return CB_SUCCESS; ** CID 1381370: Control flow issues (MISSING_BREAK) /src/device/dram/ddr2.c: 205 in spd_decode_tRR_time() ________________________________________________________________________________________________________ *** CID 1381370: Control flow issues (MISSING_BREAK) /src/device/dram/ddr2.c: 205 in spd_decode_tRR_time() 199 case 0x82: 200 *tRR = 15625 << 7; 201 case 0x83: 202 *tRR = 15625 << 9; 203 case 0x84: 204 *tRR = 15625 << 10; >>> CID 1381370: Control flow issues (MISSING_BREAK) >>> The above case falls through to this one. 205 case 0x85: 206 *tRR = 15625 << 11; 207 } 208 return CB_SUCCESS; 209 } 210 ** CID 1381369: Control flow issues (MISSING_BREAK) /src/device/dram/ddr2.c: 201 in spd_decode_tRR_time() ________________________________________________________________________________________________________ *** CID 1381369: Control flow issues (MISSING_BREAK) /src/device/dram/ddr2.c: 201 in spd_decode_tRR_time() 195 case 0x80: 196 *tRR = 15625 << 8; 197 case 0x81: 198 *tRR = 15625 << 6; 199 case 0x82: 200 *tRR = 15625 << 7; >>> CID 1381369: Control flow issues (MISSING_BREAK) >>> The above case falls through to this one. 201 case 0x83: 202 *tRR = 15625 << 9; 203 case 0x84: 204 *tRR = 15625 << 10; 205 case 0x85: 206 *tRR = 15625 << 11; ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0… To manage Coverity Scan email notifications for "coreboot(a)coreboot.org", click https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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coreboot September 2017