September 2017 - coreboot - mail.coreboot.org

Re: [coreboot] 64 UEFI payload boot fail on Denverton platform but 32 UEFI payload works
by Szafranski, MariuszX Sept. 22, 2017

Sept. 22, 2017

Verified payload was built using code based on EDK2 code commit: >commit c1b0828b3ba8fa203033ede0c3329c0d5573719e >Author: Zhang, Chao B <chao.b.zhang(a)intel.com> >Date: Wed Jan 25 12:50:55 2017 +0800 > > SecurityPkg: Tcg2Dxe: Update PCR[4] measure logic …………………………………………………….. from git repo at https://github.com/tianocore/edk2 (master branch) From: Melissa Yi [mailto:huayi@celestica.com] Sent: Friday, September 22, 2017 10:53 AM To: Szafranski, MariuszX <mariuszx.szafranski(a)intel.com> Cc: coreboot(a)coreboot.org Subject: Re: [coreboot] 64 UEFI payload boot fail on Denverton platform but 32 UEFI payload works Hi Mariusz, which revision of EDK2 do you use? I used SVN 35017 Thanks. Regards, Melissa Yi BIOS Lead Engineer Celestica(Shanghai) R&D Center, China www.celestica.com<http://www.celestica.com/> Solid Partners, Flexible Solutions 2017-09-22 15:16 GMT+08:00 Szafranski, MariuszX <mariuszx.szafranski(a)intel.com<mailto:mariuszx.szafranski@intel.com>>: Hi, It was tested on Denverton_NS platform using mainly 64bit UEFI payload. 32bit UEFI payload was tested also. Both UEFI payload versions should behave similarly when built from same source code using same coreboot configs. I didn`t noticed difference between 32 and 64 versions. BR, Mariusz From: coreboot [mailto:coreboot-bounces@coreboot.org<mailto:coreboot-bounces@coreboot.org>] On Behalf Of Melissa Yi Sent: Thursday, September 21, 2017 11:21 AM To: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: [coreboot] 64 UEFI payload boot fail on Denverton platform but 32 UEFI payload works Hi I want to know whether coreboot supports 64bit UEFI payload on denverton platform? Attached the fail log. Thanks. Regards, Melissa Yi -------------------------------------------------------------- Intel Research and Development Ireland Limited Registered in Ireland Registered Office: Collinstown Industrial Park, Leixlip, County Kildare Registered Number: 308263 This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://mail.coreboot.org/mailman/listinfo/coreboot -------------------------------------------------------------- Intel Research and Development Ireland Limited Registered in Ireland Registered Office: Collinstown Industrial Park, Leixlip, County Kildare Registered Number: 308263 This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies.

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Re: [coreboot] 64 UEFI payload boot fail on Denverton platform but 32 UEFI payload works
by WANG FEI Sept. 22, 2017

Sept. 22, 2017

I can confirm coreboot has no issue to support 64 bit UEFI payload, it's already verified. Can you please provide more information of your coreboot/payload? Like, coreboot revision/commit ID, payload revision/commid ID, FSP revision, platform details (CRB or OEM platform) etc. On Thu, Sep 21, 2017 at 10:20 AM, Melissa Yi <huayi(a)celestica.com> wrote: > Hi > I want to know whether coreboot supports 64bit UEFI payload on > denverton platform? > Attached the fail log. > > Thanks. > > Regards, > Melissa Yi > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] 64 UEFI payload boot fail on Denverton platform but 32 UEFI payload works
by Melissa Yi Sept. 22, 2017

Sept. 22, 2017

Hi The 32bit build log is attached, the log is too big so I compressed it. I didn't find out some important information between them. I will contact Intel team directly, thanks for your help. Thanks. Regards, Melissa Yi 2017-09-22 15:25 GMT+08:00 Zoran Stojsavljevic < zoran.stojsavljevic(a)gmail.com>: > I have looked into the log. I see that INTEL FSP (for what I know) works > correctly. It entered bunch of phases (now there are many, NOT only three). > Anyway, scary stuff, directly taken from INTEL BIOS development, and > tailored as "FSP" per say. > > I also see that MRC passed (there is in total 6 GB of DDR3 memory there), > I see that dynamic PCIe discovery worked correctly. > > At the end of Coreboot booting, we see the following boot sequence: > > [SPS] SpsFspReadyToBootEvent Start > [SPS] Looking for SPS HOB info .. > [SPS] HOB: flow 1, feature set 0x9B8106, pwr opt boot 0, cores2disable 0 > [SPS] SpsFspSendEndOfPost Start > [SPS] Sending END_OF_POST to ME > [HECI] Send msg: 80040007 00000CFF > [HECI] Got msg: 80080007 00008CFF ... > [SPS] SpsFspSendEndOfPost End > [SPS] Disabling Global Reset capability > [SPS] SpsFspReadyToBootEvent End Success > > From my modest knowledge, I see that HECI I/F between ME and Coreboot > still works as expected (actually between HECI and FSP embedded in > Coreboot, at the end of Coreboot, hidden from Coreboot designers). Also > what I see as a non-standard set of features added is SPS addendum, which > should be the following: > *SPS -> INTEL Server Platform Services (since Denverton belongs to class > of micro servers, as I correctly remember)?! <<== This makes (maybe) some > difference from the normal booting!?* > > And, at the very end, EDKII taking over Coreboot (my best guess from the > end of the log): > > NotifyPhaseApi() - End [Status: 0x00000000] > BS: BS_PAYLOAD_LOAD times (us): entry 0 run 1091381 exit 707003 > COLLECT_TIMESTAMPS: Coreboot took 59501373064 <0595%200137%203064> TSC > ticks > Total booting time : 28.333987 seconds > *Jumping to boot code at 00800340(7f7c8000) <<== EDKII takes over* > *CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cabc, stack > used: 1348 bytes <<== Too low stack value of 4KB (maybe, only one page), > seems...* > entry = 0x00800340 > lb_start = 0x00100000 > lb_size = 0x000358b0 > buffer = 0x7f726000 > PROGRESS CODE: V03020003 I0 > Loading PEIM at 0x00000813BA0 EntryPoint=0x00000813EDF CbSupportPeim.efi > PROGRESS CODE: V03020002 I0 > 0. 0000000000000000 - 0000000000000FFF [10] > 1. 0000000000001000 - 000000000009FFFF [01] > 2. 0000000000100000 - 000000007F791FFF [01] > 3. 000000007F792000 - 000000007FBFFFFF [10] > 4. 000000007FC00000 - 000000007FFFFFFF [02] > 5. 00000000E0000000 - 00000000EFFFFFFF [02] > 6. 0000000100000000 - 000000017FFFFFFF [01] > Low memory 0x7F792000 > SystemLowMemTop 0x80000000 > PeiMemBase: 0x7B790000. > PeiMemSize: 0x4000000. > PeiInstallPeiMemory MemoryBegin 0x7B790000, MemoryLength 0x4000000 > Found one valid fv : 0x4C000000830000. > Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 > Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry > point: 802069 > The 1th FV start address is 0x00000830000, size is 0x004C0000, handle is > 0x830000 > > Melissa, > > If bunch of @intel.com folks will not help you (they should), you should > do the same exercise with 32bit EDKII as payload, and compare tail -100 > (last 100 lines of log, where 64bit EDKII fails). > > Hope this helps...?! > > Good luck! :-) > Zoran Stojsavljevic > _______ > > On Fri, Sep 22, 2017 at 8:46 AM, Patrick Georgi via coreboot < > coreboot(a)coreboot.org> wrote: > >> 2017-09-22 3:33 GMT+02:00 Melissa Yi <huayi(a)celestica.com>: >> > Anyone can give some information? >> Probably not. >> >> 64bit tianocore as payload should work in general (since it still >> comes with a 32bit entry point, just switches to long mode really >> early). >> It's hard to tell what's going on if the entire report is "doesn't work". >> >> >> Regards, >> Patrick Georgi >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://mail.coreboot.org/mailman/listinfo/coreboot >> > >

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Re: [coreboot] 64 UEFI payload boot fail on Denverton platform but 32 UEFI payload works
by Melissa Yi Sept. 22, 2017

Sept. 22, 2017

Hi Mariusz, which revision of EDK2 do you use? I used SVN 35017 Thanks. Regards, Melissa Yi BIOS Lead Engineer Celestica(Shanghai) R&D Center, China www.celestica.com Solid Partners, Flexible Solutions 2017-09-22 15:16 GMT+08:00 Szafranski, MariuszX < mariuszx.szafranski(a)intel.com>: > Hi, > > > > It was tested on Denverton_NS platform using mainly 64bit UEFI payload. > 32bit UEFI payload was tested also. > > Both UEFI payload versions should behave similarly when built from same > source code using same coreboot configs. > > I didn`t noticed difference between 32 and 64 versions. > > > > BR, > > Mariusz > > > > *From:* coreboot [mailto:coreboot-bounces@coreboot.org] *On Behalf Of *Melissa > Yi > *Sent:* Thursday, September 21, 2017 11:21 AM > *To:* coreboot(a)coreboot.org > *Subject:* [coreboot] 64 UEFI payload boot fail on Denverton platform but > 32 UEFI payload works > > > > Hi > > I want to know whether coreboot supports 64bit UEFI payload on > denverton platform? > > Attached the fail log. > > > > Thanks. > > > Regards, > > Melissa Yi > > -------------------------------------------------------------- > Intel Research and Development Ireland Limited > Registered in Ireland > Registered Office: Collinstown Industrial Park, Leixlip, County Kildare > Registered Number: 308263 > > This e-mail and any attachments may contain confidential material for the > sole use of the intended recipient(s). Any review or distribution by others > is strictly prohibited. If you are not the intended recipient, please > contact the sender and delete all copies. > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] 64 UEFI payload boot fail on Denverton platform but 32 UEFI payload works
by Zoran Stojsavljevic Sept. 22, 2017

Sept. 22, 2017

I have looked into the log. I see that INTEL FSP (for what I know) works correctly. It entered bunch of phases (now there are many, NOT only three). Anyway, scary stuff, directly taken from INTEL BIOS development, and tailored as "FSP" per say. I also see that MRC passed (there is in total 6 GB of DDR3 memory there), I see that dynamic PCIe discovery worked correctly. At the end of Coreboot booting, we see the following boot sequence: [SPS] SpsFspReadyToBootEvent Start [SPS] Looking for SPS HOB info .. [SPS] HOB: flow 1, feature set 0x9B8106, pwr opt boot 0, cores2disable 0 [SPS] SpsFspSendEndOfPost Start [SPS] Sending END_OF_POST to ME [HECI] Send msg: 80040007 00000CFF [HECI] Got msg: 80080007 00008CFF ... [SPS] SpsFspSendEndOfPost End [SPS] Disabling Global Reset capability [SPS] SpsFspReadyToBootEvent End Success >From my modest knowledge, I see that HECI I/F between ME and Coreboot still works as expected (actually between HECI and FSP embedded in Coreboot, at the end of Coreboot, hidden from Coreboot designers). Also what I see as a non-standard set of features added is SPS addendum, which should be the following: *SPS -> INTEL Server Platform Services (since Denverton belongs to class of micro servers, as I correctly remember)?! <<== This makes (maybe) some difference from the normal booting!?* And, at the very end, EDKII taking over Coreboot (my best guess from the end of the log): NotifyPhaseApi() - End [Status: 0x00000000] BS: BS_PAYLOAD_LOAD times (us): entry 0 run 1091381 exit 707003 COLLECT_TIMESTAMPS: Coreboot took 59501373064 TSC ticks Total booting time : 28.333987 seconds *Jumping to boot code at 00800340(7f7c8000) <<== EDKII takes over* *CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cabc, stack used: 1348 bytes <<== Too low stack value of 4KB (maybe, only one page), seems...* entry = 0x00800340 lb_start = 0x00100000 lb_size = 0x000358b0 buffer = 0x7f726000 PROGRESS CODE: V03020003 I0 Loading PEIM at 0x00000813BA0 EntryPoint=0x00000813EDF CbSupportPeim.efi PROGRESS CODE: V03020002 I0 0. 0000000000000000 - 0000000000000FFF [10] 1. 0000000000001000 - 000000000009FFFF [01] 2. 0000000000100000 - 000000007F791FFF [01] 3. 000000007F792000 - 000000007FBFFFFF [10] 4. 000000007FC00000 - 000000007FFFFFFF [02] 5. 00000000E0000000 - 00000000EFFFFFFF [02] 6. 0000000100000000 - 000000017FFFFFFF [01] Low memory 0x7F792000 SystemLowMemTop 0x80000000 PeiMemBase: 0x7B790000. PeiMemSize: 0x4000000. PeiInstallPeiMemory MemoryBegin 0x7B790000, MemoryLength 0x4000000 Found one valid fv : 0x4C000000830000. Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: 802069 The 1th FV start address is 0x00000830000, size is 0x004C0000, handle is 0x830000 Melissa, If bunch of @intel.com folks will not help you (they should), you should do the same exercise with 32bit EDKII as payload, and compare tail -100 (last 100 lines of log, where 64bit EDKII fails). Hope this helps...?! Good luck! :-) Zoran Stojsavljevic _______ On Fri, Sep 22, 2017 at 8:46 AM, Patrick Georgi via coreboot < coreboot(a)coreboot.org> wrote: > 2017-09-22 3:33 GMT+02:00 Melissa Yi <huayi(a)celestica.com>: > > Anyone can give some information? > Probably not. > > 64bit tianocore as payload should work in general (since it still > comes with a 32bit entry point, just switches to long mode really > early). > It's hard to tell what's going on if the entire report is "doesn't work". > > > Regards, > Patrick Georgi > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] 64 UEFI payload boot fail on Denverton platform but 32 UEFI payload works
by Szafranski, MariuszX Sept. 22, 2017

Sept. 22, 2017

Hi, It was tested on Denverton_NS platform using mainly 64bit UEFI payload. 32bit UEFI payload was tested also. Both UEFI payload versions should behave similarly when built from same source code using same coreboot configs. I didn`t noticed difference between 32 and 64 versions. BR, Mariusz From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Melissa Yi Sent: Thursday, September 21, 2017 11:21 AM To: coreboot(a)coreboot.org Subject: [coreboot] 64 UEFI payload boot fail on Denverton platform but 32 UEFI payload works Hi I want to know whether coreboot supports 64bit UEFI payload on denverton platform? Attached the fail log. Thanks. Regards, Melissa Yi -------------------------------------------------------------- Intel Research and Development Ireland Limited Registered in Ireland Registered Office: Collinstown Industrial Park, Leixlip, County Kildare Registered Number: 308263 This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies.

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Re: [coreboot] 64 UEFI payload boot fail on Denverton platform but 32 UEFI payload works
by Patrick Georgi Sept. 22, 2017

Sept. 22, 2017

2017-09-22 3:33 GMT+02:00 Melissa Yi <huayi(a)celestica.com>: > Anyone can give some information? Probably not. 64bit tianocore as payload should work in general (since it still comes with a 32bit entry point, just switches to long mode really early). It's hard to tell what's going on if the entire report is "doesn't work". Regards, Patrick Georgi

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ECC’17: Fund developer travel costs
by Paul Menzel Sept. 22, 2017

Sept. 22, 2017

Dear coreboot folks, The European coreboot conference 2017 is around the corner and starts on October 26th [1]. Are there developers who need funding of their travel costs? Kyösti, Arthur, Patrick, …? Please tell the community and note the amount. Until we know for sure, it’d be great if the coreboot community members would be willing to fund some of these costs. Thanks, Paul [1] https://ecc2017.coreboot.org/

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ASUS KFSN4-DRE Automated Test Failure [master]
by Raptor Engineering Automated Coreboot Test Stand Sept. 22, 2017

Sept. 22, 2017

The ASUS KFSN4-DRE fails verification for branch master as of commit cbe8c58e07d1b52cac75f356edfc1cfcad4171da The following tests failed: BOOT_FAILURE Commits since last successful test: cbe8c58 mb/purism/librem13v2: Remove redundant MAINBOARD_VENDOR setting d681524 AGESA binaryPI: Clean up amdfamXX.h include See attached log for details This message was automatically generated from Raptor Engineering's ASUS KFSN4-DRE test stand Want to test on your own equipment? Check out https://www.raptorengineering.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineering.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineering.com> regarding any issues stemming from this notification

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Re: [coreboot] 64 UEFI payload boot fail on Denverton platform but 32 UEFI payload works
by Melissa Yi Sept. 22, 2017

Sept. 22, 2017

Hi all, Anyone can give some information? Thanks. Regards, Melissa Yi BIOS Lead Engineer Celestica(Shanghai) R&D Center, China www.celestica.com Solid Partners, Flexible Solutions 2017-09-21 17:20 GMT+08:00 Melissa Yi <huayi(a)celestica.com>: > Hi > I want to know whether coreboot supports 64bit UEFI payload on > denverton platform? > Attached the fail log. > > Thanks. > > Regards, > Melissa Yi >

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