On Fri, Sep 15, 2017 at 7:40 PM, Fabian <coreboot(a)bufa.info> wrote:
I try to get coreboot run on my H8SCM. Sadly I get no log over serial or USB. So I want
to give SPI console a try. It seems to be a very new feature introduced here .
Do you have a tested usbdebug setup with some other coreboot mainboard?
Not sure if that works either, but do you have 7-seg POST card for PCI slot?
Currently, for H8SCM, console on usb would start in ramstage.. which
is way too late to be useful for you. It makes things otherwise
unstable, but you can have USBDEBUG_IN_ROMSTAGE=y by modifying
depends on EARLY_CBMEM_INIT << remove
When I compile coreboot it fails with this warning:
warning: (CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS &&
CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CONSOLE_SPI_FLASH) selects
BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY which has unmet direct dependencies (SPI_FLASH
As written in  it's only tested for Skylake. How much effort is necessary to port
it to my board? Are there more Information about SPI console? Or is there an other way to
get log from my board?
SPI master controller (flash write) support has not been implemented
for SB700 southbridge. It's probably a matter of including
cimx/sb800/spi.c in your build (with some PCI ID changes) and adding
"select SPI_FLASH". Then again, once you enable FMAP for SPI console
use, you probably break AGESA build elsewhere.
There are some assumptions left (for AGESA and binaryPI) that CBFS
would cover the complete SPI flash part.