coreboot March 2017

coreboot@coreboot.org

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267 discussions

Reminder: The maiing list vs forum poll closes in just under 24 hours.
by Martin Roth 03 Mar '17

03 Mar '17

As brought up in the previous coreboot community meeting, the coreboot project is discussing the idea of switching from the mailing list to a forum. This idea did not originate with the coreboot leadership, but from a request by members of the community. I know many people have some strong feelings about this one way or the other. Right now we're just collecting data on how people feel about it, and looking for suggestions on ways to either improve the mailing list or set up a well-run forum. Here's the poll about the switch. I will close the poll tomorrow, March 3, 2017. https://goo.gl/9Hd569 Martin

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Re: [coreboot] The ECC 2017 web page
by ron minnich 03 Mar '17

03 Mar '17

osx and chrome. Since I closed the tab, my fan is quiet and my power consumption and cpu usage are back to much less. ron On Thu, Mar 2, 2017 at 9:15 PM Matt DeVillier <matt.devillier(a)gmail.com> wrote: > I'm seeing ~90MB RAM use and low single digit CPU usage here on > Win10/Chrome - what browser/OS you you seeing 25% on? > > On Thu, Mar 2, 2017 at 11:11 PM, ron minnich <rminnich(a)gmail.com> wrote: > > That one web page, while not even visible, eats up 25% of the cpu on one > core of my osx laptop. > > Fan is at high speed. Laptop is hot. > > I realize it's a pretty web page and all, but what makes it do that? Is it > necessary for it to cause such power consumption? We need green web pages > :-) > > thanks > > ron > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot > >

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Re: [coreboot] The ECC 2017 web page
by Matt DeVillier 03 Mar '17

03 Mar '17

I'm seeing ~90MB RAM use and low single digit CPU usage here on Win10/Chrome - what browser/OS you you seeing 25% on? On Thu, Mar 2, 2017 at 11:11 PM, ron minnich <rminnich(a)gmail.com> wrote: > That one web page, while not even visible, eats up 25% of the cpu on one > core of my osx laptop. > > Fan is at high speed. Laptop is hot. > > I realize it's a pretty web page and all, but what makes it do that? Is it > necessary for it to cause such power consumption? We need green web pages > :-) > > thanks > > ron > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

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The ECC 2017 web page
by ron minnich 03 Mar '17

03 Mar '17

That one web page, while not even visible, eats up 25% of the cpu on one core of my osx laptop. Fan is at high speed. Laptop is hot. I realize it's a pretty web page and all, but what makes it do that? Is it necessary for it to cause such power consumption? We need green web pages :-) thanks ron

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coreboot community meeting minutes for March 2, 2017
by Martin Roth 03 Mar '17

03 Mar '17

Here are the meeting minutes of today's coreboot community meeting. Info about the next meeting (March 16) is at the bottom. ################################################################## # Thursday, March 2nd, 2017 General coreboot news & discussions * coreboot was not accepted for GSoC 2017. - Google has updated their policy, so that students can only participate two times. * Next release coreboot 4.6 - Roughly April 15th. An announcement should be made on the mailing list around the time of the next community meeting. - Philipp wants to fix the verified toolchain patch until we do the release. * coreboot granted 'BOOT' ID for ACPI - http://www.uefi.org/ACPI_ID_List?search=boot * Mailing list poll about coreboot switching from the mailing list to a forum: https://goo.gl/9Hd569 - Around 40 answers so far. Poll closes tomorrow - Martin will post results over the weekend. * New coreboot specific payload: cbui - https://www.coreboot.org/pipermail/coreboot/2017-February/083454.html - source: https://github.com/siro20/coreboot/tree/cbui * board status uploads are still only a few boards. How do we improve usage? - Add more documentation - publicize iso used for testing boards - Add option to push commands to the remote system to make it easier to use - Archive old commits to help bring down the size of the repo. Do a shallow checkout to reduce the amount of data downloaded. * Project Management, Transparency and Integration of services. - What's about something like phabricator. Making things easier for us and providing same review features like the gerrit. https://www.phacility.com/ - What's the advantage? Why do we want to tear down all of the existing infrastructure and set up new? Why right now? Who's going to do this? - Integration of the current system could be better, but gerrit is relatively standard, so it might not be good for companies to swith to a new system. - switch to github & gerrithub.io? - Test phabricator on a separate small project before trying to move all of coreboot to it. - Needs to be discussed with coreboot leadership. * Organizational issues. We need more people doing coreboot organizational related stuff. - How do we get more people who are interested in helping with the non-coding aspects of running the project? coreboot Conference news * What is the Future of conferences in the USA regarding traveling restrictions - Martin, Ron, and Stefan discussed moving the conferences outside of the USA for next year. The conclusion that was reached was that doing that would just prevent people inside the USA who couldn't easily return after leaving from going to any conference. * coreboot conference website structure is finished. * ECC17 is online via ecc2017.coreboot.org, dates and locations are clear. * Denver conference page will be forked from ECC17 page and set up this weekend. * ACC17 (American coreboot conference 2017) - Catering set up & Location officially reserved. Infrastructure Issues & News * Enable checkpatch.pl as gate keeper to block non-compliant patches? - Martin feels that this isn't realistic until checkpatch.pl actually passes on the current tree. Can we work towards that? - Add a "lint" flag that isn't a gating item, but can signal that there's an issue which should be looked at. - Clean up the codebase and then enable specific items? - Run on include first and clean that, then work our way up. - Need to exclude vendorcode from being tested. * Documentation project: Will be set up at coreboot.org/docs - Working on that this weekend and upcoming weeks. - We will take the new system live before deleting the old documentation. - Hugo supports markdown, asciidoc, and restructuredtext (ReST) * Updating to new toolchain this weekend. PLEASE TEST YOUR BOARDS. - See this for instructions: https://www.coreboot.org/pipermail/coreboot/2017-January/082883.html - Updated toolchain patch: https://review.coreboot.org/#/c/17189/ Development * We need more people doing review and merging patches that are ready to be pushed into the master. - Looking at adding a couple more submitters to help merge other people's commits Interesting External news items * Chemnitzer Linux days 2017 - https://chemnitzer.linux-tage.de/2017/en - Paul will be giving a presentation on coreboot. If it's recorded, we'll link to it. * Raptor's OpenBMC campaign has been funded to the minimum level. - https://www.raptorengineering.com/coreboot/kgpe-d16-bmc-port-offer.php * http://www.intelsecurity.com/advanced-threat-research/content/data/REConBru… - Security issues, do we have a cve tracker ??? - Philipp can set something up when he has some time. ################################################################## Next meeting is March 16, 2017 Check the coreboot calendar for the time in your timezone: https://www.coreboot.org/calendar.html Join using the bluejeans web app or the phone bridge: https://bluejeans.com/616384323 Phone bridge call in numbers: https://www.bluejeans.com/numbers Meeting ID: 616384323 Current agenda & history: https://coreboot-meeting.pads.ccc.de/CommunityMeetingTopics

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How to improve the boot time of the Asus KGPE-D16?
by Paul Menzel 02 Mar '17

02 Mar '17

Dear coreboot folks, With 128 GB of RAM consisting of eight 16 GB modules, coreboot takes over a minute to get to the payload on the Asus KGPE-D16 even without serial console enabled [1]. This is not much faster than the vendor firmware. Please note that the timings below are incorrect. Comparing it with the timings from SeaBIOS’ `script/read_serial.py`, I’d say the time values need to be multiplied by two. (Somebody mentioned, that the reason might be `cbmem -t` using some scaling factor to convert the time stamps to seconds, and that might be wrong on the board.) ``` $ more asus/kgpe-d16/4.5-1093-g308aeff/2017-03-01T16_03_07Z/coreboot_timestamps.txt 21 entries total: 0:1st timestamp 24,384 1:start of rom stage 25,061 (676) 2:before ram initialization 913,502 (888,441) 3:after ram initialization 35,548,889 (34,635,386) 4:end of romstage 35,642,960 (94,070) 8:starting to load ramstage 35,647,351 (4,391) 15:starting LZMA decompress (ignore for x86) 35,647,872 (520) 16:finished LZMA decompress (ignore for x86) 35,695,864 (47,991) 9:finished loading ramstage 35,696,312 (447) 10:start of ramstage 35,696,893 (581) 30:device enumeration 35,696,897 (3) 40:device configuration 36,639,627 (942,730) 50:device enable 36,644,848 (5,221) 60:device initialization 36,646,012 (1,163) 70:device setup done 37,044,848 (398,836) 75:cbmem post 37,044,850 (1) 80:write tables 37,044,851 (1) 85:finalize chips 37,053,950 (9,099) 90:load payload 37,324,647 (270,697) 15:starting LZMA decompress (ignore for x86) 37,325,042 (395) 16:finished LZMA decompress (ignore for x86) 37,349,321 (24,278) 99:selfboot jump 37,349,328 (7) ``` I think most of the time is spent in RAM initialization. 1. Do board owners with similar amount of memory (independent of the board) have similar numbers? 2. What are the ways to improve that? Is it possible? For example, can the modules be probed in parallel (if that isn’t done already)? Thanks, Paul [1] https://review.coreboot.org/cgit/board-status.git/commit/?id=4b4b7ab5865b15…

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Re: [coreboot] Suggestions on shipping ARMv8 Chromebook
by tturne＠codeaurora.org 02 Mar '17

02 Mar '17

On 2017-02-17 10:10, Patrick Georgi wrote: > The just-released Chromebook Plus comes with an RK3399 SoC, which is > ARMv8 and fully open at the AP firmware level (GPU is Mali with its > usual issues, as well as Wifi firmware). > Thanks for this suggestion, we are in process of purchasing. Do you or anybody on the list know what board name this is known as in the tree? Cheers, T.mike > > Patrick > > 2017-02-17 15:49 GMT+01:00 <tturne(a)codeaurora.org>: >> Folks, >> As we work on our own implementation we are kicking around purchasing >> an >> off-the-shelf ARMv8 Chromebook. >> >> Main requirement is that it has a nice clean software build in the >> chrome/coreboot trees. >> Prefer no binary blobs, but that is merely a preference. >> >> Does the community have any suggestions? >> Cheers, >> T.mike >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Some errors by compiling romstage (I am a newbie)
by Aaron Durbin 02 Mar '17

02 Mar '17

On Thu, Mar 2, 2017 at 8:33 AM, Maxim Gusev <mail(a)maximgusev.com> wrote: > Hello, Aaron! > > I am compiling sourses of my arch e2k. > I have compiled bootblock with my sources. There aren't my sources in other > stages. I have create arch directory and mainboard directory where the > sources are located. > > > > Log: > > /home/maxim/coreboot/util/crossgcc/xgcc/bin/linux-ld: warning: cannot find > entry symbol start; defaulting to 0000000100187000 > build/romstage/lib/imd_cbmem.o: In function `cbmem_add_bootmem': > /home/maxim/coreboot/src/lib/imd_cbmem.c:287: undefined reference to > `bootmem_add_range' > build/romstage/lib/imd_cbmem.o: In function `cbmem_add_records_to_cbtable': > /home/maxim/coreboot/src/lib/imd_cbmem.c:314: undefined reference to > `lb_new_record' > make: *** [build/cbfs/fallback/romstage.debug] Error 1 > Does your arch's compiler support -ffuncation-sections and -fdata-sections? As well as your linker supporting --gc-sections ? All the architectures we support have those flags. See Makefile.inc which provides those in CFLAGS_common and LDFLAGS_common. That support allows us to not sprinkle #ifdef's all around in the code when the same source file is compiled for different stages. > > > -------- Original Message -------- > Subject: Re: [coreboot] Some errors by compiling romstage (I am a newbie) > Local Time: 2 Марта 2017 г. 5:22 вечера > UTC Time: 2 Марта 2017 г. 14:22 > From: adurbin(a)google.com > To: Maxim Gusev <mail(a)maximgusev.com> > coreboot(a)coreboot.org <coreboot(a)coreboot.org> > > On Thu, Mar 2, 2017 at 7:24 AM, Maxim Gusev via coreboot > <coreboot(a)coreboot.org> wrote: >> Hi everbody! >> >> I have a question. Very hope for your help. >> >> When I am compiling the romstage there are 2 errors by the linker: >> Undefined refference to 'bootmem_add_range' >> Undefined refference to 'lb_new_record' in the imd_cbmem.c file (it is >> included in src/lib/Makefile.inc romstage). >> >> The definitions of these functions are in lib/bootmem.c and >> lib/coreboot_table.c accordingly. >> But I can't see the inclusion of these files in romstage in >> src/Makefile.inc >> (only in ramstage): >> ramstage-y += bootmem.c >> ramstage-y += coreboot_table.c >> >> How to solve this problem? >> The inclusion of these files produces a number of other errors, but >> nowhere >> in the code no one does it? Why only I am having this error. > > > What board are you building? Are you working on local patches to your > setup only? What does the build log indicate? > >> >> In General, I don't even need these stages (romstage and ramstage) - I >> want >> to check the performance on real hardware the work of the bootblock, but >> the >> toolchain requires me to compile other stages. And the error occurs even >> not >> in my code, but my ignorance. >> >> Thanks a lot! >> Regards, Maxim >> >> >> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot > >

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Re: [coreboot] Some errors by compiling romstage (I am a newbie)
by Maxim Gusev 02 Mar '17

02 Mar '17

Hello, Aaron! I am compiling sourses of my arch e2k. I have compiled bootblock with my sources. There aren't my sources in other stages. I have create arch directory and mainboard directory where the sources are located. Log: /home/maxim/coreboot/util/crossgcc/xgcc/bin/linux-ld: warning: cannot find entry symbol start; defaulting to 0000000100187000 build/romstage/lib/imd_cbmem.o: In function `cbmem_add_bootmem': /home/maxim/coreboot/src/lib/imd_cbmem.c:287: undefined reference to `bootmem_add_range' build/romstage/lib/imd_cbmem.o: In function `cbmem_add_records_to_cbtable': /home/maxim/coreboot/src/lib/imd_cbmem.c:314: undefined reference to `lb_new_record' make: *** [build/cbfs/fallback/romstage.debug] Error 1 -------- Original Message -------- Subject: Re: [coreboot] Some errors by compiling romstage (I am a newbie) Local Time: 2 Марта 2017 г. 5:22 вечера UTC Time: 2 Марта 2017 г. 14:22 From: adurbin(a)google.com To: Maxim Gusev <mail(a)maximgusev.com> coreboot(a)coreboot.org <coreboot(a)coreboot.org> On Thu, Mar 2, 2017 at 7:24 AM, Maxim Gusev via coreboot <coreboot(a)coreboot.org> wrote: > Hi everbody! > > I have a question. Very hope for your help. > > When I am compiling the romstage there are 2 errors by the linker: > Undefined refference to 'bootmem_add_range' > Undefined refference to 'lb_new_record' in the imd_cbmem.c file (it is > included in src/lib/Makefile.inc romstage). > > The definitions of these functions are in lib/bootmem.c and > lib/coreboot_table.c accordingly. > But I can't see the inclusion of these files in romstage in src/Makefile.inc > (only in ramstage): > ramstage-y += bootmem.c > ramstage-y += coreboot_table.c > > How to solve this problem? > The inclusion of these files produces a number of other errors, but nowhere > in the code no one does it? Why only I am having this error. What board are you building? Are you working on local patches to your setup only? What does the build log indicate? > > In General, I don't even need these stages (romstage and ramstage) - I want > to check the performance on real hardware the work of the bootblock, but the > toolchain requires me to compile other stages. And the error occurs even not > in my code, but my ignorance. > > Thanks a lot! > Regards, Maxim > > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Some errors by compiling romstage (I am a newbie)
by Aaron Durbin 02 Mar '17

02 Mar '17

On Thu, Mar 2, 2017 at 7:24 AM, Maxim Gusev via coreboot <coreboot(a)coreboot.org> wrote: > Hi everbody! > > I have a question. Very hope for your help. > > When I am compiling the romstage there are 2 errors by the linker: > Undefined refference to 'bootmem_add_range' > Undefined refference to 'lb_new_record' in the imd_cbmem.c file (it is > included in src/lib/Makefile.inc romstage). > > The definitions of these functions are in lib/bootmem.c and > lib/coreboot_table.c accordingly. > But I can't see the inclusion of these files in romstage in src/Makefile.inc > (only in ramstage): > ramstage-y += bootmem.c > ramstage-y += coreboot_table.c > > How to solve this problem? > The inclusion of these files produces a number of other errors, but nowhere > in the code no one does it? Why only I am having this error. What board are you building? Are you working on local patches to your setup only? What does the build log indicate? > > In General, I don't even need these stages (romstage and ramstage) - I want > to check the performance on real hardware the work of the bootblock, but the > toolchain requires me to compile other stages. And the error occurs even not > in my code, but my ignorance. > > Thanks a lot! > Regards, Maxim > > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot

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coreboot March 2017