coreboot March 2017

coreboot@coreboot.org

79 participants
267 discussions

Re: [coreboot] Where to get ME image/flash descriptors for the x220?
by cb＠imap.cc 05 Mar '17

05 Mar '17

There's a lot of useful info here relating to X230 ECs, which may help. Mostly applicable to the X220 too. https://github.com/hamishcoleman/thinkpad-ec On Sun, 5 Mar 2017, at 14:31, qma ster wrote: > It should be possible to reflash EC internal firmware through a > keyboard port, - or maybe through some other debug port that may or > may not be soldered by default... For example, here is a guide that > describes how to reflash EC KB9012 internal firmware on Lenovo G505S - > "AMD based laptop that is supported by coreboot project" , > http://dangerousprototypes.com/docs/Flashing_KB9012_with_Bus_Pirate . > Thanks to this method it is possible to flash a completely clean EC > KB9012 firmware image, which: 1) does not contain any "secret configs" > (could be stored in the free place after the firmware) 2) does not > contain any serial numbers or other specific laptop information ... > For any EC it is guaranteed that it IS possible to reflash a firmware > through In-System Programming (direct flashing) - otherwise, 1) how > the manufacturers flash EC for the first time? ;) 2) if some laptop's > EC is burned, how do repair shops flash a firmware to a new > replacement EC? > Sadly, for this direct flashing method you may need to buy a > proprietary programmer (closed source hardware/software) , because a > flashrom does not support every EC in existence > > 2017-03-05 13:20 GMT+03:00 Arthur Heymans <arthur(a)aheymans.xyz>: >> "Taiidan(a)gmx.com" <Taiidan(a)gmx.com> writes: >> >> > Well I managed to download the latest BIOS from the lenovo site, >> > which includes an ME update now the issue is that I can't seem to >> > figure out how to extract it from the .FL1 and .FL2 files. >> > >> Those might have a length too long to fit a flash so you need to trim >> those down before using ifdtool on those (If they contain and ifd of >> course) >> so depending on size of rom >> dd if=FL1(or 2)file of=vendor_bios.rom bs=1 count=xM >> >> and then ifdtool -x vendor_bios.rom >> >> > I would also like to know as to how I can re-flash the EC firmware >> > if that could potentially cause problems, I of course do not know >> > if it has DMA. >> > >> >> Only existing tool to flash EC is using vendor tool. >> EC are only accessed trough port mapped IO (or on newer ones >> also via >> memory mapped IO). EC itself does not have DMA afaik. >> >> -- >> Arthur Heymans >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot

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Flash second/dual bios chip on Gigabyte G41M-ES2L without external flasher possible?
by i1w5d7gf38keg＠tutanota.com 05 Mar '17

05 Mar '17

Is it possible to flash the second flash chip on the Gigabyte G41M-ES2L mainboard without external flasher?

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Re: [coreboot] Reminder: The maiing list vs forum poll closes in just under 24 hours.
by i1w5d7gf38keg＠tutanota.com 04 Mar '17

04 Mar '17

I would also really prefer a non-google poll. Taiidan wrote "I also do not like contributing to machine learning or advertising databases." You wrote "If people want to just email me responses, I can fill them into the form on their behalf." Thats exactly what he didnt want. He didnt want to feed skynet. Of course he also didnt want that you feed it for him with the data he provide to anyone. Would be really great if some free software running on the coreboot servers is been used for coreboot polls. 3. Mar 2017 20:27 by gaumless(a)gmail.com: > Hey Talidan,> If someone wants to suggest a different site for doing polls, I'd be glad to take a look, but I'm probably not going to change away from Google forms unless we find something comparable. It's easy to make the forms, easy to take the poll, and easy to collect, analyze, and view the data. > As a compromise, for future polls that I send out, I can send out a list of the questions out to the mailing list as well. If people want to just email me responses, I can fill them into the form on their behalf. That way you don't have to deal with the site, but we can still use something that's easy to work with. > Would that work for you? > Martin > On Fri, Mar 3, 2017 at 3:03 AM, > Taiidan(a)gmx.com> <> Taiidan(a)gmx.com> > wrote: > >> On 03/03/2017 01:45 AM, Martin Roth wrote: >> >> >>> As brought up in the previous coreboot community meeting, the coreboot project >>> is discussing the idea of switching from the mailing list to a forum. This >>> idea did not originate with the coreboot leadership, but from a request by >>> members of the community. >>> >>> I know many people have some strong feelings about this one way or the >>> other. Right now we're just collecting data on how people feel about it, >>> and looking for suggestions on ways to either improve the mailing list or >>> set up a well-run forum. >>> >>> Here's the poll about the switch. I will close the poll tomorrow, >>> March 3, 2017. >>> >>> https://goo.gl/9Hd569 >>> >>> Martin >>> >>> >> Thank you for reminding me. >> >> For future reference I would really prefer a non-google poll - the use of google services requires javascript and I don't like enabling javascript due to how easily exploitable it is. I also do not like contributing to machine learning or advertising databases. >> >> As I have said before, most forum software discriminates against people who do not wish to run a window manager and of course javascript which is why I think things are fine as they are. >> > >

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Re: [coreboot] call on AMD to release src+specs+datasheets for ryzen
by Leah Rowe 04 Mar '17

04 Mar '17

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Hi Ron, On 03/03/17 23:26, ron minnich wrote: > We could target putting a meeting with AMD together at the Denver > meeting or the one in the fall. ron Yes, this is what I'm banking on. If coreboot can arrange that, and get AMD in its meetings then that would be great. That, plus raising public awareness and showing demand from the public. That's what I'm trying to do here, but we need people in coreboot to help out since coreboot has better relations with AMD that libreboot does. - -- Leah Rowe Libreboot developer Use free software. Free as in freedom. https://en.wikipedia.org/wiki/Free_software Use a free operating system, GNU+Linux. https://libreboot.org/docs/distros/ Or BSD: https://libreboot.org/docs/bsd/ Use a free BIOS. https://libreboot.org/ Support computer user freedom. https://peers.community/ Minifree Ltd, trading as Ministry of Freedom | Registered in England, No. 9361826 | VAT No. GB202190462 Registered Office: 19 Hilton Road, Canvey Island, Essex SS8 9QA, UK | Web: https://minifree.org/ -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEE+JRrnG26iGmvPhSA/0W3TPnRz5QFAli6IjMACgkQ/0W3TPnR z5Tt8wf+KjSBw+Ghkq4szfcafAhlhhctrZQaMdVq8of4kK/dgDTqIuTHTzyad7Ab VFRsBeiEHRQGqp57EUZkfc5zKAdxuSZcSQvZx8bGpnSUnej83IXQytA7YurTpvBo aEInxqgh8m27QBFgu71OJvnZPP8TuN9qbTlZIHkRWr5uxR73OwmbubqUOaf4MHw5 yPMSMWj3qEAstKiKJy/xrc9RyaiGqGJi+sO5HIUQM6N24QGTWdMu1cLKya5ilnWd GCoWT53AsD2cammg5bNamOPoCqvhsMxUbMOLGsp9q+vlkstBkpgP7JzAFdq8BHjB GIDPrbtFOAt58y/b6HvDnblKRcyfJQ== =ajuw -----END PGP SIGNATURE-----

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coreboot only takes 260 ms on Lenovo 430s!
by Paul Menzel 03 Mar '17

03 Mar '17

Dear coreboot folks, Kamyl pushed the board status for the Lenovo 430s, and I am excited looking at the time stamps! Gone in 260 ms! Awesome. (RAM training results are cached.) ``` $ more lenovo/t430s/4.5-1105-gd55ea7b/2017-03-03T18_41_49Z/coreboot_timestamps.txt 21 entries total: 0:1st timestamp 1,809 1:start of rom stage 59,610 (57,800) 2:before ram initialization 60,859 (1,249) 3:after ram initialization 74,194 (13,334) 4:end of romstage 75,740 (1,546) 8:starting to load ramstage 77,081 (1,341) 15:starting LZMA decompress (ignore for x86) 77,298 (216) 16:finished LZMA decompress (ignore for x86) 94,003 (16,704) 9:finished loading ramstage 94,214 (211) 10:start of ramstage 94,296 (82) 30:device enumeration 94,299 (3) 40:device configuration 98,818 (4,519) 50:device enable 100,528 (1,710) 60:device initialization 100,661 (133) 70:device setup done 223,845 (123,183) 75:cbmem post 223,846 (1) 80:write tables 223,847 (1) 85:finalize chips 245,080 (21,232) 90:load payload 245,081 (1) 15:starting LZMA decompress (ignore for x86) 245,192 (110) 16:finished LZMA decompress (ignore for x86) 262,007 (16,815) 99:selfboot jump 262,024 (17) Total Time: 260,208 ``` So a big thank you to everyone involved in making that possible. phcoder, the Googlers, siro, lynxis, and many, many more. This is great work! Thanks, Paul PS: Even the SMBIOS tables contain the embedded controller strings, which takes over 100 ms on the Lenovo X60 for example. ``` thinkpad_acpi: ThinkPad BIOS CBET4000 4.5-1105-gd55ea7b, EC G7HT29WW-3.22 ``` [1] https://review.coreboot.org/cgit/board-status.git/commit/?id=a2a34b4c7

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Re: [coreboot] How to improve the boot time of the Asus KGPE-D16?
by Daniel Kulesz 03 Mar '17

03 Mar '17

Hi Paul, > > I think most of the time is spent in RAM initialization. > > 1. Do board owners with similar amount of memory (independent of the > board) have similar numbers? > 2. What are the ways to improve that? Is it possible? For example, can > the modules be probed in parallel (if that isn?t done already)? > Regarding 1: I am running 128GB in 8GB modules (LRDIMMs) and experiencing a similar issue. With just two UDIMMs, the boot times are *much* faster. Also, the vendor BIOS is faster from the time you press the poweron button to the time the monitor gets a signal. Cheers, Daniel

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Re: [coreboot] Reminder: The maiing list vs forum poll closes in just under 24 hours.
by Taiidan＠gmx.com 03 Mar '17

03 Mar '17

On 03/03/2017 01:45 AM, Martin Roth wrote: > As brought up in the previous coreboot community meeting, the coreboot project > is discussing the idea of switching from the mailing list to a forum. This > idea did not originate with the coreboot leadership, but from a request by > members of the community. > > I know many people have some strong feelings about this one way or the > other. Right now we're just collecting data on how people feel about it, > and looking for suggestions on ways to either improve the mailing list or > set up a well-run forum. > > Here's the poll about the switch. I will close the poll tomorrow, > March 3, 2017. > > https://goo.gl/9Hd569 > > Martin > Thank you for reminding me. For future reference I would really prefer a non-google poll - the use of google services requires javascript and I don't like enabling javascript due to how easily exploitable it is. I also do not like contributing to machine learning or advertising databases. As I have said before, most forum software discriminates against people who do not wish to run a window manager and of course javascript which is why I think things are fine as they are.

2 1

Re: [coreboot] Reminder: The maiing list vs forum poll closes in just under 24 hours.
by Martin Roth 03 Mar '17

03 Mar '17

I don't want to skew the poll by releasing the data before it closes. Martin On Fri, Mar 3, 2017 at 12:22 AM, Zoran Stojsavljevic < zoran.stojsavljevic(a)gmail.com> wrote: > Hello Martin, > > The current/up to date poll results would be also nice to have... I > guess, I am asking for too much, don't I? ;-) > > (anyway, it is too late) > > Zoran > _______ > > On 3/3/17, Martin Roth <gaumless(a)gmail.com> wrote: > > As brought up in the previous coreboot community meeting, the coreboot > > project > > is discussing the idea of switching from the mailing list to a forum. > This > > idea did not originate with the coreboot leadership, but from a request > by > > members of the community. > > > > I know many people have some strong feelings about this one way or the > > other. Right now we're just collecting data on how people feel about it, > > and looking for suggestions on ways to either improve the mailing list or > > set up a well-run forum. > > > > Here's the poll about the switch. I will close the poll tomorrow, > > March 3, 2017. > > > > https://goo.gl/9Hd569 > > > > Martin > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > https://www.coreboot.org/mailman/listinfo/coreboot > > >

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Re: [coreboot] Some errors by compiling romstage (I am a newbie)
by Aaron Durbin 03 Mar '17

03 Mar '17

On Fri, Mar 3, 2017 at 11:23 AM, Maxim Gusev <mail(a)maximgusev.com> wrote: > Yes, Aaron. I tried to figure it all out. > Some option doesn't works correctly. But the compiler and the linker are > supporting these options. > There is a log of "readelf -e imd_cbmem.o": http://pastebin.com/G5y36uU4 The above is indicating that -ffunction-sections and -fdata-sections is not working. All your symbols are in .text and .data so when you attempt to link it'll try to pull in everything which is why you are a getting the link error. > I also have a warning: cannot find entry symbol start; defaulting to > 0000000100187000 before undefined refference errors (but I think it doesn't > affect). > > I have also tried to compile the simple code by gcc: > http://pastebin.com/AYnxTjZx (the compilation string, code and the readelf > log). > I'm not doing something wrong, because I don't see sections with the name of > the function. There is the same with my compiler. > Maybe these options work only in conjunction with others? No. They work on all of our supported architectures as standalone options. > > If I will compile some sources of supported mainboard by coreboot, the > readelf log and sections will be good with appropriate title > (.text.function). > > Thanks a lot! > Regards, Maxim > > > > -------- Original Message -------- > Subject: Re: [coreboot] Some errors by compiling romstage (I am a newbie) > Local Time: 3 Марта 2017 г. 5:54 вечера > UTC Time: 3 Марта 2017 г. 14:54 > From: adurbin(a)google.com > To: Maxim Gusev <mail(a)maximgusev.com>, Coreboot <coreboot(a)coreboot.org> > > On Fri, Mar 3, 2017 at 8:37 AM, Maxim Gusev <mail(a)maximgusev.com> wrote: >> It doesn't work any case. >> As I understood these options remove the unreferenced symbols, but I have >> referenced symbols (the error is undefined reference). >> The definition of the used functions is in the file that is missing at >> this >> stage but all works on other archs. >> > > The symbol might be referenced in one function in that compilation > unit, but if the symbol of the function using the undefined symbols is > not referenced from any of the root symbols then it should be removed. > The fact that it isn't suggests -gc-sections isn't working *or* > -f(data|function)-sections isn't working. As I requested previously, > readelf -e from one of the romstage .o files would confirm the latter. > As it stands now I can't speculate as to what is happening because the > code you are working on isn't published so I can't do anything beyond > request the information I've already requested. > >> >> >> -------- Original Message -------- >> Subject: Re: [coreboot] Some errors by compiling romstage (I am a newbie) >> Local Time: 3 Марта 2017 г. 4:54 дня >> UTC Time: 3 Марта 2017 г. 13:54 >> From: adurbin(a)google.com >> To: Maxim Gusev <mail(a)maximgusev.com>, Coreboot <coreboot(a)coreboot.org> >> >> On Fri, Mar 3, 2017 at 6:41 AM, Maxim Gusev <mail(a)maximgusev.com> wrote: >>> These options are supported. >>> But the option -fno-pie is not supported (Don’t produce a position >>> independent executable). >>> Is it the reason of the fault? >> >> >> I wouldn't think so. If you remove that option does it magically work? >> From the errors you showed -gc-sections along with -fdata-sections and >> -ffunction-sections would have removed the unreferenced symbols and >> not cause a link error. To prove that -f(data|function)-sections are >> working can you provide the readelf -e output from an intermediate .o >> file you compiled for romstage? >> >>> >>> >>> >>> -------- Original Message -------- >>> Subject: Re: [coreboot] Some errors by compiling romstage (I am a newbie) >>> Local Time: 2 Марта 2017 г. 6:01 вечера >>> UTC Time: 2 Марта 2017 г. 15:01 >>> From: adurbin(a)google.com >>> To: Maxim Gusev <mail(a)maximgusev.com> >>> coreboot(a)coreboot.org <coreboot(a)coreboot.org> >>> >>> On Thu, Mar 2, 2017 at 8:33 AM, Maxim Gusev <mail(a)maximgusev.com> wrote: >>>> Hello, Aaron! >>>> >>>> I am compiling sourses of my arch e2k. >>>> I have compiled bootblock with my sources. There aren't my sources in >>>> other >>>> stages. I have create arch directory and mainboard directory where the >>>> sources are located. >>>> >>>> >>>> >>>> Log: >>>> >>>> /home/maxim/coreboot/util/crossgcc/xgcc/bin/linux-ld: warning: cannot >>>> find >>>> entry symbol start; defaulting to 0000000100187000 >>>> build/romstage/lib/imd_cbmem.o: In function `cbmem_add_bootmem': >>>> /home/maxim/coreboot/src/lib/imd_cbmem.c:287: undefined reference to >>>> `bootmem_add_range' >>>> build/romstage/lib/imd_cbmem.o: In function >>>> `cbmem_add_records_to_cbtable': >>>> /home/maxim/coreboot/src/lib/imd_cbmem.c:314: undefined reference to >>>> `lb_new_record' >>>> make: *** [build/cbfs/fallback/romstage.debug] Error 1 >>>> >>> >>> Does your arch's compiler support -ffuncation-sections and >>> -fdata-sections? As well as your linker supporting --gc-sections ? All >>> the architectures we support have those flags. See Makefile.inc which >>> provides those in CFLAGS_common and LDFLAGS_common. That support >>> allows us to not sprinkle #ifdef's all around in the code when the >>> same source file is compiled for different stages. >>> >>>> >>>> >>>> -------- Original Message -------- >>>> Subject: Re: [coreboot] Some errors by compiling romstage (I am a >>>> newbie) >>>> Local Time: 2 Марта 2017 г. 5:22 вечера >>>> UTC Time: 2 Марта 2017 г. 14:22 >>>> From: adurbin(a)google.com >>>> To: Maxim Gusev <mail(a)maximgusev.com> >>>> coreboot(a)coreboot.org <coreboot(a)coreboot.org> >>>> >>>> On Thu, Mar 2, 2017 at 7:24 AM, Maxim Gusev via coreboot >>>> <coreboot(a)coreboot.org> wrote: >>>>> Hi everbody! >>>>> >>>>> I have a question. Very hope for your help. >>>>> >>>>> When I am compiling the romstage there are 2 errors by the linker: >>>>> Undefined refference to 'bootmem_add_range' >>>>> Undefined refference to 'lb_new_record' in the imd_cbmem.c file (it is >>>>> included in src/lib/Makefile.inc romstage). >>>>> >>>>> The definitions of these functions are in lib/bootmem.c and >>>>> lib/coreboot_table.c accordingly. >>>>> But I can't see the inclusion of these files in romstage in >>>>> src/Makefile.inc >>>>> (only in ramstage): >>>>> ramstage-y += bootmem.c >>>>> ramstage-y += coreboot_table.c >>>>> >>>>> How to solve this problem? >>>>> The inclusion of these files produces a number of other errors, but >>>>> nowhere >>>>> in the code no one does it? Why only I am having this error. >>>> >>>> >>>> What board are you building? Are you working on local patches to your >>>> setup only? What does the build log indicate? >>>> >>>>> >>>>> In General, I don't even need these stages (romstage and ramstage) - I >>>>> want >>>>> to check the performance on real hardware the work of the bootblock, >>>>> but >>>>> the >>>>> toolchain requires me to compile other stages. And the error occurs >>>>> even >>>>> not >>>>> in my code, but my ignorance. >>>>> >>>>> Thanks a lot! >>>>> Regards, Maxim >>>>> >>>>> >>>>> >>>>> >>>>> -- >>>>> coreboot mailing list: coreboot(a)coreboot.org >>>>> https://www.coreboot.org/mailman/listinfo/coreboot >>>> >>>> >>> >>> >> >> > >

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Re: [coreboot] Some errors by compiling romstage (I am a newbie)
by Maxim Gusev 03 Mar '17

03 Mar '17

Yes, Aaron. I tried to figure it all out. Some option doesn't works correctly. But the compiler and the linker are supporting these options. There is a log of "readelf -e imd_cbmem.o": http://pastebin.com/G5y36uU4 I also have a warning: cannot find entry symbol start; defaulting to 0000000100187000 before undefined refference errors (but I think it doesn't affect). I have also tried to compile the simple code by gcc: http://pastebin.com/AYnxTjZx (the compilation string, code and the readelf log). I'm not doing something wrong, because I don't see sections with the name of the function. There is the same with my compiler. Maybe these options work only in conjunction with others? If I will compile some sources of supported mainboard by coreboot, the readelf log and sections will be good with appropriate title (.text.function). Thanks a lot! Regards, Maxim -------- Original Message -------- Subject: Re: [coreboot] Some errors by compiling romstage (I am a newbie) Local Time: 3 Марта 2017 г. 5:54 вечера UTC Time: 3 Марта 2017 г. 14:54 From: adurbin(a)google.com To: Maxim Gusev <mail(a)maximgusev.com>, Coreboot <coreboot(a)coreboot.org> On Fri, Mar 3, 2017 at 8:37 AM, Maxim Gusev <mail(a)maximgusev.com> wrote: > It doesn't work any case. > As I understood these options remove the unreferenced symbols, but I have > referenced symbols (the error is undefined reference). > The definition of the used functions is in the file that is missing at this > stage but all works on other archs. > The symbol might be referenced in one function in that compilation unit, but if the symbol of the function using the undefined symbols is not referenced from any of the root symbols then it should be removed. The fact that it isn't suggests -gc-sections isn't working *or* -f(data|function)-sections isn't working. As I requested previously, readelf -e from one of the romstage .o files would confirm the latter. As it stands now I can't speculate as to what is happening because the code you are working on isn't published so I can't do anything beyond request the information I've already requested. > > > -------- Original Message -------- > Subject: Re: [coreboot] Some errors by compiling romstage (I am a newbie) > Local Time: 3 Марта 2017 г. 4:54 дня > UTC Time: 3 Марта 2017 г. 13:54 > From: adurbin(a)google.com > To: Maxim Gusev <mail(a)maximgusev.com>, Coreboot <coreboot(a)coreboot.org> > > On Fri, Mar 3, 2017 at 6:41 AM, Maxim Gusev <mail(a)maximgusev.com> wrote: >> These options are supported. >> But the option -fno-pie is not supported (Don’t produce a position >> independent executable). >> Is it the reason of the fault? > > > I wouldn't think so. If you remove that option does it magically work? > From the errors you showed -gc-sections along with -fdata-sections and > -ffunction-sections would have removed the unreferenced symbols and > not cause a link error. To prove that -f(data|function)-sections are > working can you provide the readelf -e output from an intermediate .o > file you compiled for romstage? > >> >> >> >> -------- Original Message -------- >> Subject: Re: [coreboot] Some errors by compiling romstage (I am a newbie) >> Local Time: 2 Марта 2017 г. 6:01 вечера >> UTC Time: 2 Марта 2017 г. 15:01 >> From: adurbin(a)google.com >> To: Maxim Gusev <mail(a)maximgusev.com> >> coreboot(a)coreboot.org <coreboot(a)coreboot.org> >> >> On Thu, Mar 2, 2017 at 8:33 AM, Maxim Gusev <mail(a)maximgusev.com> wrote: >>> Hello, Aaron! >>> >>> I am compiling sourses of my arch e2k. >>> I have compiled bootblock with my sources. There aren't my sources in >>> other >>> stages. I have create arch directory and mainboard directory where the >>> sources are located. >>> >>> >>> >>> Log: >>> >>> /home/maxim/coreboot/util/crossgcc/xgcc/bin/linux-ld: warning: cannot >>> find >>> entry symbol start; defaulting to 0000000100187000 >>> build/romstage/lib/imd_cbmem.o: In function `cbmem_add_bootmem': >>> /home/maxim/coreboot/src/lib/imd_cbmem.c:287: undefined reference to >>> `bootmem_add_range' >>> build/romstage/lib/imd_cbmem.o: In function >>> `cbmem_add_records_to_cbtable': >>> /home/maxim/coreboot/src/lib/imd_cbmem.c:314: undefined reference to >>> `lb_new_record' >>> make: *** [build/cbfs/fallback/romstage.debug] Error 1 >>> >> >> Does your arch's compiler support -ffuncation-sections and >> -fdata-sections? As well as your linker supporting --gc-sections ? All >> the architectures we support have those flags. See Makefile.inc which >> provides those in CFLAGS_common and LDFLAGS_common. That support >> allows us to not sprinkle #ifdef's all around in the code when the >> same source file is compiled for different stages. >> >>> >>> >>> -------- Original Message -------- >>> Subject: Re: [coreboot] Some errors by compiling romstage (I am a newbie) >>> Local Time: 2 Марта 2017 г. 5:22 вечера >>> UTC Time: 2 Марта 2017 г. 14:22 >>> From: adurbin(a)google.com >>> To: Maxim Gusev <mail(a)maximgusev.com> >>> coreboot(a)coreboot.org <coreboot(a)coreboot.org> >>> >>> On Thu, Mar 2, 2017 at 7:24 AM, Maxim Gusev via coreboot >>> <coreboot(a)coreboot.org> wrote: >>>> Hi everbody! >>>> >>>> I have a question. Very hope for your help. >>>> >>>> When I am compiling the romstage there are 2 errors by the linker: >>>> Undefined refference to 'bootmem_add_range' >>>> Undefined refference to 'lb_new_record' in the imd_cbmem.c file (it is >>>> included in src/lib/Makefile.inc romstage). >>>> >>>> The definitions of these functions are in lib/bootmem.c and >>>> lib/coreboot_table.c accordingly. >>>> But I can't see the inclusion of these files in romstage in >>>> src/Makefile.inc >>>> (only in ramstage): >>>> ramstage-y += bootmem.c >>>> ramstage-y += coreboot_table.c >>>> >>>> How to solve this problem? >>>> The inclusion of these files produces a number of other errors, but >>>> nowhere >>>> in the code no one does it? Why only I am having this error. >>> >>> >>> What board are you building? Are you working on local patches to your >>> setup only? What does the build log indicate? >>> >>>> >>>> In General, I don't even need these stages (romstage and ramstage) - I >>>> want >>>> to check the performance on real hardware the work of the bootblock, but >>>> the >>>> toolchain requires me to compile other stages. And the error occurs even >>>> not >>>> in my code, but my ignorance. >>>> >>>> Thanks a lot! >>>> Regards, Maxim >>>> >>>> >>>> >>>> >>>> -- >>>> coreboot mailing list: coreboot(a)coreboot.org >>>> https://www.coreboot.org/mailman/listinfo/coreboot >>> >>> >> >> > >

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coreboot March 2017