coreboot March 2017

coreboot@coreboot.org

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PCI BAR attacks on SMM at RECon Brussels
by Trammell Hudson 03 Mar '17

03 Mar '17

Intel ATR presented "Baring the system: New vulnerabilities in SMM of coreboot and UEFI based systems" at RECon Brussels last month: https://recon.cx/2017/brussels/talks/baring_the_system.html The slides are online now: http://www.intelsecurity.com/advanced-threat-research/content/data/REConBru… Their first conclusion is that "the root cause is that firmware assumes hardware is trusted". This seems to be less and less of a valid assumption. -- Trammell

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Inteal Leafhill : Linux SATA driver fails when used with coreboot+grub
by Gailu Singh 03 Mar '17

03 Mar '17

Hi Experts, I am trying to boot Linux 4.1 with coreboot and grub but SATA drive fails with error "ata1: SATA link down (SStatus 4 SControl 300)". It is interesting that GRUB2 can use the SATA drive without issue and able to load kernel from SATA disk. If I use same SATA Drive with Coreboot+UEFI payload then Linux driver just works fine and I am able to boot linux. Any Idea What might be going wrong with Linux Driver. Does it expect something from BIOS/Coreboot that is not fulfilled Linux boot logs: --------------------- Initializing cgroup subsys cpuset Initializing cgroup subsys cpu Initializing cgroup subsys cpuacct Linux version 4.1.21-WR8.0.0.11_standard (vgahlaut@ubuntu) (gcc version 5.2.0 (Wind River Linux 5.2.0-8.0-intel-apollolake-i-64) ) #1 SMP PREEMPT Mon Feb 6 18:38:46 PST 2017 Command line: BOOT_IMAGE=(ahci0,msdos1)/boot/bzImage root=/dev/sda1 rootdelay=10 console=ttyS2,115200 KERNEL supported cpus: Intel GenuineIntel AMD AuthenticAMD Centaur CentaurHauls e820: BIOS-provided physical RAM map: BIOS-e820: [mem 0x0000000000000000-0x0000000000000fff] type 16 BIOS-e820: [mem 0x0000000000001000-0x000000000009ffff] usable BIOS-e820: [mem 0x00000000000a0000-0x00000000000fffff] reserved BIOS-e820: [mem 0x0000000000100000-0x000000000fffffff] usable BIOS-e820: [mem 0x0000000010000000-0x0000000012150fff] reserved BIOS-e820: [mem 0x0000000012151000-0x000000007a64ffff] usable BIOS-e820: [mem 0x000000007a650000-0x000000007affffff] type 16 BIOS-e820: [mem 0x000000007b000000-0x000000007fffffff] reserved BIOS-e820: [mem 0x00000000d0000000-0x00000000ffffffff] reserved BIOS-e820: [mem 0x0000000100000000-0x000000017fffffff] usable NX (Execute Disable) protection: active SMBIOS 2.7 present. e820: last_pfn = 0x180000 max_arch_pfn = 0x400000000 PAT configuration [0-7]: WB WC UC- UC WB WC UC- UC e820: last_pfn = 0x7a650 max_arch_pfn = 0x400000000 Scanning 1 areas for low memory corruption Using GB pages for direct mapping init_memory_mapping: [mem 0x00000000-0x000fffff] init_memory_mapping: [mem 0x17fe00000-0x17fffffff] init_memory_mapping: [mem 0x160000000-0x17fdfffff] init_memory_mapping: [mem 0x00100000-0x0fffffff] init_memory_mapping: [mem 0x12151000-0x7a64ffff] init_memory_mapping: [mem 0x100000000-0x15fffffff] ACPI: Early table checksum verification disabled ACPI: RSDP 0x00000000000F0000 000024 (v02 CORE ) ACPI: XSDT 0x000000007A6690E0 00005C (v01 CORE COREBOOT 00000000 CORE 00000000) ACPI: FACP 0x000000007A66BA60 00010C (v05 CORE COREBOOT 00000000 CORE 00000001) ACPI BIOS Warning (bug): 32/64X length mismatch in FADT/Pm1aEventBlock: 32/16 (20150410/tbfadt-623) ACPI BIOS Warning (bug): Invalid length for FADT/Pm1aEventBlock: 16, using default 32 (20150410/tbfadt-704) ACPI: DSDT 0x000000007A669280 0027D8 (v05 COREv4 COREBOOT 20110725 INTL 20160831) ACPI: FACS 0x000000007A669240 000040 ACPI: FACS 0x000000007A669240 000040 ACPI: SSDT 0x000000007A66BB70 000774 (v02 CORE COREBOOT 0000002A CORE 0000002A) ACPI: MCFG 0x000000007A66C2F0 00003C (v01 CORE COREBOOT 00000000 CORE 00000000) ACPI: TCPA 0x000000007A66C330 000032 (v02 CORE COREBOOT 00000000 CORE 00000000) ACPI: TPM2 0x000000007A66C370 000034 (v04 CORE COREBOOT 00000000 CORE 00000000) ACPI: APIC 0x000000007A66C3B0 00006C (v01 CORE COREBOOT 00000000 CORE 00000000) ACPI: HPET 0x000000007A66C420 000038 (v01 CORE COREBOOT 00000000 CORE 00000000) Zone ranges: DMA [mem 0x0000000000001000-0x0000000000ffffff] DMA32 [mem 0x0000000001000000-0x00000000ffffffff] Normal [mem 0x0000000100000000-0x000000017fffffff] Movable zone start for each node Early memory node ranges node 0: [mem 0x0000000000001000-0x000000000009ffff] node 0: [mem 0x0000000000100000-0x000000000fffffff] node 0: [mem 0x0000000012151000-0x000000007a64ffff] node 0: [mem 0x0000000100000000-0x000000017fffffff] Initmem setup node 0 [mem 0x0000000000001000-0x000000017fffffff] ACPI: PM-Timer IO Port: 0x408 IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-119 ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level) Using ACPI (MADT) for SMP configuration information ACPI: HPET id: 0x8086a701 base: 0xfed00000 smpboot: Allowing 4 CPUs, 0 hotplug CPUs PM: Registered nosave memory: [mem 0x00000000-0x00000fff] PM: Registered nosave memory: [mem 0x000a0000-0x000fffff] PM: Registered nosave memory: [mem 0x10000000-0x12150fff] PM: Registered nosave memory: [mem 0x7a650000-0x7affffff] PM: Registered nosave memory: [mem 0x7b000000-0x7fffffff] PM: Registered nosave memory: [mem 0x80000000-0xcfffffff] PM: Registered nosave memory: [mem 0xd0000000-0xffffffff] e820: [mem 0x80000000-0xcfffffff] available for PCI devices clocksource refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1910969940391419 ns setup_percpu: NR_CPUS:4 nr_cpumask_bits:4 nr_cpu_ids:4 nr_node_ids:1 PERCPU: Embedded 32 pages/cpu @ffff88017fc00000 s93912 r8192 d28968 u524288 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 1001076 Kernel command line: BOOT_IMAGE=(ahci0,msdos1)/boot/bzImage root=/dev/sda1 rootdelay=10 console=ttyS2,115200 PID hash table entries: 4096 (order: 3, 32768 bytes) Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes) Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes) xsave: enabled xstate_bv 0x1b, cntxt size 0x440 using standard form Memory: 3909396K/4067960K available (10570K kernel code, 1220K rwdata, 4084K rodata, 1380K init, 1068K bss, 158564K reserved, 0K cma-reserved) SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 Preemptible hierarchical RCU implementation. Additional per-CPU info printed with stalls. NR_IRQS:4352 nr_irqs:1024 16 Console: colour dummy device 80x25 console [ttyS2] enabled clocksource hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 99544814920 ns tsc: PIT calibration matches HPET. 1 loops tsc: Detected 1593.639 MHz processor Calibrating delay loop (skipped), value calculated using timer frequency.. 3187.27 BogoMIPS (lpj=1593639) pid_max: default: 32768 minimum: 301 ACPI: Core revision 20150410 ACPI: 2 ACPI AML tables successfully acquired and loaded Security Framework initialized Mount-cache hash table entries: 8192 (order: 4, 65536 bytes) Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes) Initializing cgroup subsys blkio Initializing cgroup subsys memory Initializing cgroup subsys devices Initializing cgroup subsys freezer Initializing cgroup subsys net_cls Initializing cgroup subsys debug CPU: Physical Processor ID: 0 CPU: Processor Core ID: 0 mce: CPU supports 7 MCE banks CPU0: Thermal monitoring enabled (TM1) Last level iTLB entries: 4KB 48, 2MB 0, 4MB 0 Last level dTLB entries: 4KB 0, 2MB 0, 4MB 0, 1GB 0 Freeing SMP alternatives memory: 36K (ffffffff8228c000 - ffffffff82295000) ftrace: allocating 36317 entries in 142 pages x2apic: IRQ remapping doesn't support X2APIC mode ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 smpboot: CPU0: Intel(R) Atom(TM) Processor E3950 @ 1.60GHz (family: 0x6, model: 0x5c, stepping: 0x9) Performance Events: PEBS fmt3+, 32-deep LBR, Goldmont events, full-width counters, Intel PMU driver. ... version: 4 ... bit width: 48 ... generic registers: 4 ... value mask: 0000ffffffffffff ... max period: 0000ffffffffffff ... fixed-purpose events: 3 ... event mask: 000000070000000f x86: Booting SMP configuration: .... node #0, CPUs: #1 #2 #3 x86: Booted up 1 node, 4 CPUs smpboot: Total of 4 processors activated (12749.11 BogoMIPS) devtmpfs: initialized clocksource jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns xor: measuring software checksum speed prefetch64-sse: 10212.000 MB/sec generic_sse: 8832.000 MB/sec xor: using function: prefetch64-sse (10212.000 MB/sec) pinctrl core: initialized pinctrl subsystem NET: Registered protocol family 16 cpuidle: using governor ladder cpuidle: using governor menu failed to register the SPI slaves... ACPI: bus type PCI registered PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in E820 PCI: Using configuration type 1 for base access raid6: sse2x1 gen() 4566 MB/s raid6: sse2x1 xor() 2697 MB/s raid6: sse2x2 gen() 4988 MB/s raid6: sse2x2 xor() 3156 MB/s raid6: sse2x4 gen() 5699 MB/s raid6: sse2x4 xor() 2541 MB/s raid6: using algorithm sse2x4 gen() 5699 MB/s raid6: .... xor() 2541 MB/s, rmw enabled raid6: using ssse3x2 recovery algorithm ACPI: Added _OSI(Module Device) ACPI: Added _OSI(Processor Device) ACPI: Added _OSI(3.0 _SCP Extensions) ACPI: Added _OSI(Processor Aggregator Device) ACPI: Executed 1 blocks of module-level executable AML code ACPI: Interpreter enabled ACPI: (supports S0 S3 S4 S5) ACPI: Using IOAPIC for interrupt routing PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability] PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [bus 00-ff] pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000c3fff window] pci_bus 0000:00: root bus resource [mem 0x000c4000-0x000c7fff window] pci_bus 0000:00: root bus resource [mem 0x000c8000-0x000cbfff window] pci_bus 0000:00: root bus resource [mem 0x000cc000-0x000cffff window] pci_bus 0000:00: root bus resource [mem 0x000d0000-0x000d3fff window] pci_bus 0000:00: root bus resource [mem 0x000d4000-0x000d7fff window] pci_bus 0000:00: root bus resource [mem 0x000d8000-0x000dbfff window] pci_bus 0000:00: root bus resource [mem 0x000dc000-0x000dffff window] pci_bus 0000:00: root bus resource [mem 0x000e0000-0x000e3fff window] pci_bus 0000:00: root bus resource [mem 0x000e4000-0x000e7fff window] pci_bus 0000:00: root bus resource [mem 0x000e8000-0x000ebfff window] pci_bus 0000:00: root bus resource [mem 0x000ec000-0x000effff window] pci_bus 0000:00: root bus resource [mem 0x000f0000-0x000fffff window] pci_bus 0000:00: root bus resource [mem 0x7c000000-0x7fffffff window] pci_bus 0000:00: root bus resource [mem 0x80000000-0xcfffffff window] pci_bus 0000:00: root bus resource [mem 0xfed40000-0xfed44fff window] pci 0000:00:13.0: PCI bridge to [bus 01] pci 0000:00:13.2: PCI bridge to [bus 02] pci 0000:00:13.3: PCI bridge to [bus 03] pci 0000:00:14.0: PCI bridge to [bus 04] pci 0000:00:14.1: PCI bridge to [bus 05] pci 0000:02:00.0: Max Payload Size 128, but upstream 0000:00:13.2 set to 256; if necessary, use "pci=pcie_bus_safe" and report a bug ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. vgaarb: setting as boot device: PCI:0000:00:02.0 vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none vgaarb: loaded vgaarb: bridge control possible 0000:00:02.0 SCSI subsystem initialized ACPI: bus type USB registered usbcore: registered new interface driver usbfs usbcore: registered new interface driver hub usbcore: registered new device driver usb pps_core: LinuxPPS API ver. 1 registered pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti < giometti(a)linux.it> PTP clock support registered EDAC MC: Ver: 3.0.0 Advanced Linux Sound Architecture Driver Initialized. PCI: Using ACPI for IRQ routing Bluetooth: Core ver 2.20 NET: Registered protocol family 31 Bluetooth: HCI device and connection manager initialized Bluetooth: HCI socket layer initialized Bluetooth: L2CAP socket layer initialized Bluetooth: SCO socket layer initialized hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0 hpet0: 8 comparators, 64-bit 19.200000 MHz counter Switched to clocksource hpet pnp: PnP ACPI init system 00:00: [mem 0xd0000000-0xdfffffff] could not be reserved system 00:00: [mem 0xe0000000-0xefffffff] has been reserved system 00:00: [mem 0xfee00000-0xfeefffff] has been reserved system 00:01: [io 0x0400-0x04fe] could not be reserved pnp: PnP ACPI: found 3 devices clocksource acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns pci 0000:00:13.0: BAR 8: assigned [mem 0x80000000-0x801fffff] pci 0000:00:13.0: BAR 9: assigned [mem 0x80200000-0x803fffff 64bit pref] pci 0000:00:13.2: BAR 9: assigned [mem 0x80400000-0x805fffff 64bit pref] pci 0000:00:14.0: BAR 8: assigned [mem 0x80600000-0x807fffff] pci 0000:00:14.0: BAR 9: assigned [mem 0x80800000-0x809fffff 64bit pref] pci 0000:00:14.1: BAR 8: assigned [mem 0x80a00000-0x80bfffff] pci 0000:00:14.1: BAR 9: assigned [mem 0x80c00000-0x80dfffff 64bit pref] pci 0000:00:13.0: BAR 7: assigned [io 0x3000-0x3fff] pci 0000:00:14.0: BAR 7: assigned [io 0x4000-0x4fff] pci 0000:00:14.1: BAR 7: assigned [io 0x5000-0x5fff] pci 0000:00:13.0: PCI bridge to [bus 01] pci 0000:00:13.0: bridge window [io 0x3000-0x3fff] pci 0000:00:13.0: bridge window [mem 0x80000000-0x801fffff] pci 0000:00:13.0: bridge window [mem 0x80200000-0x803fffff 64bit pref] pci 0000:00:13.2: PCI bridge to [bus 02] pci 0000:00:13.2: bridge window [io 0x1000-0x1fff] pci 0000:00:13.2: bridge window [mem 0xc1300000-0xc13fffff] pci 0000:00:13.2: bridge window [mem 0x80400000-0x805fffff 64bit pref] pci 0000:00:13.3: PCI bridge to [bus 03] pci 0000:00:14.0: PCI bridge to [bus 04] pci 0000:00:14.0: bridge window [io 0x4000-0x4fff] pci 0000:00:14.0: bridge window [mem 0x80600000-0x807fffff] pci 0000:00:14.0: bridge window [mem 0x80800000-0x809fffff 64bit pref] pci 0000:00:14.1: PCI bridge to [bus 05] pci 0000:00:14.1: bridge window [io 0x5000-0x5fff] pci 0000:00:14.1: bridge window [mem 0x80a00000-0x80bfffff] pci 0000:00:14.1: bridge window [mem 0x80c00000-0x80dfffff 64bit pref] NET: Registered protocol family 2 TCP established hash table entries: 32768 (order: 6, 262144 bytes) TCP bind hash table entries: 32768 (order: 7, 524288 bytes) TCP: Hash tables configured (established 32768 bind 32768) UDP hash table entries: 2048 (order: 4, 65536 bytes) UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes) NET: Registered protocol family 1 RPC: Registered named UNIX socket transport module. RPC: Registered udp transport module. RPC: Registered tcp transport module. RPC: Registered tcp NFSv4.1 backchannel transport module. PCI-DMA: Using software bounce buffering for IO (SWIOTLB) software IO TLB [mem 0x76650000-0x7a650000] (64MB) mapped at [ffff880076650000-ffff88007a64ffff] microcode: CPU0 sig=0x506c9, pf=0x1, revision=0x1c microcode: CPU1 sig=0x506c9, pf=0x1, revision=0x1c microcode: CPU2 sig=0x506c9, pf=0x1, revision=0x1c microcode: CPU3 sig=0x506c9, pf=0x1, revision=0x1c microcode: Microcode Update Driver: v2.00 <tigran(a)aivazian.fsnet.co.uk>, Peter Oruba Scanning for low memory corruption every 60 seconds Apollo Lake Sideband Interface loading i2c adapter not found i2c adapter not found futex hash table entries: 1024 (order: 4, 65536 bytes) HugeTLB registered 1 GB page size, pre-allocated 0 pages HugeTLB registered 2 MB page size, pre-allocated 0 pages NFS: Registering the id_resolver key type Key type id_resolver registered Key type id_legacy registered aufs 4.1-20150629 Block layer SCSI generic (bsg) driver version 0.4 loaded (major 249) io scheduler noop registered io scheduler deadline registered io scheduler cfq registered (default) pcieport 0000:00:13.0: enabling device (0104 -> 0107) pcieport 0000:00:14.0: enabling device (0104 -> 0107) pcieport 0000:00:14.1: enabling device (0104 -> 0107) pcieport 0000:00:13.0: Signaling PME through PCIe PME interrupt pcieport 0000:00:13.2: Signaling PME through PCIe PME interrupt pci 0000:02:00.0: Signaling PME through PCIe PME interrupt pcieport 0000:00:13.3: Signaling PME through PCIe PME interrupt pcieport 0000:00:14.0: Signaling PME through PCIe PME interrupt pcieport 0000:00:14.1: Signaling PME through PCIe PME interrupt pci_hotplug: PCI Hot Plug PCI Core version: 0.5 efifb: probing for efifb efifb: framebuffer at 0xb0000000, mapped to 0xffffc90000800000, using 8128k, total 8128k efifb: mode is 1920x1080x32, linelength=7680, pages=1 efifb: scrolling: redraw efifb: Truecolor: size=8:8:8:8, shift=24:16:8:0 Console: switching to colour frame buffer device 240x67 fb0: EFI VGA frame buffer device input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input0 ACPI: Power Button [PWRB] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1 ACPI: Power Button [PWRF] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled Linux agpgart interface v0.103 [drm] Initialized drm 1.1.0 20060810 [drm] Memory usable by graphics device = 4096M fb: switching to inteldrmfb from EFI VGA Console: switching to colour dummy device 80x25 [drm] Replacing VGA console driver [drm] RC6 disabled by BIOS [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [drm] Driver supports precise vblank timestamp query. i915 0000:00:02.0: Direct firmware load for i915/bxt_dmc_ver1.bin failed with error -2 i915 0000:00:02.0: Failed to load DMC firmware [ https://01.org/linuxgraphics/intel-linux-graphics-firmwares], disabling runtime power management. vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem [drm] failed to retrieve link info, disabling eDP i915 0000:00:02.0: Direct firmware load for i915/bxt_guc_ver8.bin failed with error -2 [drm:intel_guc_ucode_init] *ERROR* Failed to fetch GuC firmware from i915/bxt_guc_ver8.bin (error -2) tsc: Refined TSC clocksource calibration: 1593.615 MHz clocksource tsc: mask: 0xffffffffffffffff max_cycles: 0x16f89566daa, max_idle_ns: 440795280110 ns [drm] RC6 disabled, disabling runtime PM support IOTG i915 forklift 2016-03-25 IOTG i915 build 2016y-05m-16d-15h-25m-52s -0700 (45c9a12) [drm] Initialized i915 1.6.0 20160314 for 0000:00:02.0 on minor 0 brd: module loaded loop: module loaded sbi_apl starting, bus 0, device d.0 apl_gpio apl_gpio.1: Failed to attach ACPI GPIO chip apl_gpio apl_gpio.2: Failed to attach ACPI GPIO chip apl_gpio apl_gpio.3: Failed to attach ACPI GPIO chip idma64 idma64.0: Found Intel integrated DMA 64-bit idma64 idma64.1: Found Intel integrated DMA 64-bit idma64 idma64.2: Found Intel integrated DMA 64-bit idma64 idma64.3: Found Intel integrated DMA 64-bit idma64 idma64.4: Found Intel integrated DMA 64-bit idma64 idma64.5: Found Intel integrated DMA 64-bit idma64 idma64.6: Found Intel integrated DMA 64-bit idma64 idma64.7: Found Intel integrated DMA 64-bit idma64 idma64.8: Found Intel integrated DMA 64-bit dw-apb-uart.8: ttyS0 at MMIO 0xc1435000 (irq = 4, base_baud = 115200) is a 16550A idma64 idma64.9: Found Intel integrated DMA 64-bit dw-apb-uart.9: ttyS1 at MMIO 0xc1437000 (irq = 5, base_baud = 115200) is a 16550A console [ttyS2] disabled dw-apb-uart.10: ttyS2 at MMIO 0xc1439000 (irq = 6, base_baud = 114825) is a 16550A Switched to clocksource tsc [drm] RC6 off [drm:host2guc_action] *ERROR* GuC: host2guc action 0x6 failed. ret=-110 status=0x00000006 response=0x00000000 console [ttyS2] enabled fbcon: inteldrmfb (fb0) is primary device dw-apb-uart.11: ttyS3 at MMIO 0xc143b000 (irq = 7, base_baud = 115200) is a 16550A Console: switching to colour frame buffer device 240x67 idma64 idma64.12: Found Intel integrated DMA 64-bit pxa2xx-spi pxa2xx-spi.12: cs2 >= max 2 pxa2xx-spi pxa2xx-spi.12: can't create new device for spidev idma64 idma64.13: Found Intel integrated DMA 64-bit pxa2xx-spi pxa2xx-spi.13: cs2 >= max 2 pxa2xx-spi pxa2xx-spi.13: can't create new device for spidev idma64 idma64.14: Found Intel integrated DMA 64-bit ahci 0000:00:12.0: AHCI 0001.0301 32 slots 1 ports 6 Gbps 0x1 impl SATA mode ahci 0000:00:12.0: flags: 64bit ncq sntf pm clo only pmp pio slum part deso sadm sds apst scsi host0: ahci ata1: SATA max UDMA/133 abar m2048@0xc1449000 port 0xc1449100 irq 372 igb: Intel(R) Gigabit Ethernet Network Driver - version 5.2.15-k igb: Copyright (c) 2007-2014 Intel Corporation. pps pps0: new PPS source ptp0 igb 0000:02:00.0: added PHC on eth0 igb 0000:02:00.0: Intel(R) Gigabit Ethernet Network Connection igb 0000:02:00.0: eth0: (PCIe:2.5Gb/s:Width x1) 98:4f:ee:13:bb:76 igb 0000:02:00.0: eth0: PBA No: FFFFFF-0FF igb 0000:02:00.0: Using MSI-X interrupts. 4 rx queue(s), 4 tx queue(s) Failed to set pin attr for GSI13 dwc3-pci 0000:00:15.1: PCI INT B: failed to register GSI dwc3-pci: probe of 0000:00:15.1 failed with error -1 xhci_hcd 0000:00:15.0: xHCI Host Controller xhci_hcd 0000:00:15.0: new USB bus registered, assigned bus number 1 xhci_hcd 0000:00:15.0: hcc params 0x200077c1 hci version 0x100 quirks 0x00009810 hub 1-0:1.0: USB hub found hub 1-0:1.0: 8 ports detected xhci_hcd 0000:00:15.0: xHCI Host Controller xhci_hcd 0000:00:15.0: new USB bus registered, assigned bus number 2 hub 2-0:1.0: USB hub found hub 2-0:1.0: 7 ports detected usbcore: registered new interface driver usb-storage i8042: PNP: No PS/2 controller found. Probing ports directly. i915 0000:00:02.0: fb0: inteldrmfb frame buffer device ata1: SATA link down (SStatus 4 SControl 300) i8042: No controller found mousedev: PS/2 mouse device common for all mice rtc_cmos 00:02: rtc core: registered rtc_cmos as rtc0 rtc_cmos 00:02: alarms up to one month, 242 bytes nvram, hpet irqs i2c /dev entries driver i801_smbus 0000:00:1f.1: can't derive routing for PCI INT A i801_smbus 0000:00:1f.1: PCI INT A: no GSI genirq: Flags mismatch irq 0. 00000080 (i801_smbus) vs. 00015a00 (timer) i801_smbus 0000:00:1f.1: Failed to allocate irq 0: -16 i801_smbus 0000:00:1f.1: SMBus using polling md: linear personality registered for level -1 md: raid0 personality registered for level 0 md: raid1 personality registered for level 1 md: raid10 personality registered for level 10 md: multipath personality registered for level -4 md: faulty personality registered for level -5 device-mapper: ioctl: 4.31.0-ioctl (2015-3-12) initialised: dm-devel(a)redhat.com EDAC pnd2: ECC disabled on channel 0 EDAC pnd2: Failed to register device with error -22. Intel P-state driver initializing. sdhci: Secure Digital Host Controller Interface driver sdhci: Copyright(c) Pierre Ossman sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:5aca] (rev b) sdhci-pci 0000:00:1b.0: failed to setup card detect gpio sdhci-pci 0000:00:1b.0: No vmmc regulator found sdhci-pci 0000:00:1b.0: No vqmmc regulator found mmc0: SDHCI controller on PCI [0000:00:1b.0] using ADMA 64-bit sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev b) sdhci-pci 0000:00:1c.0: No vmmc regulator found sdhci-pci 0000:00:1c.0: No vqmmc regulator found usb 1-2: new low-speed USB device number 2 using xhci_hcd mmc1: SDHCI controller on PCI [0000:00:1c.0] using ADMA 64-bit sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:5ad0] (rev b) sdhci-pci 0000:00:1e.0: No vmmc regulator found sdhci-pci 0000:00:1e.0: No vqmmc regulator found mmc2: SDHCI controller on PCI [0000:00:1e.0] using ADMA 64-bit usbcore: registered new interface driver usbhid usbhid: USB HID core driver mmc1: MAN_BKOPS_EN bit is not set mmc1: new HS400 MMC card at address 0001 mmcblk0: mmc1:0001 CGND3R 58.2 GiB mmcblk0boot0: mmc1:0001 CGND3R partition 1 4.00 MiB mmcblk0boot1: mmc1:0001 CGND3R partition 2 4.00 MiB mmcblk0rpmb: mmc1:0001 CGND3R partition 3 4.00 MiB usb 1-2: ep 0x81 - rounding interval to 64 microframes, ep desc says 80 microframes usb 1-2: ep 0x82 - rounding interval to 64 microframes, ep desc says 80 microframes input: SIGMACHIP USB Keyboard as /devices/pci0000:00/0000:00:15.0/usb1/1-2/1-2:1.0/0003:1C4F:0016.0001/input/input2 hid-generic 0003:1C4F:0016.0001: input: USB HID v1.10 Keyboard [SIGMACHIP USB Keyboard] on usb-0000:00:15.0-2/input0 input: SIGMACHIP USB Keyboard as /devices/pci0000:00/0000:00:15.0/usb1/1-2/1-2:1.1/0003:1C4F:0016.0002/input/input3 hid-generic 0003:1C4F:0016.0002: input: USB HID v1.10 Device [SIGMACHIP USB Keyboard] on usb-0000:00:15.0-2/input1 oprofile: using NMI interrupt. u32 classifier Actions configured NET: Registered protocol family 10 sit: IPv6 over IPv4 tunneling driver NET: Registered protocol family 17 l2tp_core: L2TP core driver, V2.0 l2tp_netlink: L2TP netlink interface Key type dns_resolver registered Btrfs loaded console [netcon0] enabled netconsole: network logging started rtc_cmos 00:02: setting system clock to 2017-02-25 20:39:16 UTC (1488055156) snd_hda_codec_realtek hdaudioC0D0: ALC662 rev3: SKU not ready 0x00000100 snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC662 rev3: line_outs=3 (0x14/0x16/0x15/0x0/0x0) type:line snd_hda_codec_realtek hdaudioC0D0: speaker_outs=0 (0x0/0x0/0x0/0x0/0x0) snd_hda_codec_realtek hdaudioC0D0: hp_outs=1 (0x1b/0x0/0x0/0x0/0x0) snd_hda_codec_realtek hdaudioC0D0: mono: mono_out=0x0 snd_hda_codec_realtek hdaudioC0D0: dig-out=0x1e/0x0 snd_hda_codec_realtek hdaudioC0D0: inputs: snd_hda_codec_realtek hdaudioC0D0: Rear Mic=0x18 snd_hda_codec_realtek hdaudioC0D0: Front Mic=0x19 snd_hda_codec_realtek hdaudioC0D0: Line=0x1a snd_hda_codec_realtek hdaudioC0D0: CD=0x1c snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec input: HDA Intel Rear Mic as /devices/pci0000:00/0000:00:0e.0/sound/card0/input4 input: HDA Intel Front Mic as /devices/pci0000:00/0000:00:0e.0/sound/card0/input5 input: HDA Intel Line as /devices/pci0000:00/0000:00:0e.0/sound/card0/input6 input: HDA Intel Line Out Front as /devices/pci0000:00/0000:00:0e.0/sound/card0/input7 input: HDA Intel Line Out Surround as /devices/pci0000:00/0000:00:0e.0/sound/card0/input8 input: HDA Intel Line Out CLFE as /devices/pci0000:00/0000:00:0e.0/sound/card0/input9 input: HDA Intel Front Headphone as /devices/pci0000:00/0000:00:0e.0/sound/card0/input10 input: HDA Intel HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input11 ish-hid {33AECD58-B679-4E54-9BD9-A04D34F0C226}: [hid-ish]: enum_devices_done OK, num_hid_devices=4 ALSA device list: #0: HDA Intel at 0xc1418000 irq 379 ttyS2 - failed to request DMA Waiting 10 sec before mounting root device... md: Waiting for all devices to be available before autodetect md: If you don't use raid, use raid=noautodetect md: Autodetecting RAID arrays. md: Scanned 0 and added 0 devices. md: autorun ... md: ... autorun DONE. VFS: Cannot open root device "sda1" or unknown-block(0,0): error -6 Please append a correct "root=" boot option; here are the available partitions: 0100 4096 ram0 (driver?) 0101 4096 ram1 (driver?) 0102 4096 ram2 (driver?) 0103 4096 ram3 (driver?) 0104 4096 ram4 (driver?) 0105 4096 ram5 (driver?) 0106 4096 ram6 (driver?) 0107 4096 ram7 (driver?) 0108 4096 ram8 (driver?) 0109 4096 ram9 (driver?) 010a 4096 ram10 (driver?) 010b 4096 ram11 (driver?) 010c 4096 ram12 (driver?) 010d 4096 ram13 (driver?) 010e 4096 ram14 (driver?) 010f 4096 ram15 (driver?) b300 61071360 mmcblk0 driver: mmcblk b318 4096 mmcblk0rpmb (driver?) b310 4096 mmcblk0boot1 (driver?) b308 4096 mmcblk0boot0 (driver?) VFS: Unable to mount root fs on unknown-block(0,0) User configuration error - no valid root filesystem found Kernel panic - not syncing: Invalid configuration from end user prevents continuing CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.1.21-WR8.0.0.11_standard #1 Hardware name: Intel Leafhill/Leafhill, BIOS APOLLOLAKE_CB_MR1_001 03/02/2017 0000000000000000 ffff88017b12fd28 ffffffff81a4568e ffffffff81eb7630 0000000000008001 ffff88017b12fda8 ffffffff81a438fa ffff88017b12fd48 ffffffff00000008 ffff88017b12fdb8 ffff88017b12fd58 62306b6c62636d6d Call Trace: [<ffffffff81a4568e>] dump_stack+0x4f/0x65 [<ffffffff81a438fa>] panic+0xbb/0x1d1 [<ffffffff8214b544>] mount_block_root+0x21e/0x235 [<ffffffff8214b76b>] mount_root+0xf1/0xfc [<ffffffff811a69a6>] ? SyS_unlink+0x16/0x20 [<ffffffff8214b8e3>] prepare_namespace+0x16d/0x1a6 [<ffffffff8214b16f>] kernel_init_freeable+0x200/0x215 [<ffffffff81a414e0>] ? rest_init+0x90/0x90 [<ffffffff81a414ee>] kernel_init+0xe/0xf0 [<ffffffff81a4dea2>] ret_from_fork+0x42/0x70 [<ffffffff81a414e0>] ? rest_init+0x90/0x90 Kernel Offset: disabled ---[ end Kernel panic - not syncing: Invalid configuration from end user prevents continuing

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Re: [coreboot] Some errors by compiling romstage (I am a newbie)
by Aaron Durbin 03 Mar '17

03 Mar '17

On Fri, Mar 3, 2017 at 8:37 AM, Maxim Gusev <mail(a)maximgusev.com> wrote: > It doesn't work any case. > As I understood these options remove the unreferenced symbols, but I have > referenced symbols (the error is undefined reference). > The definition of the used functions is in the file that is missing at this > stage but all works on other archs. > The symbol might be referenced in one function in that compilation unit, but if the symbol of the function using the undefined symbols is not referenced from any of the root symbols then it should be removed. The fact that it isn't suggests -gc-sections isn't working *or* -f(data|function)-sections isn't working. As I requested previously, readelf -e from one of the romstage .o files would confirm the latter. As it stands now I can't speculate as to what is happening because the code you are working on isn't published so I can't do anything beyond request the information I've already requested. > > > -------- Original Message -------- > Subject: Re: [coreboot] Some errors by compiling romstage (I am a newbie) > Local Time: 3 Марта 2017 г. 4:54 дня > UTC Time: 3 Марта 2017 г. 13:54 > From: adurbin(a)google.com > To: Maxim Gusev <mail(a)maximgusev.com>, Coreboot <coreboot(a)coreboot.org> > > On Fri, Mar 3, 2017 at 6:41 AM, Maxim Gusev <mail(a)maximgusev.com> wrote: >> These options are supported. >> But the option -fno-pie is not supported (Don’t produce a position >> independent executable). >> Is it the reason of the fault? > > > I wouldn't think so. If you remove that option does it magically work? > From the errors you showed -gc-sections along with -fdata-sections and > -ffunction-sections would have removed the unreferenced symbols and > not cause a link error. To prove that -f(data|function)-sections are > working can you provide the readelf -e output from an intermediate .o > file you compiled for romstage? > >> >> >> >> -------- Original Message -------- >> Subject: Re: [coreboot] Some errors by compiling romstage (I am a newbie) >> Local Time: 2 Марта 2017 г. 6:01 вечера >> UTC Time: 2 Марта 2017 г. 15:01 >> From: adurbin(a)google.com >> To: Maxim Gusev <mail(a)maximgusev.com> >> coreboot(a)coreboot.org <coreboot(a)coreboot.org> >> >> On Thu, Mar 2, 2017 at 8:33 AM, Maxim Gusev <mail(a)maximgusev.com> wrote: >>> Hello, Aaron! >>> >>> I am compiling sourses of my arch e2k. >>> I have compiled bootblock with my sources. There aren't my sources in >>> other >>> stages. I have create arch directory and mainboard directory where the >>> sources are located. >>> >>> >>> >>> Log: >>> >>> /home/maxim/coreboot/util/crossgcc/xgcc/bin/linux-ld: warning: cannot >>> find >>> entry symbol start; defaulting to 0000000100187000 >>> build/romstage/lib/imd_cbmem.o: In function `cbmem_add_bootmem': >>> /home/maxim/coreboot/src/lib/imd_cbmem.c:287: undefined reference to >>> `bootmem_add_range' >>> build/romstage/lib/imd_cbmem.o: In function >>> `cbmem_add_records_to_cbtable': >>> /home/maxim/coreboot/src/lib/imd_cbmem.c:314: undefined reference to >>> `lb_new_record' >>> make: *** [build/cbfs/fallback/romstage.debug] Error 1 >>> >> >> Does your arch's compiler support -ffuncation-sections and >> -fdata-sections? As well as your linker supporting --gc-sections ? All >> the architectures we support have those flags. See Makefile.inc which >> provides those in CFLAGS_common and LDFLAGS_common. That support >> allows us to not sprinkle #ifdef's all around in the code when the >> same source file is compiled for different stages. >> >>> >>> >>> -------- Original Message -------- >>> Subject: Re: [coreboot] Some errors by compiling romstage (I am a newbie) >>> Local Time: 2 Марта 2017 г. 5:22 вечера >>> UTC Time: 2 Марта 2017 г. 14:22 >>> From: adurbin(a)google.com >>> To: Maxim Gusev <mail(a)maximgusev.com> >>> coreboot(a)coreboot.org <coreboot(a)coreboot.org> >>> >>> On Thu, Mar 2, 2017 at 7:24 AM, Maxim Gusev via coreboot >>> <coreboot(a)coreboot.org> wrote: >>>> Hi everbody! >>>> >>>> I have a question. Very hope for your help. >>>> >>>> When I am compiling the romstage there are 2 errors by the linker: >>>> Undefined refference to 'bootmem_add_range' >>>> Undefined refference to 'lb_new_record' in the imd_cbmem.c file (it is >>>> included in src/lib/Makefile.inc romstage). >>>> >>>> The definitions of these functions are in lib/bootmem.c and >>>> lib/coreboot_table.c accordingly. >>>> But I can't see the inclusion of these files in romstage in >>>> src/Makefile.inc >>>> (only in ramstage): >>>> ramstage-y += bootmem.c >>>> ramstage-y += coreboot_table.c >>>> >>>> How to solve this problem? >>>> The inclusion of these files produces a number of other errors, but >>>> nowhere >>>> in the code no one does it? Why only I am having this error. >>> >>> >>> What board are you building? Are you working on local patches to your >>> setup only? What does the build log indicate? >>> >>>> >>>> In General, I don't even need these stages (romstage and ramstage) - I >>>> want >>>> to check the performance on real hardware the work of the bootblock, but >>>> the >>>> toolchain requires me to compile other stages. And the error occurs even >>>> not >>>> in my code, but my ignorance. >>>> >>>> Thanks a lot! >>>> Regards, Maxim >>>> >>>> >>>> >>>> >>>> -- >>>> coreboot mailing list: coreboot(a)coreboot.org >>>> https://www.coreboot.org/mailman/listinfo/coreboot >>> >>> >> >> > >

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Re: [coreboot] coreboot+filo
by sebastien basset 03 Mar '17

03 Mar '17

when i see filo.elf with readelf -a : ELF Header: Magic: 7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00 Class: ELF32 Data: 2's complement, little endian Version: 1 (current) OS/ABI: UNIX - System V ABI Version: 0 Type: EXEC (Executable file) Machine: Intel 80386 Version: 0x1 Entry point address: 0x100000 Start of program headers: 52 (bytes into file) Start of section headers: 1255408 (bytes into file) Flags: 0x0 Size of this header: 52 (bytes) Size of program headers: 32 (bytes) Number of program headers: 1 Size of section headers: 40 (bytes) Number of section headers: 10 Section header string table index: 9 Section Headers: [Nr] Name Type Addr Off Size ES Flg Lk Inf Al [ 0] NULL 00000000 000000 000000 00 0 0 0 [ 1] .text PROGBITS 00100000 100000 01e416 00 AX 0 0 16 [ 2] .boot PROGBITS 0011e418 11e418 000064 00 AX 0 0 4 [ 3] .rodata PROGBITS 0011e480 11e480 0047f7 00 A 0 0 32 [ 4] .eh_frame PROGBITS 00122c78 122c78 00d144 00 A 0 0 4 [ 5] .data PROGBITS 0012fdc0 12fdc0 002980 00 WA 0 0 32 [ 6] .hdr.mb PROGBITS 00132740 132740 00000c 00 WA 0 0 4 [ 7] .initctx PROGBITS 00132760 132760 000048 00 WA 0 0 32 [ 8] .bss NOBITS 001327c0 1327a8 041920 00 WA 0 0 32 [ 9] .shstrtab STRTAB 00000000 1327a8 000045 00 0 0 1 Key to Flags: W (write), A (alloc), X (execute), M (merge), S (strings) I (info), L (link order), G (group), T (TLS), E (exclude), x (unknown) O (extra OS processing required) o (OS specific), p (processor specific) There are no section groups in this file. Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x000000 0x00000000 0x00000000 0x1327a8 0x1740e0 RWE 0x200000 Section to Segment mapping: Segment Sections... 00 .text .boot .rodata .eh_frame .data .hdr.mb .initctx .bss There is no dynamic section in this file. There are no relocations in this file. The decoding of unwind sections for machine type Intel 80386 is not currently supported. No version information found in this file. readelf -a seabios: ELF Header: Magic: 7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00 Class: ELF32 Data: 2's complement, little endian Version: 1 (current) OS/ABI: UNIX - System V ABI Version: 0 Type: EXEC (Executable file) Machine: Intel 80386 Version: 0x1 Entry point address: 0xff06e Start of program headers: 52 (bytes into file) Start of section headers: 114388 (bytes into file) Flags: 0x0 Size of this header: 52 (bytes) Size of program headers: 32 (bytes) Number of program headers: 1 Size of section headers: 40 (bytes) Number of section headers: 3 Section header string table index: 2 Section Headers: [Nr] Name Type Addr Off Size ES Flg Lk Inf Al [ 0] NULL 00000000 000000 000000 00 0 0 0 [ 1] .text PROGBITS 000e41a0 000060 01be60 00 WAX 0 0 32 [ 2] .shstrtab STRTAB 00000000 01bec0 000011 00 0 0 1 Key to Flags: W (write), A (alloc), X (execute), M (merge), S (strings) I (info), L (link order), G (group), T (TLS), E (exclude), x (unknown) O (extra OS processing required) o (OS specific), p (processor specific) There are no section groups in this file. Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x000060 0x000e41a0 0x000e41a0 0x1be60 0x1be60 RWE 0x20 Section to Segment mapping: Segment Sections... 00 .text There is no dynamic section in this file. There are no relocations in this file. The decoding of unwind sections for machine type Intel 80386 is not currently supported. No version information found in this file. when i use seabios as payload : Loading segment from ROM address 0xfff1c5f8 code (compression=1) New segment dstaddr 0xe41a0 memsize 0x1be60 srcaddr 0xfff1c630 filesize 0xe6bb Loading segment from ROM address 0xfff1c614 Entry Point 0x000ff06e Payload being loaded at below 1MiB without region being marked as RAM usable. Bounce Buffer at 7cbf8000, 397312 bytes Loading Segment: addr: 0x00000000000e41a0 memsz: 0x000000000001be60 filesz: 0x000000000000e6bb lb: [0x0000000000100000, 0x0000000000130800) Post relocation: addr: 0x00000000000e41a0 memsz: 0x000000000001be60 filesz: 0x000000000000e6bb using LZMA [ 0x000e41a0, 00100000, 0x00100000) <- fff1c630 dest 000e41a0, end 00100000, bouncebuffer 7cbf8000 Loaded segments Calling FspNotify(0x00000040) POST: 0x95 src/soc/intel/braswell/southcluster.c/finalize_chipset ( 0x00000000 ) Finalizing SMM. BS: BS_PAYLOAD_LOAD times (us): entry 0 run 105509 exit 28406 POST: 0x7b Jumping to boot code at 000ff06e(7cc8e000) POST: 0xf8 CPU0: stack: 00127000 - 00128000, lowest used address 00127a70, stack used: 1424 bytes entry = 0x000ff06e lb_start = 0x00100000 lb_size = 0x00030800 buffer = 0x7cbf8000 SeaBIOS (version rel-1.9.3-0-ge2fc41e) for seabios New segment dstaddr 0xe41a0 memsize 0x1be60 srcaddr 0xfff1c630 filesize 0xe6bb and filo New segment dstaddr 0x0 memsize 0x1740e0 srcaddr 0xfff1c630 filesize 0x179c3 why dstaddr 0x0 for filo ? how to change ... 2017-03-03 10:38 GMT+01:00 sebastien basset <sbhome1(a)gmail.com>: > Hi all, > > - i use this config: > > 582 CONFIG_PAYLOAD_FILO=y > 589 CONFIG_FILO_MASTER=y > 590 CONFIG_PAYLOAD_FILE="payloads/external/FILO/filo/build/filo.elf" > 591 CONFIG_PAYLOAD_OPTIONS="" > > My logs: > > BS: BS_WRITE_TABLES times (us): entry 166670 run 767112 exit 0 > POST: 0x7a > CBFS: 'Master Header Locator' located CBFS at [700100:7fffc0) > CBFS: Locating 'fallback/payload' > CBFS: Found @ offset 1c4c0 size 179fb > Loading segment from ROM address 0xfff1c5f8 > code (compression=1) > New segment dstaddr 0x0 memsize 0x1740e0 srcaddr 0xfff1c630 filesize > 0x179c3 > Loading segment from ROM address 0xfff1c614 > Entry Point 0x00100000 > SELF Payload doesn't target RAM: > Failed Segment: 0x0, 1523936 bytes > 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES > 1. 0000000000001000-000000000009ffff: RAM > 2. 00000000000a0000-00000000000fffff: RESERVED > 3. 0000000000100000-000000007cc58fff: RAM > 4. 000000007cc59000-000000007cffffff: CONFIGURATION TABLES > 5. 000000007d000000-000000007fffffff: RESERVED > 6. 00000000e0000000-00000000efffffff: RESERVED > 7. 00000000fea00000-00000000febfffff: RESERVED > 8. 00000000fed01000-00000000fed01fff: RESERVED > 9. 00000000fed03000-00000000fed03fff: RESERVED > 10. 00000000fed06000-00000000fed06fff: RESERVED > 11. 00000000fed08000-00000000fed08fff: RESERVED > 12. 00000000fed1c000-00000000fed1cfff: RESERVED > 13. 00000000fed80000-00000000fed83fff: RESERVED > Payload not loaded. > > Filo can't loading in ram memory at @ 0x0, can you change this address ? > How to? > > > -- > Sébastien Basset > -- Sébastien Basset

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Re: [coreboot] Some errors by compiling romstage (I am a newbie)
by Aaron Durbin 03 Mar '17

03 Mar '17

On Fri, Mar 3, 2017 at 6:41 AM, Maxim Gusev <mail(a)maximgusev.com> wrote: > These options are supported. > But the option -fno-pie is not supported (Don’t produce a position > independent executable). > Is it the reason of the fault? I wouldn't think so. If you remove that option does it magically work? >From the errors you showed -gc-sections along with -fdata-sections and -ffunction-sections would have removed the unreferenced symbols and not cause a link error. To prove that -f(data|function)-sections are working can you provide the readelf -e output from an intermediate .o file you compiled for romstage? > > > > -------- Original Message -------- > Subject: Re: [coreboot] Some errors by compiling romstage (I am a newbie) > Local Time: 2 Марта 2017 г. 6:01 вечера > UTC Time: 2 Марта 2017 г. 15:01 > From: adurbin(a)google.com > To: Maxim Gusev <mail(a)maximgusev.com> > coreboot(a)coreboot.org <coreboot(a)coreboot.org> > > On Thu, Mar 2, 2017 at 8:33 AM, Maxim Gusev <mail(a)maximgusev.com> wrote: >> Hello, Aaron! >> >> I am compiling sourses of my arch e2k. >> I have compiled bootblock with my sources. There aren't my sources in >> other >> stages. I have create arch directory and mainboard directory where the >> sources are located. >> >> >> >> Log: >> >> /home/maxim/coreboot/util/crossgcc/xgcc/bin/linux-ld: warning: cannot find >> entry symbol start; defaulting to 0000000100187000 >> build/romstage/lib/imd_cbmem.o: In function `cbmem_add_bootmem': >> /home/maxim/coreboot/src/lib/imd_cbmem.c:287: undefined reference to >> `bootmem_add_range' >> build/romstage/lib/imd_cbmem.o: In function >> `cbmem_add_records_to_cbtable': >> /home/maxim/coreboot/src/lib/imd_cbmem.c:314: undefined reference to >> `lb_new_record' >> make: *** [build/cbfs/fallback/romstage.debug] Error 1 >> > > Does your arch's compiler support -ffuncation-sections and > -fdata-sections? As well as your linker supporting --gc-sections ? All > the architectures we support have those flags. See Makefile.inc which > provides those in CFLAGS_common and LDFLAGS_common. That support > allows us to not sprinkle #ifdef's all around in the code when the > same source file is compiled for different stages. > >> >> >> -------- Original Message -------- >> Subject: Re: [coreboot] Some errors by compiling romstage (I am a newbie) >> Local Time: 2 Марта 2017 г. 5:22 вечера >> UTC Time: 2 Марта 2017 г. 14:22 >> From: adurbin(a)google.com >> To: Maxim Gusev <mail(a)maximgusev.com> >> coreboot(a)coreboot.org <coreboot(a)coreboot.org> >> >> On Thu, Mar 2, 2017 at 7:24 AM, Maxim Gusev via coreboot >> <coreboot(a)coreboot.org> wrote: >>> Hi everbody! >>> >>> I have a question. Very hope for your help. >>> >>> When I am compiling the romstage there are 2 errors by the linker: >>> Undefined refference to 'bootmem_add_range' >>> Undefined refference to 'lb_new_record' in the imd_cbmem.c file (it is >>> included in src/lib/Makefile.inc romstage). >>> >>> The definitions of these functions are in lib/bootmem.c and >>> lib/coreboot_table.c accordingly. >>> But I can't see the inclusion of these files in romstage in >>> src/Makefile.inc >>> (only in ramstage): >>> ramstage-y += bootmem.c >>> ramstage-y += coreboot_table.c >>> >>> How to solve this problem? >>> The inclusion of these files produces a number of other errors, but >>> nowhere >>> in the code no one does it? Why only I am having this error. >> >> >> What board are you building? Are you working on local patches to your >> setup only? What does the build log indicate? >> >>> >>> In General, I don't even need these stages (romstage and ramstage) - I >>> want >>> to check the performance on real hardware the work of the bootblock, but >>> the >>> toolchain requires me to compile other stages. And the error occurs even >>> not >>> in my code, but my ignorance. >>> >>> Thanks a lot! >>> Regards, Maxim >>> >>> >>> >>> >>> -- >>> coreboot mailing list: coreboot(a)coreboot.org >>> https://www.coreboot.org/mailman/listinfo/coreboot >> >> > >

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coreboot+filo
by sebastien basset 03 Mar '17

03 Mar '17

Hi all, - i use this config: 582 CONFIG_PAYLOAD_FILO=y 589 CONFIG_FILO_MASTER=y 590 CONFIG_PAYLOAD_FILE="payloads/external/FILO/filo/build/filo.elf" 591 CONFIG_PAYLOAD_OPTIONS="" My logs: BS: BS_WRITE_TABLES times (us): entry 166670 run 767112 exit 0 POST: 0x7a CBFS: 'Master Header Locator' located CBFS at [700100:7fffc0) CBFS: Locating 'fallback/payload' CBFS: Found @ offset 1c4c0 size 179fb Loading segment from ROM address 0xfff1c5f8 code (compression=1) New segment dstaddr 0x0 memsize 0x1740e0 srcaddr 0xfff1c630 filesize 0x179c3 Loading segment from ROM address 0xfff1c614 Entry Point 0x00100000 SELF Payload doesn't target RAM: Failed Segment: 0x0, 1523936 bytes 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-000000007cc58fff: RAM 4. 000000007cc59000-000000007cffffff: CONFIGURATION TABLES 5. 000000007d000000-000000007fffffff: RESERVED 6. 00000000e0000000-00000000efffffff: RESERVED 7. 00000000fea00000-00000000febfffff: RESERVED 8. 00000000fed01000-00000000fed01fff: RESERVED 9. 00000000fed03000-00000000fed03fff: RESERVED 10. 00000000fed06000-00000000fed06fff: RESERVED 11. 00000000fed08000-00000000fed08fff: RESERVED 12. 00000000fed1c000-00000000fed1cfff: RESERVED 13. 00000000fed80000-00000000fed83fff: RESERVED Payload not loaded. Filo can't loading in ram memory at @ 0x0, can you change this address ? How to? -- Sébastien Basset

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Re: [coreboot] The ECC 2017 web page
by Zaolin 03 Mar '17

03 Mar '17

It depends on the browser if it uses hardware accerlation but I am gonna fix that for you. I will add some idle js which stops the video if not focused. Best Regards Zaolin On 03/03/2017 06:11 AM, ron minnich wrote: > That one web page, while not even visible, eats up 25% of the cpu on > one core of my osx laptop. > > Fan is at high speed. Laptop is hot. > > I realize it's a pretty web page and all, but what makes it do that? > Is it necessary for it to cause such power consumption? We need green > web pages :-) > > thanks > > ron > >

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Re: [coreboot] The ECC 2017 web page
by Zoran Stojsavljevic 03 Mar '17

03 Mar '17

> I realize it's a pretty web page and all, but what makes it do that? Ni-na-ni-na... OSX and Chrome viruses and worms web page infested. You need good organic spray against pests... We need similar box as one on this picture: https://en.wikipedia.org/wiki/Pest_control#/media/File:Rodent_Bait_Station,… But cyber modified one! ;-) Zoran _______ On 3/3/17, ron minnich <rminnich(a)gmail.com> wrote: > osx and chrome. Since I closed the tab, my fan is quiet and my power > consumption and cpu usage are back to much less. > > ron > > On Thu, Mar 2, 2017 at 9:15 PM Matt DeVillier <matt.devillier(a)gmail.com> > wrote: > >> I'm seeing ~90MB RAM use and low single digit CPU usage here on >> Win10/Chrome - what browser/OS you you seeing 25% on? >> >> On Thu, Mar 2, 2017 at 11:11 PM, ron minnich <rminnich(a)gmail.com> wrote: >> >> That one web page, while not even visible, eats up 25% of the cpu on one >> core of my osx laptop. >> >> Fan is at high speed. Laptop is hot. >> >> I realize it's a pretty web page and all, but what makes it do that? Is >> it >> necessary for it to cause such power consumption? We need green web pages >> :-) >> >> thanks >> >> ron >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot >> >> >

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Re: [coreboot] Reminder: The maiing list vs forum poll closes in just under 24 hours.
by Zoran Stojsavljevic 03 Mar '17

03 Mar '17

Hello Martin, The current/up to date poll results would be also nice to have... I guess, I am asking for too much, don't I? ;-) (anyway, it is too late) Zoran _______ On 3/3/17, Martin Roth <gaumless(a)gmail.com> wrote: > As brought up in the previous coreboot community meeting, the coreboot > project > is discussing the idea of switching from the mailing list to a forum. This > idea did not originate with the coreboot leadership, but from a request by > members of the community. > > I know many people have some strong feelings about this one way or the > other. Right now we're just collecting data on how people feel about it, > and looking for suggestions on ways to either improve the mailing list or > set up a well-run forum. > > Here's the poll about the switch. I will close the poll tomorrow, > March 3, 2017. > > https://goo.gl/9Hd569 > > Martin > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

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Kernel Panic with coreboot on Tails Linux
by i1w5d7gf38keg＠tutanota.com 03 Mar '17

03 Mar '17

Hardware: Gigabyte G41M-ES2L. coreboot-4.5-1083-g6295b8a57a How to reproduce: Download Tails: https://tails.boum.org/torrents/files/tails-i386-2.10.torrent dd to a usb-drive. Start coreboot and choose inside of seabios the usb-drive. Let it boot, shut it down. The shutdown would at the end create a kernel panic - or at least the capslock and the scroll-led on a PS2 keyboard are flashing. Serial output of coreboot stops as usual at the point when the kernel starts. So no usefull logfiles from crash.

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coreboot March 2017