coreboot April 2015

coreboot@coreboot.org

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92 discussions

Re: [coreboot] Lenovo G505S and Coreboot LTS Candidates list
by Emilian Bold 06 Apr '15

06 Apr '15

I can confirm I'm still able to buy a G505S in my country but it seems to have the quad core A8-4500M (not the A10) with a dedicated Radeon HD 8570M. It's a decent machine and it would be great to have it on the official LTS list. Speaking of the list, I cannot find any store selling the Toshiba Satellite C50D-A mentioned in the wiki. --emi On Mon, Apr 6, 2015 at 1:45 PM, Vladimir <quickcracktime(a)gmail.com> wrote: > Dear coreboot developers, > > Francis Rowe (main Libreboot developer) has hinted an idea about adding > Lenovo G505S to Coreboot LTS Candidates list of laptops, which is hosted at > MrNuke's User talk coreboot wiki page. I believe it is an excellent idea, > because: > > *1)* Lenovo G505S contains AMD APU, so there is no need to deal with > Intel ME/AMT so-called "features" > *2)* this APU has Richland architecture: as result (unlike the more > recent AMD offerings) it doesn't have "AMD Secure" feature -- based on ARM > Trustzone technology which already has some exploits against it; there are > security concerns about ARM Trustzone that are similar to concerns about > Intel vPro "feature" (remote management etc.) > *3)* this APU is A10-5750M, the most powerful mobile APU among Richland > designs - as result, this laptop is still very competitive regarding its > performance, and also price/performance > *4)* Unlike the older HP M6-1035DX amd laptop, Lenovo G505S seems to be a > very popular model: even now, more than 1.5 years after its' introduction, > there are >200 Internet shops in my large city still selling it new in box > - not used/refurbished > *5)* Lenovo G505s works without microcode updates, and already has a > working Coreboot build (although Video BIOS and SMU firmware have blobs > that are still not reverse-engineered; and some minor issues - e.g. ACPI > not perfect yet ) > > These great points are making me wonder, why this interesting laptop still > haven't been added to that LTS Candidates list? Does it fail to meet some > requirement for LTS candidates in a not-obvious way > (RYF-certifiable,Sturdy,Long shelf-life,Cool factor) or there is some > not-listed AMD laptop that could be a better candidate? > > By the way, I have discovered that there are many modifications of Lenovo > G505S, which could be divided into three primary groups by their major > difference - GPU *(minor differences, such as different size of RAM or > hard drive, are not interesting)* > GPU modification groups: > *1)* only 8650G, which is built-in into APU (no dual graphics) > *2)* 8650G + AMD HD 8570M (dual graphics) > *3)* 8650G + AMD R5 M230 ( dual graphics, slightly more powerful than > "2)" ) > Are these modifications all supported by Coreboot? And would be there any > additional difficulties regarding modifications with dual graphics? > > Your answers and opinions will be very welcome > Best regards, > Vladimir Shipovalov > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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Lenovo G505S and Coreboot LTS Candidates list
by Vladimir 06 Apr '15

06 Apr '15

Dear coreboot developers, Francis Rowe (main Libreboot developer) has hinted an idea about adding Lenovo G505S to Coreboot LTS Candidates list of laptops, which is hosted at MrNuke's User talk coreboot wiki page. I believe it is an excellent idea, because: *1)* Lenovo G505S contains AMD APU, so there is no need to deal with Intel ME/AMT so-called "features" *2)* this APU has Richland architecture: as result (unlike the more recent AMD offerings) it doesn't have "AMD Secure" feature -- based on ARM Trustzone technology which already has some exploits against it; there are security concerns about ARM Trustzone that are similar to concerns about Intel vPro "feature" (remote management etc.) *3)* this APU is A10-5750M, the most powerful mobile APU among Richland designs - as result, this laptop is still very competitive regarding its performance, and also price/performance *4)* Unlike the older HP M6-1035DX amd laptop, Lenovo G505S seems to be a very popular model: even now, more than 1.5 years after its' introduction, there are >200 Internet shops in my large city still selling it new in box - not used/refurbished *5)* Lenovo G505s works without microcode updates, and already has a working Coreboot build (although Video BIOS and SMU firmware have blobs that are still not reverse-engineered; and some minor issues - e.g. ACPI not perfect yet ) These great points are making me wonder, why this interesting laptop still haven't been added to that LTS Candidates list? Does it fail to meet some requirement for LTS candidates in a not-obvious way (RYF-certifiable,Sturdy,Long shelf-life,Cool factor) or there is some not-listed AMD laptop that could be a better candidate? By the way, I have discovered that there are many modifications of Lenovo G505S, which could be divided into three primary groups by their major difference - GPU *(minor differences, such as different size of RAM or hard drive, are not interesting)* GPU modification groups: *1)* only 8650G, which is built-in into APU (no dual graphics) *2)* 8650G + AMD HD 8570M (dual graphics) *3)* 8650G + AMD R5 M230 ( dual graphics, slightly more powerful than "2)" ) Are these modifications all supported by Coreboot? And would be there any additional difficulties regarding modifications with dual graphics? Your answers and opinions will be very welcome Best regards, Vladimir Shipovalov

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 05 Apr '15

05 Apr '15

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 9 new defect(s) introduced to coreboot found with Coverity Scan. 3 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 9 of 9 defect(s) ** CID 1293141: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /src/soc/rockchip/rk3288/sdram.c: 1027 in sdram_init() ________________________________________________________________________________________________________ *** CID 1293141: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /src/soc/rockchip/rk3288/sdram.c: 1027 in sdram_init() 1021 1022 if (sdram_params->dramtype == LPDDR3) { 1023 /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ 1024 udelay(10); 1025 send_command(ddr_pctl_regs, 1026 (sdram_params->ch[channel].rank | 1), >>> CID 1293141: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "(176 /* (0xb & 0xff) << 4 */) | sdram_params->odt" is always true regardless of the values of its operands. This occurs as the logical first operand of '?:'. 1027 MRS_CMD, LPDDR2_MA(11) | 1028 sdram_params->odt ? LPDDR2_OP(3) : 0); 1029 if (channel == 0) { 1030 writel(0, &ddr_pctl_regs->mrrcfg0); 1031 send_command(ddr_pctl_regs, 1, MRR_CMD, 1032 LPDDR2_MA(0x8)); ** CID 1293140: Control flow issues (DEADCODE) /src/soc/nvidia/tegra124/dp.c: 784 in tegra_dp_channel_eq_status() ________________________________________________________________________________________________________ *** CID 1293140: Control flow issues (DEADCODE) /src/soc/nvidia/tegra124/dp.c: 784 in tegra_dp_channel_eq_status() 778 u8 ce_done = 1; 779 780 for (cnt = 0; cnt < n_lanes / 2; cnt++) { 781 tegra_dc_dp_dpcd_read(dp, (NV_DPCD_LANE0_1_STATUS + cnt), &data); 782 783 if (n_lanes == 1) { >>> CID 1293140: Control flow issues (DEADCODE) >>> Execution cannot reach the expression "ce_done" inside this statement: "ce_done = data & 2 && data ...". 784 ce_done = (data & 785 (0x1 << NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT)) && 786 (data & (0x1 << NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT)); 787 break; 788 } else if (!(data & (0x1 << NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT)) || 789 !(data & (0x1 << NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT)) || ** CID 1293139: Control flow issues (DEADCODE) /src/soc/intel/broadwell/pcie.c: 112 in pcie_iosf_port_grant_count() ________________________________________________________________________________________________________ *** CID 1293139: Control flow issues (DEADCODE) /src/soc/intel/broadwell/pcie.c: 112 in pcie_iosf_port_grant_count() 106 107 switch (rpcd) { 108 case 1: 109 case 3: 110 update_val = 0x02; 111 break; >>> CID 1293139: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "case 2U:". 112 case 2: 113 update_val = 0x22; 114 break; 115 default: 116 update_val = 0x00; 117 break; ** CID 1293138: Control flow issues (DEADCODE) /src/soc/nvidia/tegra124/dp.c: 815 in tegra_dp_clock_recovery_status() ________________________________________________________________________________________________________ *** CID 1293138: Control flow issues (DEADCODE) /src/soc/nvidia/tegra124/dp.c: 815 in tegra_dp_clock_recovery_status() 809 810 for (cnt = 0; cnt < n_lanes / 2; cnt++) { 811 tegra_dc_dp_dpcd_read(dp, 812 (NV_DPCD_LANE0_1_STATUS + cnt), &data_ptr); 813 814 if (n_lanes == 1) >>> CID 1293138: Control flow issues (DEADCODE) >>> Execution cannot reach the expression "data_ptr & 1" inside this statement: "return (data_ptr & 1) ? 1 : 0;". 815 return (data_ptr & NV_DPCD_STATUS_LANEX_CR_DONE_YES) ? 1 : 0; 816 else if (!(data_ptr & NV_DPCD_STATUS_LANEX_CR_DONE_YES) || 817 !(data_ptr & 818 (NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES))) 819 return 0; 820 } ** CID 1293137: Control flow issues (MISSING_BREAK) /src/soc/nvidia/tegra124/sor.c: 849 in tegra_dc_sor_set_voltage_swing() ________________________________________________________________________________________________________ *** CID 1293137: Control flow issues (MISSING_BREAK) /src/soc/nvidia/tegra124/sor.c: 849 in tegra_dc_sor_set_voltage_swing() 843 case SOR_LINK_SPEED_G2_7: 844 drive_current = 0x13131313; 845 pre_emphasis = 0; 846 break; 847 case SOR_LINK_SPEED_G5_4: 848 printk(BIOS_WARNING, "T124 does not support 5.4G link clock.\n"); >>> CID 1293137: Control flow issues (MISSING_BREAK) >>> The above case falls through to this one. 849 default: 850 printk(BIOS_WARNING, "Invalid sor link bandwidth: %d\n", 851 sor->link_cfg->link_bw); 852 return; 853 } 854 ** CID 1293136: Control flow issues (NESTING_INDENT_MISMATCH) /src/arch/arm64/boot.c: 73 in arch_prog_run() ________________________________________________________________________________________________________ *** CID 1293136: Control flow issues (NESTING_INDENT_MISMATCH) /src/arch/arm64/boot.c: 73 in arch_prog_run() 67 { 68 void (*doit)(void *); 69 void *arg; 70 71 if (ENV_RAMSTAGE && prog->type == PROG_PAYLOAD) 72 run_payload(prog); >>> CID 1293136: Control flow issues (NESTING_INDENT_MISMATCH) >>> This statement is indented to column 17, as if it were nested within the preceding parent statement, but it is not. 73 return; 74 75 doit = prog_entry(prog); 76 arg = prog_entry_arg(prog); 77 78 doit(prog_entry_arg(prog)); ** CID 1293135: Incorrect expression (NO_EFFECT) /src/northbridge/amd/amdfam10/raminit_amdmct.c: 215 in amdmct_cbmem_store_info() ________________________________________________________________________________________________________ *** CID 1293135: Incorrect expression (NO_EFFECT) /src/northbridge/amd/amdfam10/raminit_amdmct.c: 215 in amdmct_cbmem_store_info() 209 { 210 /* Save memory info structures for use in ramstage */ 211 size_t i; 212 struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat); 213 struct DCTStatStruc *pDCTstatA = NULL; 214 >>> CID 1293135: Incorrect expression (NO_EFFECT) >>> Comparing an array to null is not useful: "sysinfo->DCTstatA". 215 if (pMCTstat && sysinfo->DCTstatA) { 216 /* Allocate memory */ 217 struct amdmct_memory_info* mem_info; 218 mem_info = cbmem_add(CBMEM_ID_AMDMCT_MEMINFO, sizeof(struct amdmct_memory_info)); 219 if (!mem_info) 220 return; ** CID 1293134: Uninitialized variables (UNINIT) /src/soc/intel/broadwell/pcie.c: 126 in root_port_init_config() ________________________________________________________________________________________________________ *** CID 1293134: Uninitialized variables (UNINIT) /src/soc/intel/broadwell/pcie.c: 126 in root_port_init_config() 120 RCBA32(0x103C) = (RCBA32(0x103C) & (~0xff)) | update_val; 121 } 122 123 static void root_port_init_config(device_t dev) 124 { 125 int rp; >>> CID 1293134: Uninitialized variables (UNINIT) >>> Declaring variable "data" without initializer. 126 u32 data; 127 u8 resp, id; 128 129 if (root_port_is_first(dev)) { 130 rpc.orig_rpfn = RCBA32(RPFN); 131 rpc.new_rpfn = rpc.orig_rpfn; ** CID 1293133: Control flow issues (UNREACHABLE) /src/arch/arm64/boot.c: 75 in arch_prog_run() ________________________________________________________________________________________________________ *** CID 1293133: Control flow issues (UNREACHABLE) /src/arch/arm64/boot.c: 75 in arch_prog_run() 69 void *arg; 70 71 if (ENV_RAMSTAGE && prog->type == PROG_PAYLOAD) 72 run_payload(prog); 73 return; 74 >>> CID 1293133: Control flow issues (UNREACHABLE) >>> This code cannot be reached: "doit = prog_entry(prog);". 75 doit = prog_entry(prog); 76 arg = prog_entry_arg(prog); 77 78 doit(prog_entry_arg(prog)); ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/1016?tab=overview To manage Coverity Scan email notifications for "coreboot(a)coreboot.org", click https://scan.coverity.com/subscriptions/edit?email=coreboot%40coreboot.org&… .

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Re: [coreboot] Coreboot reproducible builds
by Alexander Couzens 04 Apr '15

04 Apr '15

Hi Emilian, I chatted today with Holger from reproducible.debian.net and couldn't resist doing reproducible builds ;). These patches need additonal work, but they are working when the git tree is clean. You can test coreboot reproducible when building without payload. Or a more advanced way integrate my seabios git-tree into coreboot's payload target. coreboot needs 2 patches (one is very dirty ;) to build reproducible. http://review.coreboot.org/#/c/8611/ http://review.coreboot.org/#/c/8612/ SeaBIOS requires one patch. https://github.com/lynxis/seabios/commit/487ef74fc6cb1b1020fb25c9bb3f166602… Best, lynxis

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Re: [coreboot] How can I load SeaBIOS from GRUB with native VGA+VGA option ROM
by Peter Stuge 04 Apr '15

04 Apr '15

Iru Cai wrote: > I read previous config files from board status, and configured my Lenovo > ThinkPad X220 with CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT and > CONFIG_VGA_ROM_RUN. Unless you know why exactly you should do things any other way, always let SeaBIOS run option ROMs, never coreboot. //Peter

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Re: [coreboot] Trouble with Coreboot on Lenovo G505s
by Vladimir 04 Apr '15

04 Apr '15

Very sorry to hear that your LCD backlight problem is not resolved yet! Are you confident that LCD backlight is not faulty, and have you tried reinstalling coreboot? If answer for both questions is "yes", then you could try these two advices: 1) Redownload a source code of coreboot from github, compile it and flash again to your G505s. Since your last try - at the end of January - there were 5 commits to "coreboot/src/mainboard/lenovo/g505s" branch, and also some commits to the common branches, changes that affect all the mainboards supported by coreboot. Maybe your issue will be resolved if you would try coreboot again, with latest sources! 2) If 1st advice doesn't work, you could open "coreboot/src/mainboard/lenovo/g505s/buildOpts.c" file (which is the only file from G505s branch that has a reference to "LCD") Go to line 158, try to change the "#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200" parameter. Default value seems to be 200 for most platforms, but you could try setting it to 0. Then compile & flash again === Any advices from experienced coreboot members would be very welcome! === On 3 April 2015 at 17:46, 1 1 <zilogpnz(a)gmail.com> wrote: > No. I not solved this problem. > > 2015-04-03 17:08 GMT+04:00 Vladimir <quickcracktime(a)gmail.com>: > >> > On Mon Jan 26 13:07:42 CET 2015 zilogpnz wrote: >> >> I'm trying to run Coreboot on Lenovo G505s and have a problem: >> >> - backlight of LCD is not turn on. But on the external LCD (by CRT >> >> connector) is all good. >> >> >> >> Could you help me with a solution to this problem? >> >> >> Sorry for such a long reply, but what is a current status of this problem? >> Have you resolved the LCD backlight problem with your G505s - and, if >> yes, how? >> > >

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Re: [coreboot] Trouble with Coreboot on Lenovo G505s
by Vladimir 04 Apr '15

04 Apr '15

Very sorry to hear that your LCD backlight problem is not resolved yet! Are you confident that LCD backlight is not faulty, and have you tried reinstalling coreboot? If answer for both questions is "yes" - then you could try these two advices: 1) Re-download a source code of coreboot from github, compile it and flash again to your G505s. Since your last try - at the end of January - there were 5 commits to "coreboot/src/mainboard/lenovo/g505s" branch, and also some commits to the common branches, changes that affect all the mainboards supported by coreboot. Maybe your issue will be resolved if you would try coreboot again, with latest sources! 2) If 1st advice doesn't work, you could open "coreboot/src/mainboard/lenovo/g505s/buildOpts.c" file (which is the only file from G505s branch that has a reference to "LCD") Go to line 158, try to change the "#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200" parameter. Default value seems to be 200 for most platforms, but you could try setting it to 0. Then compile & flash again === Any advices from experienced coreboot members would be very welcome! === On 3 April 2015 at 17:46, 1 1 <zilogpnz(a)gmail.com> wrote: > No. I not solved this problem. > > 2015-04-03 17:08 GMT+04:00 Vladimir <quickcracktime(a)gmail.com>: > >> > On Mon Jan 26 13:07:42 CET 2015 zilogpnz wrote: >> >> I'm trying to run Coreboot on Lenovo G505s and have a problem: >> >> - backlight of LCD is not turn on. But on the external LCD (by CRT >> >> connector) is all good. >> >> >> >> Could you help me with a solution to this problem? >> >> >> Sorry for such a long reply, but what is a current status of this problem? >> Have you resolved the LCD backlight problem with your G505s - and, if >> yes, how? >> > >

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Trouble with Coreboot on Lenovo G505s
by Vladimir 03 Apr '15

03 Apr '15

> On Mon Jan 26 13:07:42 CET 2015 zilogpnz wrote: >> I'm trying to run Coreboot on Lenovo G505s and have a problem: >> - backlight of LCD is not turn on. But on the external LCD (by CRT >> connector) is all good. >> >> Could you help me with a solution to this problem? Sorry for such a long reply, but what is a current status of this problem? Have you resolved the LCD backlight problem with your G505s - and, if yes, how?

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Re: [coreboot] VGA doesn't work on Mohon Peak
by Kuzmichev 03 Apr '15

03 Apr '15

> Please post lspci -vs 2:0.0 and/or lspci -t Here: lspci -vs 2:0.0 02:00.0 PCI bridge: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge (rev 02) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=02, secondary=03, subordinate=03, sec-latency=0 I/O behind bridge: 00002000-00002fff Memory behind bridge: 80000000-840fffff Prefetchable memory behind bridge: 0000000084100000-00000000841fffff Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Capabilities: [78] Power Management version 3 Capabilities: [80] Express PCI/PCI-X Bridge, MSI 00 Capabilities: [a4] Subsystem: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge Capabilities: [100] Virtual Channel lspci -t -[0000:00]-+-00.0 +-01.0-[01]-- +-02.0-[02-03]----00.0-[03]----00.0 +-03.0-[04-0a]----00.0-[05-0a]--+-04.0-[06]-- | +-05.0-[07-08]--+-00.0 | | \-00.1 | +-08.0-[09]-- | \-09.0-[0a]-- +-0b.0 +-0e.0 +-0f.0 +-13.0 +-14.0 +-14.1 +-14.2 +-14.3 +-16.0 +-17.0 +-18.0 +-1f.0 \-1f.3 -Viktor

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How can I load SeaBIOS from GRUB with native VGA+VGA option ROM
by Iru Cai 03 Apr '15

03 Apr '15

I read previous config files from board status, and configured my Lenovo ThinkPad X220 with CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT and CONFIG_VGA_ROM_RUN. And according to: http://www.coreboot.org/pipermail/coreboot/2014-July/078342.html I added the bios.bin.elf to GRUB and vgabios.bin to CBFS. However, after I chose SeaBIOS in GRUB, SeaBIOS was loaded and the screen became blank. I'm not sure if there's something wrong with option ROM and SeaBIOS.

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coreboot April 2015