coreboot April 2015

coreboot@coreboot.org

54 participants
92 discussions

Re: [coreboot] Lenovo G505S and Coreboot LTS Candidates list
by Alexandru Gagniuc 11 Apr '15

11 Apr '15

On Monday, April 06, 2015 01:45:32 PM Vladimir wrote: > Dear coreboot developers, > > Francis Rowe (main Libreboot developer) has hinted an idea about adding > Lenovo G505S to Coreboot LTS Candidates list of laptops, which is hosted at > MrNuke's User talk coreboot wiki page. I believe it is an excellent idea, > because: > You are free to add it, but keep in mind that anything with an AMD APU will fail the RYF-certifiable criteria due to SMU and atombios. If we're going to lower the bar, we should also consider Librem 15. At least that one has (should have) a much more durable construction and much better screen. If those guys aren't as full of it as they sound, and have figured out how to fuse the PCH to disable ME, then RYF'ing a Librem should be less work than anything APU. > Best regards, Alex

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Re: [coreboot] 'power on after fail' on Panther (Haswell/Lynxpoint)
by Matt DeVillier 11 Apr '15

11 Apr '15

On 4/9/2015 1:21 PM, Duncan Laurie wrote: > [I got a bounce when sending this so trying again] > > I think you should be able to alter the behavior with the 0xf2 and 0xf4 registers in the LDN4 block. > > Right now mainboard/google/panther/devicetree.cb has this: > > device pnp 2e.4 on # Environment Controller > io 0x60 = 0x700 > io 0x62 = 0x710 > irq 0x70 = 0x09 > irq 0xf2 = 0x20 <<<<< PCR 1 > irq 0xf4 = 0x0 <<<<< PCR 2 > irq 0xfa = 0x12 > end > > 0xf2 bit 5 and 0xf4 bit 5,6 should have some effect on this behavior. > > F4<5> and F2<5>: > 1 X : Always ON > 0 1 : Memory > 0 0 : Always OFF > > And then F4<6> seems to be the bit that gates the PWRON pulse from the superio and lets the southbridge control the default behavior. > > I think if you set "irq 0xf2 = 0x20" (in theory if the datasheet is right F2<5> doesn't matter for always on) and "irq 0xf4 = 0x20" and then do not call it8772f_ac_resume_southbridge() (which is setting 0xf4=0x60) it should let the superio control the behavior and always power on when AC Is attached. that seems to have done the trick, thanks! I was misunderstanding the functionality of F4<5>, appreciate the clarification > > One other thing to try is to remove the RTC battery and let it reset the superio state after you have things configured as desired. didn't have to do this, just powered off fully after flashing > > -duncan > > > On Thu, Apr 9, 2015 at 10:15 AM, Matt DeVillier <matt.devillier(a)gmail.com <mailto:matt.devillier@gmail.com>> wrote: > > Duncan, > > took a look at the IT8772F data sheet (well, 8712, closest I could find: http://www.hardwaresecrets.com/datasheets/it8712f.pdf ) and it seems that there's no setting of the PCR1/2 registers that will force #PSON high when AC power is applied - it's always conditional on the previous system power state. > > I'd be happy for someone else to take a look and tell me I'm misreading though :) > > cheers, > Matt > > > On 3/26/2015 5:21 PM, Matt DeVillier wrote: >> On 3/26/2015 9:49 AM, Duncan Laurie wrote: >>> On Wed, Mar 25, 2015 at 11:35 PM, Matt DeVillier <matt.devillier(a)gmail.com <mailto:matt.devillier@gmail.com>> wrote: >>> >>> Greetings all! >>> >>> I was wondering if it's possible to have Panther (Asus ChromeBox - Haswell/Lynxpoint) power on when AC power connected regardless of the previous power state. Currently, the box will power on if AC power is lost and the device was powered on, but not if powered off. I have a use case where it would be convenient to be able to power on the boxes by toggling AC power (eg, the boxes are not within physical reach). I modified the CMOS default setting for 'power_on_after_fail' to be enabled and verified its status with nvramtool. I also tried modifying lpc.c/smihandler.c in the southbridge code to force MAINBOARD_POWER_ON (rather than MAINBOARD_POWER_KEEP) in all cases, to no avail. >>> >>> Am I approaching this from the wrong angle, or is it perhaps not possible with these boxes? >>> >>> >>> >>> This might be due to the SuperIO instead of the Southbridge. Panther does call it8772f_ac_resume_southbridge() which *should* be making the southbridge the one responsible for the power behavior when AC is applied, but as a first test you could try removing that call to see if the default SuperIO behavior is closer to what you want. >> >> Hi Duncan, I tried removing the call as suggested, but it didn't change the behavior at all. Any thoughts as to where to look next? >> >> thanks! >> -Matt >> >>> >>> -duncan >>> >> > >

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Re: [coreboot] Will coreboot work on my machine?
by camrodgers21＠gmail.com 11 Apr '15

11 Apr '15

Thanks for the response. I'm not a developer but I've been playing with the idea of learning C. Maybe having a project like this will give me a good reason and the motivation to do it. On Fri, Apr 10, 2015 at 10:39:15PM -0700, David Hendricks wrote: > Seems like it might work, if you are willing to put in the time and effort > to attempt a port. The VX800 and Nano are already supported in coreboot. > The EC will be the tricky part, since I don't think any other Coreboot > supported laptop uses it. > > On Fri, Apr 10, 2015 at 9:26 PM, <camrodgers21(a)gmail.com> wrote: > > > Lenovo IdeaPad S12 > > VIA Nano processor U2250 (1.6GHz Capable) > > http://www.via.com.tw/en/products/chipsets/v-series/vx800/ > > > > lspci -tvnn: > > > > -[0000:00]-+-00.0 VIA Technologies, Inc. VX800 Host Bridge [1106:0353] > > +-00.1 VIA Technologies, Inc. VX800/VX820 Error Reporting > > [1106:1353] > > +-00.2 VIA Technologies, Inc. VX800/VX820 Host Bus Control > > [1106:2353] > > +-00.3 VIA Technologies, Inc. VX800 PCI to PCI Bridge > > [1106:3353] > > +-00.4 VIA Technologies, Inc. VX800/VX820 Power Management > > Control [1106:4353] > > +-00.5 VIA Technologies, Inc. VX800/VX820 APIC and Central > > Traffic Control [1106:5353] > > +-00.6 VIA Technologies, Inc. VX800/VX820 Scratch Registers > > [1106:6353] > > +-00.7 VIA Technologies, Inc. VX800/VX820 North-South Module > > Interface Control [1106:7353] > > +-01.0 VIA Technologies, Inc. VX800/VX820 Chrome 9 HC3 > > Integrated Graphics [1106:1122] > > +-02.0-[01]----00.0 Broadcom Corporation NetLink BCM5906M Fast > > Ethernet PCI Express [14e4:1713] > > +-03.0-[02]----00.0 Intel Corporation PRO/Wireless 5100 AGN > > [Shiloh] Network Connection [8086:4237] > > +-03.1-[03-05]-- > > +-0d.0 VIA Technologies, Inc. Secure Digital Memory Card > > Controller [1106:9530] > > +-0f.0 VIA Technologies, Inc. VX800 Serial ATA and EIDE > > Controller [1106:5324] > > +-10.0 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 > > Controller [1106:3038] > > +-10.1 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 > > Controller [1106:3038] > > +-10.2 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 > > Controller [1106:3038] > > +-10.4 VIA Technologies, Inc. USB 2.0 [1106:3104] > > +-11.0 VIA Technologies, Inc. VX800/VX820 Bus Control and > > Power Management [1106:8353] > > +-11.7 VIA Technologies, Inc. VX8xx South-North Module > > Interface Control [1106:a353] > > +-13.0-[06]-- > > \-14.0 VIA Technologies, Inc. VT8237A/VT8251 HDA Controller > > [1106:3288] > > > > superiotool -dV: > > > > superiotool r > > Probing for ALi Super I/O at 0x3f0... > > Failed. Returned data: id=0xffff, rev=0xff > > Probing for ALi Super I/O at 0x370... > > Failed. Returned data: id=0xffff, rev=0xff > > Probing for Fintek Super I/O at 0x2e... > > Failed. Returned data: vid=0xffff, id=0xffff > > Probing for Fintek Super I/O at 0x4e... > > Failed. Returned data: vid=0x0000, id=0x11fc > > Probing for Fintek Super I/O at 0x2e... > > Failed. Returned data: vid=0xffff, id=0xffff > > Probing for Fintek Super I/O at 0x4e... > > Failed. Returned data: vid=0x0000, id=0x11fc > > Probing for ITE Super I/O (init=standard) at 0x20e... > > Failed. Returned data: id=0xffff, rev=0xf > > Probing for ITE Super I/O (init=it8502e) at 0x20e... > > Failed. Returned data: id=0xffff, rev=0xf > > Probing for ITE Super I/O (init=it8761e) at 0x20e... > > Failed. Returned data: id=0xffff, rev=0xf > > Probing for ITE Super I/O (init=it8228e) at 0x20e... > > Failed. Returned data: id=0xffff, rev=0xf > > Probing for ITE Super I/O (init=0x87,0x87) at 0x20e... > > Failed. Returned data: id=0xffff, rev=0xf > > Probing for ITE Super I/O (init=standard) at 0x25e... > > Failed. Returned data: id=0xffff, rev=0xf > > Probing for ITE Super I/O (init=it8502e) at 0x25e... > > Failed. Returned data: id=0xffff, rev=0xf > > Probing for ITE Super I/O (init=it8761e) at 0x25e... > > Failed. Returned data: id=0xffff, rev=0xf > > Probing for ITE Super I/O (init=it8228e) at 0x25e... > > Failed. Returned data: id=0xffff, rev=0xf > > Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... > > Failed. Returned data: id=0xffff, rev=0xf > > Probing for ITE Super I/O (init=standard) at 0x2e... > > Failed. Returned data: id=0xffff, rev=0xf > > Probing for ITE Super I/O (init=it8502e) at 0x2e... > > Failed. Returned data: id=0xffff, rev=0xf > > Probing for ITE Super I/O (init=it8761e) at 0x2e... > > Failed. Returned data: id=0xffff, rev=0xf > > Probing for ITE Super I/O (init=it8228e) at 0x2e... > > Failed. Returned data: id=0xffff, rev=0xf > > Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... > > Failed. Returned data: id=0xffff, rev=0xf > > Probing for ITE Super I/O (init=standard) at 0x4e... > > Failed. Returned data: id=0xfc11, rev=0x0 > > Probing for ITE Super I/O (init=it8502e) at 0x4e... > > Failed. Returned data: id=0xfc11, rev=0x0 > > Probing for ITE Super I/O (init=it8761e) at 0x4e... > > Failed. Returned data: id=0xfc11, rev=0x0 > > Probing for ITE Super I/O (init=it8228e) at 0x4e... > > Failed. Returned data: id=0xfc11, rev=0x0 > > Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... > > Failed. Returned data: id=0xfc11, rev=0x0 > > Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... > > Failed. Returned data: id=0xffff, rev=0xf > > Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... > > Failed. Returned data: id=0xffff, rev=0xf > > Probing for NSC Super I/O at 0x2e... > > Failed. Returned data: port=0xff, port+1=0xff > > Probing for NSC Super I/O at 0x4e... > > Failed. Returned data: sid=0xfc, srid=0xa2 > > Probing for NSC Super I/O at 0x15c... > > Failed. Returned data: port=0xff, port+1=0xff > > Probing for NSC Super I/O at 0x164e... > > Failed. Returned data: port=0xff, port+1=0xff > > Probing for Nuvoton Super I/O at 0x164e... > > Failed. Returned data: chip_id=0xffff > > Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... > > Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 > > Probing for Nuvoton Super I/O at 0x2e... > > Failed. Returned data: chip_id=0xffff > > Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... > > Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 > > Probing for Nuvoton Super I/O at 0x4e... > > Failed. Returned data: chip_id=0xfc11 > > Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e... > > Found Nuvoton WPCE775x / NPCE781x (id=0x05, rev=0x02) at 0x4e > > Register dump: > > idx 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f > > val fc 11 00 00 00 00 00 a2 00 1c 00 00 00 00 00 00 > > def fc 11 RR RR RR 00 00 MM 00 04 RR RR RR 00 RR RR > > LDN 0x03 (CIR Port (CIRP)) > > idx 30 60 61 70 71 74 75 f0 > > val 00 03 f8 04 03 04 04 02 > > def 00 03 f8 04 03 04 04 02 > > LDN 0x04 (Mobile System Wake-Up Control Config (MSWC)) > > idx 30 60 61 70 71 74 75 > > val 00 00 00 00 03 04 04 > > def 00 00 00 00 03 04 04 > > LDN 0x05 (Mouse config (KBC)) > > idx 30 70 71 74 75 > > val 01 0c 03 04 04 > > def 00 0c 03 04 04 > > LDN 0x06 (Keyboard config (KBC)) > > idx 30 60 61 62 63 70 71 74 75 > > val 01 00 60 00 64 01 03 04 04 > > def 00 00 60 00 64 01 03 04 04 > > LDN 0x0f (Shared memory (SHM)) > > idx 30 60 61 70 71 74 75 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb > > val 01 16 00 00 00 04 04 e9 0a 00 00 00 00 02 00 00 00 80 ff > > def 00 00 00 00 00 04 04 MM 07 RR RR 00 00 00 00 00 00 00 00 > > LDN 0x11 (Power management I/F Channel 1 (PM1)) > > idx 30 60 61 62 63 70 71 74 75 > > val 01 00 62 00 66 00 03 04 04 > > def 00 00 62 00 66 01 03 04 04 > > LDN 0x12 (Power management I/F Channel 2 (PM2)) > > idx 30 60 61 62 63 70 71 74 75 > > val 01 00 68 00 6c 00 03 04 04 > > def 00 00 68 00 6c 01 03 04 04 > > LDN 0x15 (Enhanced Wake On CIR (EWOC)) > > idx 30 60 61 62 63 70 71 74 75 > > val 00 00 00 00 00 00 03 04 04 > > def 00 00 00 00 00 00 03 04 04 > > LDN 0x17 (Power Management I/F Channel 3 (PM3)) > > idx 30 60 61 62 63 70 71 74 75 > > val 01 00 6a 00 6e 00 03 04 04 > > def 00 00 6a 00 6e 01 03 04 04 > > LDN 0x1a (Serial Port with Fast Infrared Port (FIR)) > > idx 30 60 61 70 71 74 75 f0 > > val 00 02 f8 03 03 04 04 02 > > def 00 02 f8 03 03 04 04 02 > > Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... > > Failed. Returned data: id=0xff, rev=0xff > > Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... > > Failed. Returned data: id=0xff, rev=0xff > > Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... > > Failed. Returned data: id=0xfc, rev=0x11 > > Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... > > Failed. Returned data: id=0x00, rev=0x00 > > Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... > > Failed. Returned data: id=0xff, rev=0xff > > Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... > > Failed. Returned data: id=0xff, rev=0xff > > Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... > > Failed. Returned data: id=0xff, rev=0xff > > Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... > > Failed. Returned data: id=0xff, rev=0xff > > Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... > > Failed. Returned data: id=0xff, rev=0xff > > Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... > > Failed. Returned data: id=0xff, rev=0xff > > Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... > > Failed. Returned data: id=0xff, rev=0xff > > Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... > > Failed. Returned data: id=0xff, rev=0xff > > Probing for Winbond Super I/O (init=0x88) at 0x2e... > > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > > Probing for Winbond Super I/O (init=0x89) at 0x2e... > > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > > Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... > > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > > Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... > > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > > Probing for Winbond Super I/O (init=0x88) at 0x4e... > > Failed. Returned data: id/oldid=0xfc/0x00, rev=0x11 > > Probing for Winbond Super I/O (init=0x89) at 0x4e... > > Failed. Returned data: id/oldid=0xfc/0x00, rev=0x11 > > Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... > > Failed. Returned data: id/oldid=0xfc/0x00, rev=0x11 > > Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... > > Failed. Returned data: id/oldid=0xfc/0x00, rev=0x11 > > Probing for Winbond Super I/O (init=0x88) at 0x3f0... > > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > > Probing for Winbond Super I/O (init=0x89) at 0x3f0... > > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > > Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... > > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > > Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... > > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > > Probing for Winbond Super I/O (init=0x88) at 0x370... > > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > > Probing for Winbond Super I/O (init=0x89) at 0x370... > > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > > Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... > > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > > Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... > > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > > Probing for Winbond Super I/O (init=0x88) at 0x250... > > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > > Probing for Winbond Super I/O (init=0x89) at 0x250... > > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > > Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... > > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > > Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... > > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > > Probing for VIA Super I/O at 0x3f0... > > PCI device 1106:0686 not found. > > Probing for AMD EC Super I/O at 0xaa... > > Probing for Server Engines Super I/O at 0x2e... > > Failed. Returned data: id=0xffff, rev=0xff > > Probing for Infineon Super I/O at 0x2e... > > Failed. Returned data: id=0xff, rev=0xff > > Probing for Infineon Super I/O at 0x4e... > > Failed. Returned data: id=0xfc, rev=0x11 > > > > flashrom -p internal -V: > > > > flashrom v0.9.7-r1858 on Linux 3.19.3-gnu-grsec (i686) > > flashrom is free software, get the source code at http://www.flashrom.org > > > > > > flashrom was built with libpci 3.2.1, GCC 4.8.2, little endian > > Command line (3 args): ./flashrom -p internal -V > > Calibrating delay loop... OS timer resolution is 1 usecs, 177M loops per > > second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 1006 us, 10000 myus > > = 10040 us, 4 myus = 5 us, OK. > > Initializing internal programmer > > No coreboot table found. > > Using Internal DMI decoder. > > DMI string chassis-type: "Notebook" > > Laptop detected via DMI. > > DMI string system-manufacturer: "LENOVO" > > DMI string system-product-name: "20021,2959" > > DMI string system-version: "Lenovo Ideapad S12" > > DMI string baseboard-manufacturer: "LENOVO" > > DMI string baseboard-product-name: "MoutCook" > > DMI string baseboard-version: "Not Applicable" > > W836xx enter config mode worked or we were already in config mode. W836xx > > leave config mode had no effect. > > Active config mode, unknown reg 0x20 ID: fc. > > Please send the output of "flashrom -V -p internal" to > > flashrom(a)flashrom.org with W836xx: your board name: flashrom -V > > as the subject to help us finish support for your Super I/O. Thanks. > > > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > > > > > > -- > David Hendricks (dhendrix) > Systems Software Engineer, Google Inc.

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Will coreboot work on my machine?
by camrodgers21＠gmail.com 11 Apr '15

11 Apr '15

Lenovo IdeaPad S12 VIA Nano processor U2250 (1.6GHz Capable) http://www.via.com.tw/en/products/chipsets/v-series/vx800/ lspci -tvnn: -[0000:00]-+-00.0 VIA Technologies, Inc. VX800 Host Bridge [1106:0353] +-00.1 VIA Technologies, Inc. VX800/VX820 Error Reporting [1106:1353] +-00.2 VIA Technologies, Inc. VX800/VX820 Host Bus Control [1106:2353] +-00.3 VIA Technologies, Inc. VX800 PCI to PCI Bridge [1106:3353] +-00.4 VIA Technologies, Inc. VX800/VX820 Power Management Control [1106:4353] +-00.5 VIA Technologies, Inc. VX800/VX820 APIC and Central Traffic Control [1106:5353] +-00.6 VIA Technologies, Inc. VX800/VX820 Scratch Registers [1106:6353] +-00.7 VIA Technologies, Inc. VX800/VX820 North-South Module Interface Control [1106:7353] +-01.0 VIA Technologies, Inc. VX800/VX820 Chrome 9 HC3 Integrated Graphics [1106:1122] +-02.0-[01]----00.0 Broadcom Corporation NetLink BCM5906M Fast Ethernet PCI Express [14e4:1713] +-03.0-[02]----00.0 Intel Corporation PRO/Wireless 5100 AGN [Shiloh] Network Connection [8086:4237] +-03.1-[03-05]-- +-0d.0 VIA Technologies, Inc. Secure Digital Memory Card Controller [1106:9530] +-0f.0 VIA Technologies, Inc. VX800 Serial ATA and EIDE Controller [1106:5324] +-10.0 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] +-10.1 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] +-10.2 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] +-10.4 VIA Technologies, Inc. USB 2.0 [1106:3104] +-11.0 VIA Technologies, Inc. VX800/VX820 Bus Control and Power Management [1106:8353] +-11.7 VIA Technologies, Inc. VX8xx South-North Module Interface Control [1106:a353] +-13.0-[06]-- \-14.0 VIA Technologies, Inc. VT8237A/VT8251 HDA Controller [1106:3288] superiotool -dV: superiotool r Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0x0000, id=0x11fc Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0x0000, id=0x11fc Probing for ITE Super I/O (init=standard) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xfc11, rev=0x0 Probing for ITE Super I/O (init=it8502e) at 0x4e... Failed. Returned data: id=0xfc11, rev=0x0 Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xfc11, rev=0x0 Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xfc11, rev=0x0 Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xfc11, rev=0x0 Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: sid=0xfc, srid=0xa2 Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x164e... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O at 0x164e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x2e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x4e... Failed. Returned data: chip_id=0xfc11 Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e... Found Nuvoton WPCE775x / NPCE781x (id=0x05, rev=0x02) at 0x4e Register dump: idx 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f val fc 11 00 00 00 00 00 a2 00 1c 00 00 00 00 00 00 def fc 11 RR RR RR 00 00 MM 00 04 RR RR RR 00 RR RR LDN 0x03 (CIR Port (CIRP)) idx 30 60 61 70 71 74 75 f0 val 00 03 f8 04 03 04 04 02 def 00 03 f8 04 03 04 04 02 LDN 0x04 (Mobile System Wake-Up Control Config (MSWC)) idx 30 60 61 70 71 74 75 val 00 00 00 00 03 04 04 def 00 00 00 00 03 04 04 LDN 0x05 (Mouse config (KBC)) idx 30 70 71 74 75 val 01 0c 03 04 04 def 00 0c 03 04 04 LDN 0x06 (Keyboard config (KBC)) idx 30 60 61 62 63 70 71 74 75 val 01 00 60 00 64 01 03 04 04 def 00 00 60 00 64 01 03 04 04 LDN 0x0f (Shared memory (SHM)) idx 30 60 61 70 71 74 75 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb val 01 16 00 00 00 04 04 e9 0a 00 00 00 00 02 00 00 00 80 ff def 00 00 00 00 00 04 04 MM 07 RR RR 00 00 00 00 00 00 00 00 LDN 0x11 (Power management I/F Channel 1 (PM1)) idx 30 60 61 62 63 70 71 74 75 val 01 00 62 00 66 00 03 04 04 def 00 00 62 00 66 01 03 04 04 LDN 0x12 (Power management I/F Channel 2 (PM2)) idx 30 60 61 62 63 70 71 74 75 val 01 00 68 00 6c 00 03 04 04 def 00 00 68 00 6c 01 03 04 04 LDN 0x15 (Enhanced Wake On CIR (EWOC)) idx 30 60 61 62 63 70 71 74 75 val 00 00 00 00 00 00 03 04 04 def 00 00 00 00 00 00 03 04 04 LDN 0x17 (Power Management I/F Channel 3 (PM3)) idx 30 60 61 62 63 70 71 74 75 val 01 00 6a 00 6e 00 03 04 04 def 00 00 6a 00 6e 01 03 04 04 LDN 0x1a (Serial Port with Fast Infrared Port (FIR)) idx 30 60 61 70 71 74 75 f0 val 00 02 f8 03 03 04 04 02 def 00 02 f8 03 03 04 04 02 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xfc, rev=0x11 Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xfc/0x00, rev=0x11 Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xfc/0x00, rev=0x11 Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xfc/0x00, rev=0x11 Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xfc/0x00, rev=0x11 Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O at 0x3f0... PCI device 1106:0686 not found. Probing for AMD EC Super I/O at 0xaa... Probing for Server Engines Super I/O at 0x2e... Failed. Returned data: id=0xffff, rev=0xff Probing for Infineon Super I/O at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for Infineon Super I/O at 0x4e... Failed. Returned data: id=0xfc, rev=0x11 flashrom -p internal -V: flashrom v0.9.7-r1858 on Linux 3.19.3-gnu-grsec (i686) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.2.1, GCC 4.8.2, little endian Command line (3 args): ./flashrom -p internal -V Calibrating delay loop... OS timer resolution is 1 usecs, 177M loops per second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 1006 us, 10000 myus = 10040 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. Using Internal DMI decoder. DMI string chassis-type: "Notebook" Laptop detected via DMI. DMI string system-manufacturer: "LENOVO" DMI string system-product-name: "20021,2959" DMI string system-version: "Lenovo Ideapad S12" DMI string baseboard-manufacturer: "LENOVO" DMI string baseboard-product-name: "MoutCook" DMI string baseboard-version: "Not Applicable" W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: fc. Please send the output of "flashrom -V -p internal" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks.

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Re: [coreboot] QEMU: Kernel hang issue "All ACPI Tables successfully acquired"
by Paul Menzel 10 Apr '15

10 Apr '15

Dear Ajoy, welcome to coreboot! Am Dienstag, den 07.04.2015, 20:56 +0530 schrieb Ajoy Das: > I am running coreboot on qemu with the following sequence. > > coreboot -> seabios -> GRUB -> kernel. > > The kernel booting hangs at *All ACPI Tables successfully acquired* > > coreboot-4.0 Please give us the hash of the commit you are using or the output of `git describe`. Please attach your config file and the output of build/cbfstool build/coreboot.rom print and also tell us your QEMU command. > kernel 3.19 Same here. Please attach the config file. > when I pass acpi=off to the kernel command line parameter the kernel boots > fine in this scenario. > > > Is there any specific coreboot option that needs to be enabled for > successful booting. > or anyone knows of this issue I haven’t heard of it and the Raptor Engineering Automated Test Stand verified the (default) QEMU boot off emulation/qemu-q35/4.0-8859-g9484f55/2015-04-06T00:21:26Z. See the board status repository for more information. Please attach the whole boot log. Thanks, Paul

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Re: [coreboot] OpenID
by Peter Stuge 10 Apr '15

10 Apr '15

Patrick Georgi via coreboot wrote: > gerrit maintenance is done, the site is back to normal. > What changed: Besides the current OpenID configuration, it's now also > possible to log in with OAuth. .. > I also considered adding GitHub as authentication provider I think it would be nice to provide authentication ourselves. If there's interest I'm happy to help duplicate the OpenID provider setup which I run on my server onto a coreboot server. Whether that happens or not, if anyone wants an OpenID from me to work on coreboot then send me your username, output from printf 'your password' | md5sum, your name, email and a URL where you can add two <link> tags to <head> - that URL will be your OpenID identity, only the login form is on my server. If you have no URL then I'll provide one. > it's not yet possible to link OAuth credentials to existing accounts It might be possible for existing users to add a new OpenID identity to their account themselves, but I'm not sure - Patrick might have to help with that if you have an existing account and want to switch the type of identity provider now. //Peter

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Re: [coreboot] 'power on after fail' on Panther (Haswell/Lynxpoint)
by Matt DeVillier 09 Apr '15

09 Apr '15

On 3/26/2015 9:49 AM, Duncan Laurie wrote: > On Wed, Mar 25, 2015 at 11:35 PM, Matt DeVillier <matt.devillier(a)gmail.com <mailto:matt.devillier@gmail.com>> wrote: > > Greetings all! > > I was wondering if it's possible to have Panther (Asus ChromeBox - Haswell/Lynxpoint) power on when AC power connected regardless of the previous power state. Currently, the box will power on if AC power is lost and the device was powered on, but not if powered off. I have a use case where it would be convenient to be able to power on the boxes by toggling AC power (eg, the boxes are not within physical reach). I modified the CMOS default setting for 'power_on_after_fail' to be enabled and verified its status with nvramtool. I also tried modifying lpc.c/smihandler.c in the southbridge code to force MAINBOARD_POWER_ON (rather than MAINBOARD_POWER_KEEP) in all cases, to no avail. > > Am I approaching this from the wrong angle, or is it perhaps not possible with these boxes? > > > > This might be due to the SuperIO instead of the Southbridge. Panther does call it8772f_ac_resume_southbridge() which *should* be making the southbridge the one responsible for the power behavior when AC is applied, but as a first test you could try removing that call to see if the default SuperIO behavior is closer to what you want. Hi Duncan, I tried removing the call as suggested, but it didn't change the behavior at all. Any thoughts as to where to look next? thanks! -Matt > > -duncan >

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memtest86 reading 0k memory
by Timothy Pearson 09 Apr '15

09 Apr '15

All, I have a board here that loads memtest86 but won't actually test memory. This is the output: Memtest86+ v2.11 AMD K10 CPU @ 2312 MHz L1 Cache: 64K 35028 MB/s L2 Cache: 512K 6963 MB/s L3 Cache: 2048K 6052 MB/s Memory : 0K |------------------------------------------------- Chipset : 0K LinuxBIOS I'm guessing memtest86 doesn't understand coreboot's memory tables/structure, but I have no idea why that would be. The e820 map is valid: e820: BIOS-provided physical RAM map: BIOS-e820: [mem 0x0000000000000000-0x000000000009fbff] usable BIOS-e820: [mem 0x000000000009fc00-0x000000000009ffff] reserved BIOS-e820: [mem 0x00000000000f0000-0x00000000000fffff] reserved BIOS-e820: [mem 0x0000000000100000-0x000000003ffacfff] usable BIOS-e820: [mem 0x000000003ffad000-0x000000003fffffff] reserved BIOS-e820: [mem 0x00000000e0000000-0x00000000efffffff] reserved Any ideas? Other than this one irritating glitch coreboot is working perfectly on this board. Thanks! -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 http://www.raptorengineeringinc.com

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Server maintenance done. Action Required for users that authenticate with Google accounts
by Patrick Georgi 09 Apr '15

09 Apr '15

Hi, gerrit maintenance is done, the site is back to normal. What changed: Besides the current OpenID configuration, it's now also possible to log in with OAuth. This change is necessary because Google will retire the OpenID authentication scheme for their users this month. I also considered adding GitHub as authentication provider but held off because it's not yet possible to link OAuth credentials to existing accounts, a bug in the authentication provider we're using (and I'm trying to avoid duplicate accounts) GitHub as authentication provider will be added as soon as the remaining issue on the server is sorted out. To retain access with a Google based account after April 19th (or so, timezones are complicated), some work is required. Even though the instructions are very detailed, it's a really quick process, so do it now! 1. Log out of review.coreboot.org (top right of the screen) 2. Log in again, select 'Google OAuth2 (gerrit-oauth-provider-plugin)' 3. Google will ask you if you want to grant 'coreboot' some limited access to your account. Acknowledge that 4. After the login is done, go to http://review.coreboot.org/#/settings/web-identities 4a. You should see a line 'Google Account' for the email address you used as identifier, and another line with the same email address and a long number is 'identity'. 5. If there are more Google Accounts in that list for which there isn't another line with a numerical identifier, repeat the process for them. After the switch-over at Google, this automatic linking of accounts may or may not stop to work (I have no idea). If you notice that you end up with a new account (http://review.coreboot.org/#/dashboard/self empty when it shouldn't be), contact me ASAP so I can link the accounts on the server side before the new account sees lots of activity. Since that's additional work for you and me, please try to avoid it :-) Thanks, Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Graham Law, Christine Elizabeth Flores

1 0

ASRock IMB-A180-H
by Stefan Tauner 08 Apr '15

08 Apr '15

Hi, I am (finally) playing a bit with coreboot. Thanks to the excellent work of Kyösti with the BBB I have USB output in place. Unfortunately what I see is not what I have hoped for... :) coreboot-4.0-8859-gbfe1b41 Sun Apr 5 21:29:27 UTC 2015 ramstage starting... BS: BS_PRE_DEVICE times (us): entry 0 run 1 exit 0 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 2 exit 0 Enumerating buses... Mainboard IMB-A180 Enable. setup_bsp_ramtop, TOP MEM: msr.lo = 0xe0000000, msr.hi = 0x00000000 setup_bsp_ramtop, TOP MEM2: msr.lo = 0x20000000, msr.hi = 0x00000001 setup_uma_memory: uma size 0x20000000, memory start 0xc0000000 CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled memalign(boundary=8, size=96): failed: Tried to round up free_mem_ptr 00173190 to 001731f0 but free_mem_end_ptr is 0017318c This is with level DEBUG/7... will recover tomorrow and can increase it if need be. I have not looked into it yet at all... but hints are welcome anyway :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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