coreboot April 2015

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QEMU x86_64 Q35 Automated Test Failure
by Raptor Engineering Automated Test Stand 21 Apr '15

21 Apr '15

The QEMU x86_64 Q35 fails verification as of commit 7ab46f8085146db57699001462da871f2e4d9965 Commits since last successful test: 7ab46f8 libpayload: add timer driver for cygnus b048432 cygnus: add QSPI driver 82a7bc4 veyron: add new SDRAM configuration with ram-code 1101b 823f607 pistachio: Remove 50% DDR bandwidth restriction 51ad6ac pistachio: Decrease DDR ODT from 75R to 50R 59074ff pistachio: clean DDR2 initialization code 1e935bf cygnus: enable serial driver for depthcharge 5a2718c storm: print uber-sbl information be7124e armv7: preserve bootblock invocation parameter 90fe582 ipq808x: add uber sbl parameter definitions d99e082 urara: I2C clock and MFIO setup function for all interfaces 38063b0 pistachio: add clock setup for all I2C interfaces 9ff8f6f Unify byte order macros and clrsetbits 9418476 arm(64): Manually clean up the mess left by write32() transition 2f37bd6 arm(64): Globally replace writel(v, a) with write32(a, v) 1f60f97 arm(64): Change write32() argument order to match x86 d21a329 arm(64): Replace write32() and friends with writel() 24f9476 romstage_handoff: Fix for changing CBMEM structure ebdef9f veyron_{brain,danger}: Specify vboot romstage and ramstage indices 3704e69 rk3288: disable rk808 DCDC_UV_ACT_REG restart converter function 19ee156 veyron: The ODT function is disabled for LPDDR3 c447f43 veyron: Sync up SDRAM configurations 5c8aacf rockchip: configure lpddr odt properly 9eb6f61 cbfs: Print absolute offsets of loaded files 5792e3b veyron_jerry: support K4B8G1646Q-4GB and H5TC8G63XXX-4GB ddr3 dbdd066 x86: Allow builds without ACPI tables 54cc8ba ipq806x: i2c: stop transfer as soon as an error is reported f36cffc ipq806x: i2c: write function fixed to avoid spurious success 44c5105 libpayload: mips: Do not set C0_EBase_WG ca0e89b libpayload: mips: Add macros to convert to/from KSEG{0,1} addresses ef4e87b arch/mips: simplify cache operations 8cc3a2a rk3288: support single channel ddr 9f5ad9b libpayload: mips: Use KSEG1 to access DMA-coherent memory 2e70946 libpayload: mips: Set BASE_ADDRESS to 0 b8936ad urara: Identity map DRAM/SRAM 3537e95 mips: Allow memory to be identity mapped in the TLB df4081e broadwell: Clear USB3.0 PORTSC status bits in sleep_prepare. 46d3ac1 broadwell: indent xhci code 1e6b591 broadwell: Skip pre-graphics delay in resume path b2deb22 broadwell: Implement Recovery Button f92edfe Arrange CBMEM table entries' IDs alphanumerically dfd441d urara: add config of SPI bus and correct selection of winbond flash 8549797 imgtec/pistachio: Add spi_crop_chunk() 4038a7f gigabyte/ga-b75m-d3v: Add GIGABYTE GA-B75M-D3V mainboard 31ca97c southbridge/intel/bd82x6x: Add LPC id 0x1e49 for B75 chipset bcff3bd mainboard/lenovo/t430s,t530,x230:enable usb3, set xhci overcurrent mapping 59aef5c southbrige/intel/bd82x6x: add XHCI overcurrent map config f21b657 build system: improve portability by not relying on extraordinary dd options 01368ed Kconfig: rename CONSOLE_SERIAL_UART to DRIVERS_UART c047b10 purin: add ns16550 driver 3a2ac88 console: copy ns16550 driver from u-boot 76e3303 chromeos: vboot2: Add TPM PCR extension support 5aecacc vboot2 workbuf alignment is now 16 bytes, not 8 cdf92ea rk3288: Disable ramstage compression by default 0b29a7b southbrige/intel/bd82x6x: XHCI replace magic values 7effaa4 riscv: use new-style CBFS header lookup 42001a7 vboot2: provide path for booting using alternative CBFS instances 3c90365 vboot2: Implement new vb2ex_hwcrypto API 23727ca vboot: make vboot2_verify_firmware return 7c25640 ipq806x: initialize UART even when console is not enabled b67b715 ipq806x: uart: replace hardware accessors ab7586f broadwell: Set C9/C10 vccmin aafdddf broadwell: Disable XHCI compliance mode entry 2f2a5e5 panther: Fix pointer related errors in LAN code 45e5997 cbfstool: clean up source code 1161473 cbfstool: add the missing 'break' 5e273a4 cbfstool: add a command to duplicate a cbfs instance 458a12e cbfstool: allow user to explicitly specify header location 14ecb54 soc/intel/common: Add common reset code a32b6b9 soc/intel/common: Add function to protect MRC cache 1006b10 broadwell: add ROM stage pre console init call back 3c6e5db libpayload udc: Support legal edge case of GET_CONFIGURATION call dc83d35 libpayload udc: Only enable configuration if it's valid e17d57e libpayload: Enforce strict packet handling order in ChipIdea driver 49a80ce libpayload: More defensive ChipIdea initialization 9a20a43 libpayload udc: Clear bit when it needs clearing bd6901e libpayload udc: Deconfigure device when necessary ea0bdf2 libpayload: Add zero length packet support to UDC framework 1bd3050 libpayload: Add USB device mode driver 2df124d lint: Add check for new board name scheme 139e106 kconfig: automatically include mainboards e5d5942 cygnus: enable mmu 128de62 cygnus: configure memlayout fcfd989 cygnus: add timer functions 352135e urara: Define UART used for serial console b116a1a pistachio: Move console UART to a Kconfig variable d82e0cf Fix non-x86 __PRE_RAM__ assertions and add FATAL_ASSERTS Kconfig option f0d038f flash: use two bytes of device ID to identify stmicro chips 7dcc48b storm: Add STM flash support 3b1c238 qualcomm/ipq806x: add spi_crop_chunk() e5fd1c9 spi: allow inclusion of Micronix and STM drivers in bootblock fc08b76 armv7: set CBFS header to zero d6aaca9 pistachio: add DDR2 initialization code b7be358 ryu: Add support for EVT board with ID BASE3(1,1) 4e158bc armv7: work around hang in bootblock startup code f61809a storm: handle dual purpose recovery button 20557c2 ryu: add support for p4 boards 8920865 ipq806x: extend GSBI driver to support i2c on any GSBI block 3cfb6a0 ipq806x: add LPASS clock control driver 7f70ad6 rk3288: Add software I2C support 1c2748d ipq806x: Add support for mmu in bootblock. efe279d veyron_{brain,danger,rialto}: Enable eventlogging 44004b3 veyron_{brain,danger,rialto}: Use common watchdog reboot e18c38e purin: add basic set of files for libpayload 0c253b6 rk3288: move reboot_from_watchdog() before rk808 setting 710e0a2 purin: add purin under mainboard a6712f3 broadcom/cygnus: add new SoC driver 105f5b7 chromeos: Provide common watchdog reboot support a5d2a8d veyron_*: Enable eventlogging 731bfef chromeos: Move memlayout.h/symbols.h into common directory f97b88b Makefile: Fix dependency tracking for ramstage objects 16d0188 storm: define location for storing CBFS header value 6bfabce cbfs: look for CBFS header in a predefined place 7271e23 pistachio: report UART register width 6cc5e52 libpayload: read register width from coreboot table 9dccf1c uart: pass register width in the coreboot table f7da3d2 libpayload: sync arch/arm/cache.c with coreboot d73a8e5 blaze: add new Hynix 2GB BCT e1298df exynos: return correct value when init_default_cbfs_media fails ee28c86 rk3288: detect sdram size at runtime d37bc75 veyron: move setup_chromeos_gpios() prototype to board.h 249f9cc rk3288: Handle framebuffer through memlayout, not the resource system deaaab2 arch/mips: Fix bug when performing cache operations fb03239 spi: Add function to read flash status register 1968b58 ARM: Remove -mno-unaligned-access 6addd40 libpayload: Take flash parameters from coreboot a5aac76 drivers/spi: Pass flash parameters from coreboot to payload f9b49e8 Add delay before reading GPIOs in gpio_base2_value() 92da778 urara: add board id information for urara board 90d0acb as3277: Fix month-off-by-one error for RTC driver 55cb84b bg4cd: define custom romstage entry 53b74f6 arm: allow custom stage entry code 1c78009 rk3288: Add a config variable hack to skip display init b7641cc veyron: Activate Winbond SPI driver See attached boot log for details This message was automatically generated from Raptor Engineering's QEMU x86_64 Q35 test stand Raptor Engineering offers coreboot consulting services! Please visit https://www.raptorengineeringinc.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineeringinc.com> regarding any issues stemming from this notification

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Re: [coreboot] cbmem console broken on Intel hardware since ec5e5e0
by Matt DeVillier 21 Apr '15

21 Apr '15

On 4/20/2015 3:29 PM, Aaron Durbin wrote: > On Mon, Apr 20, 2015 at 9:23 AM, Matt DeVillier > <matt.devillier(a)gmail.com> wrote: >> On 4/20/2015 8:51 AM, Aaron Durbin wrote: >>> On Fri, Apr 17, 2015 at 12:32 AM, Matt DeVillier >>> <matt.devillier(a)gmail.com> wrote: >>>> Greetings! When building upstream master tonight, discovered that cbmem console output is broken for Intel hardware (testing on google/panther). With some help on IRC from kmalkki, was able to determine the culprit is commit ec5e5e0 (New mechanism to define SRAM/memory map with automatic bounds checking). I verified this via bisecting; the prior commit, 06ef046, functions normally. >>> Did this get fixed? >> not as of yet (cdf92ea still has the issue) > Try this if you have time? I'm sure I haven't handled all the cases, > but it my work for you. > > http://review.coreboot.org/#/c/9851/ applying this as a cherry-pick gives me garbage/binary output for 'cbmem -c' >>> >>>> regards, >>>> Matt >>>> >>>> -- >>>> coreboot mailing list: coreboot(a)coreboot.org >>>> http://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Zako coreboot serial output does not insert 'return caret'
by Aaron Durbin 21 Apr '15

21 Apr '15

On Tue, Apr 21, 2015 at 12:35 AM, Anatol Pomozov <anatol.pomozov(a)gmail.com> wrote: > Hi > > I am playing with coreboot and try to build it with seabios payload for my > Zako device. Here is .config I use to compile coreboot at current HEAD > (4038a7f631dc) https://gist.github.com/a950a69e737ac06a24f3 I use board > "Panther" that I believe is the same as one in my Zako. > > I use google's servo to deploy FW to the board and I see a weird debug log > in my console. The log from coreboot looks like newline is inserted, but > return caret is not. SeaBIOS debug looks normal. Here and the log example > https://gist.github.com/anatol/8e30c8d5045ddf7e6b03 > > The host is Linux Arch. I tried several different console apps (cu, com) but > result is the same. > > Dear community, do you have ideas what can make the coreboot log unreadable? Feel free to cherry pick this: http://review.coreboot.org/9932 And/or log to a file and tail it. I use screen for my serial port attachment and just log to file. Hope that helps. > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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Lenovo T400 boot screen problem
by Andreas Kuss 21 Apr '15

21 Apr '15

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Dear coreboot developers, I successfully flashed a Lenovo T400 notebook with the latest release of libreboot. Unfortunately the boot screen does not exactly look like it should. I can only see the right half of the screen (on the left side of the display), the rest is black. Here is what it looks like: https://i.imgur.com/LqAdmmK.jpg The display is a FRU 42T0597 (B141PW03 V.0) PW AUO WXGA+ (1440x900). I checked the RAM (2x4GB Crucial both individually and 1x2GB) with no change. I also booted a Parabola live CD which seems to work but has no affect on the screen. Francis Rowe suspects a bug in coreboot and advised me to subscribe to the mailing list. Has anyone experienced something similar? Any help would be much appreciated! Thanks for reading! Kind regards Andreas -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQEcBAEBCAAGBQJVNlgyAAoJEDvFbiItFuuStSIIAI9HcYpV9Fte/VAPI0rVI5k4 LkzQqGYeQrb/8YEcFhC3xWZ1hAZZHo0sBJgqR07SlNsqBJVTj2UcByRBh+zfHhmi jVIHENuvVkwIQUNW9tUyRssnOdeWPUx9nzl/S3etSn3gZ2CuQpphorZvPKn8/Acj nv9okkVoFxuSYMjJlRIqyTUW7KDh3DfMRq/KzPyhMfGA5EgKJ8pOENHFW9UkC2B3 ECa6CEcX6Wu8MXKo9WrQgiM06Wz7zcy116XGfdUUeECpug+nmd8vQ6tf/RgEm8Po sLOBBoXUPbs+wQC3rYVXcceSNhCUidxIDrQ0+HM4+JKotq1dtFKhDQvVu1cxOvQ= =HXMW -----END PGP SIGNATURE-----

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Re: [coreboot] Zako coreboot serial output does not insert 'return caret'
by Patrick Georgi 21 Apr '15

21 Apr '15

2015-04-21 7:35 GMT+02:00 Anatol Pomozov <anatol.pomozov(a)gmail.com>: > I use google's servo to deploy FW to the board and I see a weird debug log > in my console. The log from coreboot looks like newline is inserted, but > return caret is not. SeaBIOS debug looks normal. Here and the log example > https://gist.github.com/anatol/8e30c8d5045ddf7e6b03 http://review.coreboot.org/#/c/8857/ changed the output format from ASCII to UNIX. Regards, Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Graham Law, Christine Elizabeth Flores

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Zako coreboot serial output does not insert 'return caret'
by Anatol Pomozov 21 Apr '15

21 Apr '15

Hi I am playing with coreboot and try to build it with seabios payload for my Zako device. Here is .config I use to compile coreboot at current HEAD (4038a7f631dc) https://gist.github.com/a950a69e737ac06a24f3 I use board "Panther" that I believe is the same as one in my Zako. I use google's servo to deploy FW to the board and I see a weird debug log in my console. The log from coreboot looks like newline is inserted, but return caret is not. SeaBIOS debug looks normal. Here and the log example https://gist.github.com/anatol/8e30c8d5045ddf7e6b03 The host is Linux Arch. I tried several different console apps (cu, com) but result is the same. Dear community, do you have ideas what can make the coreboot log unreadable?

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Re: [coreboot] Gerrit access rules
by Yang, York 21 Apr '15

21 Apr '15

That's great. Is "reviewers" also capable of merging a patch to master? Or requires some role else? Thanks, York -----Original Message----- From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Patrick Georgi via coreboot Sent: Thursday, April 16, 2015 9:46 AM To: coreboot(a)coreboot.org Subject: [coreboot] Gerrit access rules Hi, after deliberation to encourage positive feedback, gerrit rules are changed so that 'reviewers' can now give +2 Code-Reviews. Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Graham Law, Christine Elizabeth Flores -- coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

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QEMU x86_64 Q35 Automated Test Failure
by Raptor Engineering Automated Test Stand 21 Apr '15

21 Apr '15

The QEMU x86_64 Q35 fails verification as of commit 4038a7f631dce05aa184184a225a49bc7723aed0 Commits since last successful test: 4038a7f gigabyte/ga-b75m-d3v: Add GIGABYTE GA-B75M-D3V mainboard 31ca97c southbridge/intel/bd82x6x: Add LPC id 0x1e49 for B75 chipset bcff3bd mainboard/lenovo/t430s,t530,x230:enable usb3, set xhci overcurrent mapping 59aef5c southbrige/intel/bd82x6x: add XHCI overcurrent map config f21b657 build system: improve portability by not relying on extraordinary dd options 01368ed Kconfig: rename CONSOLE_SERIAL_UART to DRIVERS_UART c047b10 purin: add ns16550 driver 3a2ac88 console: copy ns16550 driver from u-boot 76e3303 chromeos: vboot2: Add TPM PCR extension support 5aecacc vboot2 workbuf alignment is now 16 bytes, not 8 cdf92ea rk3288: Disable ramstage compression by default 0b29a7b southbrige/intel/bd82x6x: XHCI replace magic values 7effaa4 riscv: use new-style CBFS header lookup 42001a7 vboot2: provide path for booting using alternative CBFS instances 3c90365 vboot2: Implement new vb2ex_hwcrypto API 23727ca vboot: make vboot2_verify_firmware return 7c25640 ipq806x: initialize UART even when console is not enabled b67b715 ipq806x: uart: replace hardware accessors ab7586f broadwell: Set C9/C10 vccmin aafdddf broadwell: Disable XHCI compliance mode entry 2f2a5e5 panther: Fix pointer related errors in LAN code 45e5997 cbfstool: clean up source code 1161473 cbfstool: add the missing 'break' 5e273a4 cbfstool: add a command to duplicate a cbfs instance 458a12e cbfstool: allow user to explicitly specify header location 14ecb54 soc/intel/common: Add common reset code a32b6b9 soc/intel/common: Add function to protect MRC cache 1006b10 broadwell: add ROM stage pre console init call back 3c6e5db libpayload udc: Support legal edge case of GET_CONFIGURATION call dc83d35 libpayload udc: Only enable configuration if it's valid e17d57e libpayload: Enforce strict packet handling order in ChipIdea driver 49a80ce libpayload: More defensive ChipIdea initialization 9a20a43 libpayload udc: Clear bit when it needs clearing bd6901e libpayload udc: Deconfigure device when necessary ea0bdf2 libpayload: Add zero length packet support to UDC framework 1bd3050 libpayload: Add USB device mode driver 2df124d lint: Add check for new board name scheme 139e106 kconfig: automatically include mainboards e5d5942 cygnus: enable mmu 128de62 cygnus: configure memlayout fcfd989 cygnus: add timer functions 352135e urara: Define UART used for serial console b116a1a pistachio: Move console UART to a Kconfig variable d82e0cf Fix non-x86 __PRE_RAM__ assertions and add FATAL_ASSERTS Kconfig option f0d038f flash: use two bytes of device ID to identify stmicro chips 7dcc48b storm: Add STM flash support 3b1c238 qualcomm/ipq806x: add spi_crop_chunk() e5fd1c9 spi: allow inclusion of Micronix and STM drivers in bootblock fc08b76 armv7: set CBFS header to zero d6aaca9 pistachio: add DDR2 initialization code b7be358 ryu: Add support for EVT board with ID BASE3(1,1) 4e158bc armv7: work around hang in bootblock startup code f61809a storm: handle dual purpose recovery button 20557c2 ryu: add support for p4 boards 8920865 ipq806x: extend GSBI driver to support i2c on any GSBI block 3cfb6a0 ipq806x: add LPASS clock control driver 7f70ad6 rk3288: Add software I2C support 1c2748d ipq806x: Add support for mmu in bootblock. efe279d veyron_{brain,danger,rialto}: Enable eventlogging 44004b3 veyron_{brain,danger,rialto}: Use common watchdog reboot e18c38e purin: add basic set of files for libpayload 0c253b6 rk3288: move reboot_from_watchdog() before rk808 setting 710e0a2 purin: add purin under mainboard a6712f3 broadcom/cygnus: add new SoC driver 105f5b7 chromeos: Provide common watchdog reboot support a5d2a8d veyron_*: Enable eventlogging 731bfef chromeos: Move memlayout.h/symbols.h into common directory f97b88b Makefile: Fix dependency tracking for ramstage objects 16d0188 storm: define location for storing CBFS header value 6bfabce cbfs: look for CBFS header in a predefined place 7271e23 pistachio: report UART register width 6cc5e52 libpayload: read register width from coreboot table 9dccf1c uart: pass register width in the coreboot table f7da3d2 libpayload: sync arch/arm/cache.c with coreboot d73a8e5 blaze: add new Hynix 2GB BCT e1298df exynos: return correct value when init_default_cbfs_media fails ee28c86 rk3288: detect sdram size at runtime d37bc75 veyron: move setup_chromeos_gpios() prototype to board.h 249f9cc rk3288: Handle framebuffer through memlayout, not the resource system deaaab2 arch/mips: Fix bug when performing cache operations fb03239 spi: Add function to read flash status register 1968b58 ARM: Remove -mno-unaligned-access 6addd40 libpayload: Take flash parameters from coreboot a5aac76 drivers/spi: Pass flash parameters from coreboot to payload f9b49e8 Add delay before reading GPIOs in gpio_base2_value() 92da778 urara: add board id information for urara board 90d0acb as3277: Fix month-off-by-one error for RTC driver 55cb84b bg4cd: define custom romstage entry 53b74f6 arm: allow custom stage entry code 1c78009 rk3288: Add a config variable hack to skip display init b7641cc veyron: Activate Winbond SPI driver See attached boot log for details This message was automatically generated from Raptor Engineering's QEMU x86_64 Q35 test stand Raptor Engineering offers coreboot consulting services! Please visit https://www.raptorengineeringinc.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineeringinc.com> regarding any issues stemming from this notification

1 0

QEMU x86_64 Q35 Automated Test Failure
by Raptor Engineering Automated Test Stand 20 Apr '15

20 Apr '15

The QEMU x86_64 Q35 fails verification as of commit f21b657f27965beacd2a3134aafbf66d4db60930 Commits since last successful test: f21b657 build system: improve portability by not relying on extraordinary dd options 01368ed Kconfig: rename CONSOLE_SERIAL_UART to DRIVERS_UART c047b10 purin: add ns16550 driver 3a2ac88 console: copy ns16550 driver from u-boot 76e3303 chromeos: vboot2: Add TPM PCR extension support 5aecacc vboot2 workbuf alignment is now 16 bytes, not 8 cdf92ea rk3288: Disable ramstage compression by default 0b29a7b southbrige/intel/bd82x6x: XHCI replace magic values 7effaa4 riscv: use new-style CBFS header lookup 42001a7 vboot2: provide path for booting using alternative CBFS instances 3c90365 vboot2: Implement new vb2ex_hwcrypto API 23727ca vboot: make vboot2_verify_firmware return 7c25640 ipq806x: initialize UART even when console is not enabled b67b715 ipq806x: uart: replace hardware accessors ab7586f broadwell: Set C9/C10 vccmin aafdddf broadwell: Disable XHCI compliance mode entry 2f2a5e5 panther: Fix pointer related errors in LAN code 45e5997 cbfstool: clean up source code 1161473 cbfstool: add the missing 'break' 5e273a4 cbfstool: add a command to duplicate a cbfs instance 458a12e cbfstool: allow user to explicitly specify header location 14ecb54 soc/intel/common: Add common reset code a32b6b9 soc/intel/common: Add function to protect MRC cache 1006b10 broadwell: add ROM stage pre console init call back 3c6e5db libpayload udc: Support legal edge case of GET_CONFIGURATION call dc83d35 libpayload udc: Only enable configuration if it's valid e17d57e libpayload: Enforce strict packet handling order in ChipIdea driver 49a80ce libpayload: More defensive ChipIdea initialization 9a20a43 libpayload udc: Clear bit when it needs clearing bd6901e libpayload udc: Deconfigure device when necessary ea0bdf2 libpayload: Add zero length packet support to UDC framework 1bd3050 libpayload: Add USB device mode driver 2df124d lint: Add check for new board name scheme 139e106 kconfig: automatically include mainboards e5d5942 cygnus: enable mmu 128de62 cygnus: configure memlayout fcfd989 cygnus: add timer functions 352135e urara: Define UART used for serial console b116a1a pistachio: Move console UART to a Kconfig variable d82e0cf Fix non-x86 __PRE_RAM__ assertions and add FATAL_ASSERTS Kconfig option f0d038f flash: use two bytes of device ID to identify stmicro chips 7dcc48b storm: Add STM flash support 3b1c238 qualcomm/ipq806x: add spi_crop_chunk() e5fd1c9 spi: allow inclusion of Micronix and STM drivers in bootblock fc08b76 armv7: set CBFS header to zero d6aaca9 pistachio: add DDR2 initialization code b7be358 ryu: Add support for EVT board with ID BASE3(1,1) 4e158bc armv7: work around hang in bootblock startup code f61809a storm: handle dual purpose recovery button 20557c2 ryu: add support for p4 boards 8920865 ipq806x: extend GSBI driver to support i2c on any GSBI block 3cfb6a0 ipq806x: add LPASS clock control driver 7f70ad6 rk3288: Add software I2C support 1c2748d ipq806x: Add support for mmu in bootblock. efe279d veyron_{brain,danger,rialto}: Enable eventlogging 44004b3 veyron_{brain,danger,rialto}: Use common watchdog reboot e18c38e purin: add basic set of files for libpayload 0c253b6 rk3288: move reboot_from_watchdog() before rk808 setting 710e0a2 purin: add purin under mainboard a6712f3 broadcom/cygnus: add new SoC driver 105f5b7 chromeos: Provide common watchdog reboot support a5d2a8d veyron_*: Enable eventlogging 731bfef chromeos: Move memlayout.h/symbols.h into common directory f97b88b Makefile: Fix dependency tracking for ramstage objects 16d0188 storm: define location for storing CBFS header value 6bfabce cbfs: look for CBFS header in a predefined place 7271e23 pistachio: report UART register width 6cc5e52 libpayload: read register width from coreboot table 9dccf1c uart: pass register width in the coreboot table f7da3d2 libpayload: sync arch/arm/cache.c with coreboot d73a8e5 blaze: add new Hynix 2GB BCT e1298df exynos: return correct value when init_default_cbfs_media fails ee28c86 rk3288: detect sdram size at runtime d37bc75 veyron: move setup_chromeos_gpios() prototype to board.h 249f9cc rk3288: Handle framebuffer through memlayout, not the resource system deaaab2 arch/mips: Fix bug when performing cache operations fb03239 spi: Add function to read flash status register 1968b58 ARM: Remove -mno-unaligned-access 6addd40 libpayload: Take flash parameters from coreboot a5aac76 drivers/spi: Pass flash parameters from coreboot to payload f9b49e8 Add delay before reading GPIOs in gpio_base2_value() 92da778 urara: add board id information for urara board 90d0acb as3277: Fix month-off-by-one error for RTC driver 55cb84b bg4cd: define custom romstage entry 53b74f6 arm: allow custom stage entry code 1c78009 rk3288: Add a config variable hack to skip display init b7641cc veyron: Activate Winbond SPI driver See attached boot log for details This message was automatically generated from Raptor Engineering's QEMU x86_64 Q35 test stand Raptor Engineering offers coreboot consulting services! Please visit https://www.raptorengineeringinc.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineeringinc.com> regarding any issues stemming from this notification

1 0

Re: [coreboot] cbmem console broken on Intel hardware since ec5e5e0
by Matt DeVillier 20 Apr '15

20 Apr '15

On 4/20/2015 8:51 AM, Aaron Durbin wrote: > On Fri, Apr 17, 2015 at 12:32 AM, Matt DeVillier > <matt.devillier(a)gmail.com> wrote: >> Greetings! When building upstream master tonight, discovered that cbmem console output is broken for Intel hardware (testing on google/panther). With some help on IRC from kmalkki, was able to determine the culprit is commit ec5e5e0 (New mechanism to define SRAM/memory map with automatic bounds checking). I verified this via bisecting; the prior commit, 06ef046, functions normally. > Did this get fixed? not as of yet (cdf92ea still has the issue) > >> regards, >> Matt >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot

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coreboot April 2015