coreboot April 2015

coreboot@coreboot.org

54 participants
92 discussions

by Raptor Engineering Automated Test Stand

The QEMU x86_64 Q35 fails verification as of commit f21b657f27965beacd2a3134aafbf66d4db60930 Commits since last successful test: f21b657 build system: improve portability by not relying on extraordinary dd options 01368ed Kconfig: rename CONSOLE_SERIAL_UART to DRIVERS_UART c047b10 purin: add ns16550 driver 3a2ac88 console: copy ns16550 driver from u-boot 76e3303 chromeos: vboot2: Add TPM PCR extension support 5aecacc vboot2 workbuf alignment is now 16 bytes, not 8 cdf92ea rk3288: Disable ramstage compression by default 0b29a7b southbrige/intel/bd82x6x: XHCI replace magic values 7effaa4 riscv: use new-style CBFS header lookup 42001a7 vboot2: provide path for booting using alternative CBFS instances 3c90365 vboot2: Implement new vb2ex_hwcrypto API 23727ca vboot: make vboot2_verify_firmware return 7c25640 ipq806x: initialize UART even when console is not enabled b67b715 ipq806x: uart: replace hardware accessors ab7586f broadwell: Set C9/C10 vccmin aafdddf broadwell: Disable XHCI compliance mode entry 2f2a5e5 panther: Fix pointer related errors in LAN code 45e5997 cbfstool: clean up source code 1161473 cbfstool: add the missing 'break' 5e273a4 cbfstool: add a command to duplicate a cbfs instance 458a12e cbfstool: allow user to explicitly specify header location 14ecb54 soc/intel/common: Add common reset code a32b6b9 soc/intel/common: Add function to protect MRC cache 1006b10 broadwell: add ROM stage pre console init call back 3c6e5db libpayload udc: Support legal edge case of GET_CONFIGURATION call dc83d35 libpayload udc: Only enable configuration if it's valid e17d57e libpayload: Enforce strict packet handling order in ChipIdea driver 49a80ce libpayload: More defensive ChipIdea initialization 9a20a43 libpayload udc: Clear bit when it needs clearing bd6901e libpayload udc: Deconfigure device when necessary ea0bdf2 libpayload: Add zero length packet support to UDC framework 1bd3050 libpayload: Add USB device mode driver 2df124d lint: Add check for new board name scheme 139e106 kconfig: automatically include mainboards e5d5942 cygnus: enable mmu 128de62 cygnus: configure memlayout fcfd989 cygnus: add timer functions 352135e urara: Define UART used for serial console b116a1a pistachio: Move console UART to a Kconfig variable d82e0cf Fix non-x86 __PRE_RAM__ assertions and add FATAL_ASSERTS Kconfig option f0d038f flash: use two bytes of device ID to identify stmicro chips 7dcc48b storm: Add STM flash support 3b1c238 qualcomm/ipq806x: add spi_crop_chunk() e5fd1c9 spi: allow inclusion of Micronix and STM drivers in bootblock fc08b76 armv7: set CBFS header to zero d6aaca9 pistachio: add DDR2 initialization code b7be358 ryu: Add support for EVT board with ID BASE3(1,1) 4e158bc armv7: work around hang in bootblock startup code f61809a storm: handle dual purpose recovery button 20557c2 ryu: add support for p4 boards 8920865 ipq806x: extend GSBI driver to support i2c on any GSBI block 3cfb6a0 ipq806x: add LPASS clock control driver 7f70ad6 rk3288: Add software I2C support 1c2748d ipq806x: Add support for mmu in bootblock. efe279d veyron_{brain,danger,rialto}: Enable eventlogging 44004b3 veyron_{brain,danger,rialto}: Use common watchdog reboot e18c38e purin: add basic set of files for libpayload 0c253b6 rk3288: move reboot_from_watchdog() before rk808 setting 710e0a2 purin: add purin under mainboard a6712f3 broadcom/cygnus: add new SoC driver 105f5b7 chromeos: Provide common watchdog reboot support a5d2a8d veyron_*: Enable eventlogging 731bfef chromeos: Move memlayout.h/symbols.h into common directory f97b88b Makefile: Fix dependency tracking for ramstage objects 16d0188 storm: define location for storing CBFS header value 6bfabce cbfs: look for CBFS header in a predefined place 7271e23 pistachio: report UART register width 6cc5e52 libpayload: read register width from coreboot table 9dccf1c uart: pass register width in the coreboot table f7da3d2 libpayload: sync arch/arm/cache.c with coreboot d73a8e5 blaze: add new Hynix 2GB BCT e1298df exynos: return correct value when init_default_cbfs_media fails ee28c86 rk3288: detect sdram size at runtime d37bc75 veyron: move setup_chromeos_gpios() prototype to board.h 249f9cc rk3288: Handle framebuffer through memlayout, not the resource system deaaab2 arch/mips: Fix bug when performing cache operations fb03239 spi: Add function to read flash status register 1968b58 ARM: Remove -mno-unaligned-access 6addd40 libpayload: Take flash parameters from coreboot a5aac76 drivers/spi: Pass flash parameters from coreboot to payload f9b49e8 Add delay before reading GPIOs in gpio_base2_value() 92da778 urara: add board id information for urara board 90d0acb as3277: Fix month-off-by-one error for RTC driver 55cb84b bg4cd: define custom romstage entry 53b74f6 arm: allow custom stage entry code 1c78009 rk3288: Add a config variable hack to skip display init b7641cc veyron: Activate Winbond SPI driver See attached boot log for details This message was automatically generated from Raptor Engineering's QEMU x86_64 Q35 test stand Raptor Engineering offers coreboot consulting services! Please visit https://www.raptorengineeringinc.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineeringinc.com> regarding any issues stemming from this notification

5 years, 10 months

Re: [coreboot] fsp_baytrail default SMM_TSEG_SIZE value

by David Imhoff

On 2015-04-16 16:31, Aaron Durbin wrote: > On Wed, Apr 15, 2015 at 5:06 AM, David Imhoff <dimhoff_devel(a)xs4all.nl> > wrote: >> When I change the SMM_TSEG_SIZE value to 0x800000 my Minnowboard Max >> is >> able to boot. >> >> So I wonder what the reason is for setting SMM_TSEG_SIZE to 0x100000 >> for fsp_baytrail SOC's instead of 0x800000 or 0? Also why is there a >> difference between the smm_region_size() default and the Kconfig >> default? >> > > See my comments on http://review.coreboot.org/#/c/7026/6 > > This patch should make it work for you as you noted. > > diff --git a/src/soc/intel/fsp_baytrail/Kconfig > b/src/soc/intel/fsp_baytrail/Kconfig > index d97879f..4881d8d 100644 > --- a/src/soc/intel/fsp_baytrail/Kconfig > +++ b/src/soc/intel/fsp_baytrail/Kconfig > @@ -72,7 +72,7 @@ config CPU_ADDR_BITS > > config SMM_TSEG_SIZE > hex > - default 0x100000 > + default 0x800000 > help > This is set by the FSP > I tested you're patch and can confirm it works. Can I do anything to get this patch accepted into GIT? I also quickly looked into you're review comment about BAYTRAIL_SMM. It is only used in src/soc/intel/fsp_baytrail/acpi.c. The only thing I can say about this is that if I force this ifdef to true and add 'cpu/x86/smm.h' to the includes, I can still build a booting firmware and boot Linux. But since I don't know what this code does, I can't say if this is the correct solution. Kind regards, David

5 years, 10 months

cbmem console broken on Intel hardware since ec5e5e0

by Matt DeVillier

Greetings! When building upstream master tonight, discovered that cbmem console output is broken for Intel hardware (testing on google/panther). With some help on IRC from kmalkki, was able to determine the culprit is commit ec5e5e0 (New mechanism to define SRAM/memory map with automatic bounds checking). I verified this via bisecting; the prior commit, 06ef046, functions normally. regards, Matt

5 years, 10 months

New Defects reported by Coverity Scan for coreboot

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 18 new defect(s) introduced to coreboot found with Coverity Scan. 3 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 18 of 18 defect(s) ** CID 1294808: Integer handling issues (DIVIDE_BY_ZERO) /src/soc/nvidia/tegra132/clock.c: 377 in clock_configure_plld() ________________________________________________________________________________________________________ *** CID 1294808: Integer handling issues (DIVIDE_BY_ZERO) /src/soc/nvidia/tegra132/clock.c: 377 in clock_configure_plld() 371 plld.cpcon = 12; 372 373 if (best_diff) { 374 printk(BIOS_WARNING, "%s: Failed to match output frequency %u, " 375 "best difference is %u.\n", __func__, frequency, 376 best_diff); >>> CID 1294808: Integer handling issues (DIVIDE_BY_ZERO) >>> In expression "ref / plld.m", division by expression "plld.m" which may be zero has undefined behavior. 377 rounded_rate = (ref / plld.m * plld.n) >> plld.p; 378 } 379 380 printk(BIOS_DEBUG, "%s: PLLD=%u ref=%u, m/n/p/cpcon=%u/%u/%u/%u\n", 381 __func__, rounded_rate, ref, plld.m, plld.n, plld.p, plld.cpcon); 382 ** CID 1294807: Integer handling issues (DIVIDE_BY_ZERO) /payloads/libpayload/libc/time.c: 62 in update_clock() ________________________________________________________________________________________________________ *** CID 1294807: Integer handling issues (DIVIDE_BY_ZERO) /payloads/libpayload/libc/time.c: 62 in update_clock() 56 ticks_per_sec = timer_hz(); 57 ticks_per_usec = timer_hz() / 1000000; 58 } 59 60 clock.ticks += delta; 61 >>> CID 1294807: Integer handling issues (DIVIDE_BY_ZERO) >>> In expression "delta / ticks_per_sec", division by expression "ticks_per_sec" which may be zero has undefined behavior. 62 secs = (int) (delta / ticks_per_sec); 63 clock.secs += secs; 64 delta -= (secs * ticks_per_sec); 65 clock.usecs += (int)(delta / ticks_per_usec); 66 67 if (clock.usecs > 1000000) { ** CID 1294806: Null pointer dereferences (FORWARD_NULL) /src/arch/riscv/rom_media.c: 69 in init_rom_media_cbfs() ________________________________________________________________________________________________________ *** CID 1294806: Null pointer dereferences (FORWARD_NULL) /src/arch/riscv/rom_media.c: 69 in init_rom_media_cbfs() 63 //extern unsigned long _cbfs_master_header; 64 // On X86, we always keep a reference of pointer to CBFS header in 65 // 0xfffffffc, and the pointer is still a memory-mapped address. 66 // Since the CBFS core always use ROM offset, we need to figure out 67 // header->romsize even before media is initialized. 68 struct cbfs_header *header = (struct cbfs_header*) CONFIG_CBFS_HEADER_ROM_OFFSET; //&_cbfs_master_header; >>> CID 1294806: Null pointer dereferences (FORWARD_NULL) >>> Dereferencing null pointer "header". 69 if (CBFS_HEADER_MAGIC != ntohl(header->magic)) { 70 printk(BIOS_ERR, "Invalid CBFS master header at %p\n", header); 71 printk(BIOS_ERR, "Expected %08lx and got %08lx\n", (unsigned long) CBFS_HEADER_MAGIC, (unsigned long) ntohl(header->magic)); 72 return -1; 73 } else { 74 uint32_t romsize = ntohl(header->romsize); ** CID 1294805: Null pointer dereferences (FORWARD_NULL) /src/soc/nvidia/tegra132/dsi.c: 726 in tegra_dsi_host_transfer() ________________________________________________________________________________________________________ *** CID 1294805: Null pointer dereferences (FORWARD_NULL) /src/soc/nvidia/tegra132/dsi.c: 726 in tegra_dsi_host_transfer() 720 /* write payload (if any) */ 721 if (msg->tx_len > 2) { 722 for (j = 2; j < msg->tx_len; j += 4) { 723 value = 0; 724 725 for (i = 0; i < 4 && j + i < msg->tx_len; i++) >>> CID 1294805: Null pointer dereferences (FORWARD_NULL) >>> Dereferencing null pointer "tx". 726 value |= tx[j + i] << (i << 3); 727 728 tegra_dsi_writel(dsi, value, DSI_WR_DATA); 729 } 730 } 731 ** CID 1294804: Memory - illegal accesses (OVERRUN) /coreboot-builds/amd_olivehillplus/agesa/amdlib.c: 1411 in IdsErrorStop() ________________________________________________________________________________________________________ *** CID 1294804: Memory - illegal accesses (OVERRUN) /coreboot-builds/amd_olivehillplus/agesa/amdlib.c: 1411 in IdsErrorStop() 1405 } post = {0xDEAD, FileCode, 0xDEAD, FileCode}; 1406 UINT16 offset = 0; 1407 UINT16 j; 1408 1409 while(1) { 1410 offset %= sizeof(struct POST) / 2; >>> CID 1294804: Memory - illegal accesses (OVERRUN) >>> Overrunning array of 3 4-byte elements at element index 15 (byte offset 60) by dereferencing pointer "(UINT32 *)(&post + offset)". 1411 WriteIo32(80, *((UINT32*)(&post+offset))); 1412 ++offset; 1413 for (j=0; j<250; ++j) { 1414 ReadIo8(80); 1415 } 1416 } ** CID 1294803: (OVERRUN) /src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpmaxfreq.c: 289 in MemPGetMaxFreqSupported() /src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpmaxfreq.c: 277 in MemPGetMaxFreqSupported() ________________________________________________________________________________________________________ *** CID 1294803: (OVERRUN) /src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpmaxfreq.c: 289 in MemPGetMaxFreqSupported() 283 NBPtr->MaxFreqVDDIO[CurrentVoltage] = 0; 284 } 285 } 286 IDS_HDT_CONSOLE (MEM_FLOW, "\n"); 287 } 288 ASSERT (DDR3Voltage <= VOLT1_25_ENCODED_VAL); >>> CID 1294803: (OVERRUN) >>> Overrunning array of 3 2-byte elements at element index 255 (byte offset 510) by dereferencing pointer "SpeedArray + DDR3Voltage". 289 MaxFreqSupported = SpeedArray[DDR3Voltage]; 290 } 291 292 if (MaxFreqSupported == UNSUPPORTED_DDR_FREQUENCY) { 293 // No entry in the table for current dimm population is found 294 IDS_HDT_CONSOLE (MEM_FLOW, "\nDCT %d: No entry is found in the Max Frequency table\n", NBPtr->Dct); /src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpmaxfreq.c: 277 in MemPGetMaxFreqSupported() 271 NBPtr->MaxFreqVDDIO[CurrentVoltage] = 0; 272 } 273 } 274 IDS_HDT_CONSOLE (MEM_FLOW, "\n"); 275 } 276 ASSERT (DDR3Voltage <= VOLT1_25_ENCODED_VAL); >>> CID 1294803: (OVERRUN) >>> Overrunning array of 3 2-byte elements at element index 255 (byte offset 510) by dereferencing pointer "SpeedArray + DDR3Voltage". 277 MaxFreqSupported = SpeedArray[DDR3Voltage]; 278 } 279 280 if (MaxFreqSupported == UNSUPPORTED_DDR_FREQUENCY) { 281 // No entry in the table for current dimm population is found 282 IDS_HDT_CONSOLE (MEM_FLOW, "\nDCT %d: No entry is found in the Max Frequency table\n", NBPtr->Dct); ** CID 1294802: API usage errors (PW.PRINTF_ARG_MISMATCH) /util/bimgtool/bimgtool.c: 275 in () ________________________________________________________________________________________________________ *** CID 1294802: API usage errors (PW.PRINTF_ARG_MISMATCH) /util/bimgtool/bimgtool.c: 275 in () 269 return -1; 270 } 271 272 if ((file_header.data_size + sizeof(struct bimg_header)) > 273 buf.st_size) { 274 fprintf(stderr, "Data size too big: %d > %d\n", >>> CID 1294802: API usage errors (PW.PRINTF_ARG_MISMATCH) >>> argument is incompatible with corresponding format string conversion 275 file_header.data_size, buf.st_size); 276 return -1; 277 } 278 279 if (file_header.ver_major != crc_type.ver_major) { 280 fprintf(stderr, "Image version mismatch: %d\n", ** CID 1294801: (RESOURCE_LEAK) /src/soc/qualcomm/ipq806x/lcc.c: 313 in audio_clock_config() /src/soc/qualcomm/ipq806x/lcc.c: 315 in audio_clock_config() /src/soc/qualcomm/ipq806x/lcc.c: 310 in audio_clock_config() /src/soc/qualcomm/ipq806x/lcc.c: 308 in audio_clock_config() /src/soc/qualcomm/ipq806x/lcc.c: 306 in audio_clock_config() ________________________________________________________________________________________________________ *** CID 1294801: (RESOURCE_LEAK) /src/soc/qualcomm/ipq806x/lcc.c: 313 in audio_clock_config() 307 if (lcc_init_enable_ahbix(bus)) 308 return 1; 309 if (lcc_init_mi2s(bus, frequency)) 310 return 1; 311 312 if (lcc_enable_mi2s(bus)) >>> CID 1294801: (RESOURCE_LEAK) >>> Variable "bus" going out of scope leaks the storage it points to. 313 return 1; 314 315 return 0; /src/soc/qualcomm/ipq806x/lcc.c: 315 in audio_clock_config() 309 if (lcc_init_mi2s(bus, frequency)) 310 return 1; 311 312 if (lcc_enable_mi2s(bus)) 313 return 1; 314 >>> CID 1294801: (RESOURCE_LEAK) >>> Variable "bus" going out of scope leaks the storage it points to. 315 return 0; /src/soc/qualcomm/ipq806x/lcc.c: 310 in audio_clock_config() 304 305 if (lcc_init_enable_pll0(bus)) 306 return 1; 307 if (lcc_init_enable_ahbix(bus)) 308 return 1; 309 if (lcc_init_mi2s(bus, frequency)) >>> CID 1294801: (RESOURCE_LEAK) >>> Variable "bus" going out of scope leaks the storage it points to. 310 return 1; 311 312 if (lcc_enable_mi2s(bus)) 313 return 1; 314 315 return 0; /src/soc/qualcomm/ipq806x/lcc.c: 308 in audio_clock_config() 302 bus->lcc_pll_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_PLL_PCLK_REG); 303 304 305 if (lcc_init_enable_pll0(bus)) 306 return 1; 307 if (lcc_init_enable_ahbix(bus)) >>> CID 1294801: (RESOURCE_LEAK) >>> Variable "bus" going out of scope leaks the storage it points to. 308 return 1; 309 if (lcc_init_mi2s(bus, frequency)) 310 return 1; 311 312 if (lcc_enable_mi2s(bus)) 313 return 1; 314 315 return 0; /src/soc/qualcomm/ipq806x/lcc.c: 306 in audio_clock_config() 300 bus->lcc_ahbix_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_AHBIX_NS_REG); 301 bus->lcc_mi2s_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_MI2S_NS_REG); 302 bus->lcc_pll_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_PLL_PCLK_REG); 303 304 305 if (lcc_init_enable_pll0(bus)) >>> CID 1294801: (RESOURCE_LEAK) >>> Variable "bus" going out of scope leaks the storage it points to. 306 return 1; 307 if (lcc_init_enable_ahbix(bus)) 308 return 1; 309 if (lcc_init_mi2s(bus, frequency)) 310 return 1; 311 ** CID 1294800: (SIGN_EXTENSION) /src/soc/nvidia/tegra132/dsi.c: 340 in tegra_dsi_configure() /src/soc/nvidia/tegra132/dsi.c: 341 in tegra_dsi_configure() ________________________________________________________________________________________________________ *** CID 1294800: (SIGN_EXTENSION) /src/soc/nvidia/tegra132/dsi.c: 340 in tegra_dsi_configure() 334 } else { 335 /* 1 byte (DCS command) + pixel data */ 336 bytes = 1 + mode->xres * mul / div; 337 } 338 339 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1); >>> CID 1294800: (SIGN_EXTENSION) >>> Suspicious implicit sign extension: "bytes" with type "unsigned short" (16 bits, unsigned) is promoted in "bytes << 16" to type "int" (32 bits, signed), then sign-extended to type "unsigned long" (64 bits, unsigned). If "bytes << 16" is greater than 0x7FFFFFFF, the upper bits of the result will all be 1. 340 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3); 341 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5); 342 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7); 343 344 value = MIPI_DCS_WRITE_MEMORY_START << 8 | 345 MIPI_DCS_WRITE_MEMORY_CONTINUE; /src/soc/nvidia/tegra132/dsi.c: 341 in tegra_dsi_configure() 335 /* 1 byte (DCS command) + pixel data */ 336 bytes = 1 + mode->xres * mul / div; 337 } 338 339 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1); 340 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3); >>> CID 1294800: (SIGN_EXTENSION) >>> Suspicious implicit sign extension: "bytes" with type "unsigned short" (16 bits, unsigned) is promoted in "bytes << 16" to type "int" (32 bits, signed), then sign-extended to type "unsigned long" (64 bits, unsigned). If "bytes << 16" is greater than 0x7FFFFFFF, the upper bits of the result will all be 1. 341 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5); 342 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7); 343 344 value = MIPI_DCS_WRITE_MEMORY_START << 8 | 345 MIPI_DCS_WRITE_MEMORY_CONTINUE; 346 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS); ** CID 1294799: Control flow issues (UNREACHABLE) /src/soc/rockchip/rk3288/edp.c: 746 in rk_edp_read_bytes_from_i2c() ________________________________________________________________________________________________________ *** CID 1294799: Control flow issues (UNREACHABLE) /src/soc/rockchip/rk3288/edp.c: 746 in rk_edp_read_bytes_from_i2c() 740 edp_debug("Aux Transaction fail!\n"); 741 continue; 742 } 743 744 /* Check if Rx sends defer */ 745 val = readl(&edp->regs->aux_rx_comm); >>> CID 1294799: Control flow issues (UNREACHABLE) >>> This code cannot be reached: "if (val == 2U || val == 8U)...". 746 if (val == AUX_RX_COMM_AUX_DEFER || 747 val == AUX_RX_COMM_I2C_DEFER) { 748 edp_debug("Defer: %d\n\n", val); 749 defer = 1; 750 } 751 } ** CID 1294798: Code maintainability issues (UNUSED_VALUE) /src/soc/rockchip/rk3288/edp.c: 721 in rk_edp_read_bytes_from_i2c() ________________________________________________________________________________________________________ *** CID 1294798: Code maintainability issues (UNUSED_VALUE) /src/soc/rockchip/rk3288/edp.c: 721 in rk_edp_read_bytes_from_i2c() 715 716 /* 717 * If Rx sends defer, Tx sends only reads 718 * request without sending addres 719 */ 720 if (!defer) >>> CID 1294798: Code maintainability issues (UNUSED_VALUE) >>> Assigning value from "rk_edp_select_i2c_device(edp, device_addr, val_addr + i)" to "retval" here, but that stored value is overwritten before it can be used. 721 retval = rk_edp_select_i2c_device(edp, 722 device_addr, val_addr + i); 723 else 724 defer = 0; 725 726 /* ** CID 1294797: Error handling issues (CHECKED_RETURN) /util/cbfstool/cbfstool.c: 350 in cbfs_create() ________________________________________________________________________________________________________ *** CID 1294797: Error handling issues (CHECKED_RETURN) /util/cbfstool/cbfstool.c: 350 in cbfs_create() 344 ERROR("You need to specify -m/--machine arch.\n"); 345 return 1; 346 } 347 348 if (!param.bootblock) { 349 DEBUG("-B not given, creating image without bootblock.\n"); >>> CID 1294797: Error handling issues (CHECKED_RETURN) >>> Calling "buffer_create" without checking return value (as is done elsewhere 9 out of 10 times). 350 buffer_create(&bootblock, 0, "(dummy)"); 351 } else if (buffer_from_file(&bootblock, param.bootblock)) { 352 return 1; 353 } 354 355 if (!param.alignment) ** CID 1294796: Integer handling issues (BAD_SHIFT) /src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpmaxfreq.c: 291 in MemPGetMaxFreqSupported() ________________________________________________________________________________________________________ *** CID 1294796: Integer handling issues (BAD_SHIFT) /src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpmaxfreq.c: 291 in MemPGetMaxFreqSupported() 285 } 286 } 287 IDS_HDT_CONSOLE (MEM_FLOW, "\n"); 288 } 289 ASSERT (DDR3Voltage <= VOLT1_25_ENCODED_VAL); 290 for (CurrentVoltage = DDR3Voltage; CurrentVoltage >= VOLT1_5_ENCODED_VAL; CurrentVoltage --) { >>> CID 1294796: Integer handling issues (BAD_SHIFT) >>> In expression "1 << CurrentVoltage", left shifting by more than 31 bits has undefined behavior. The shift amount, "CurrentVoltage", is 255. 291 if (NBPtr->SharedPtr->VoltageMap & (1 << CurrentVoltage)) { 292 MaxFreqSupported = SpeedArray[CurrentVoltage]; 293 if (MaxFreqSupported != UNSUPPORTED_DDR_FREQUENCY) { 294 NBPtr->RefPtr->DDR3Voltage = CONVERT_ENCODED_TO_VDDIO (CurrentVoltage); 295 IDS_HDT_CONSOLE (MEM_FLOW, "\nVDDIO leveraged to %s\n", (CurrentVoltage == VOLT1_5_ENCODED_VAL) ? "1.5V" : ((CurrentVoltage == VOLT1_35_ENCODED_VAL) ? "1.35V" : "1.25V")); 296 break; ** CID 1294795: Control flow issues (DEADCODE) /src/soc/rockchip/rk3288/edp.c: 724 in rk_edp_read_bytes_from_i2c() ________________________________________________________________________________________________________ *** CID 1294795: Control flow issues (DEADCODE) /src/soc/rockchip/rk3288/edp.c: 724 in rk_edp_read_bytes_from_i2c() 718 * request without sending addres 719 */ 720 if (!defer) 721 retval = rk_edp_select_i2c_device(edp, 722 device_addr, val_addr + i); 723 else >>> CID 1294795: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "defer = 0U;". 724 defer = 0; 725 726 /* 727 * Set I2C transaction and write data 728 * If bit 3 is 1, DisplayPort transaction. 729 * If Bit 3 is 0, I2C transaction. ** CID 1294794: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /src/soc/imgtec/pistachio/clocks.c: 359 in mips_clk_setup() ________________________________________________________________________________________________________ *** CID 1294794: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /src/soc/imgtec/pistachio/clocks.c: 359 in mips_clk_setup() 353 void mips_clk_setup(u8 divider1, u8 divider2) 354 { 355 u32 reg; 356 357 /* Check input parameters */ 358 assert(!(divider1 & ~(MIPSCLKINTERNAL_MASK))); >>> CID 1294794: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "divider2 & -256 /* ~0xff */" is always 0 regardless of the values of its operands. This occurs as the logical operand of '!'. 359 assert(!(divider2 & ~(MIPSCLKOUT_MASK))); 360 361 /* Set divider 1 */ 362 reg = read32(MIPSCLKINTERNAL_CTRL_ADDR); 363 reg &= ~MIPSCLKINTERNAL_MASK; 364 reg |= divider1 & MIPSCLKINTERNAL_MASK; ** CID 1294793: Control flow issues (DEADCODE) /src/soc/imgtec/pistachio/uart.c: 129 in uart_init() ________________________________________________________________________________________________________ *** CID 1294793: Control flow issues (DEADCODE) /src/soc/imgtec/pistachio/uart.c: 129 in uart_init() 123 } 124 125 void uart_init(int idx) 126 { 127 u32 base = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; 128 if (!base) >>> CID 1294793: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "return;". 129 return; 130 131 unsigned int div; 132 div = uart_baudrate_divisor(CONFIG_TTYS0_BAUD, 133 uart_platform_refclk(), 16); 134 uart8250_mem_init(base, div); ** CID 1260908: Null pointer dereferences (FORWARD_NULL) /src/ec/google/chromeec/ec.c: 421 in google_chromeec_set_usb_charge_mode() ________________________________________________________________________________________________________ *** CID 1260908: Null pointer dereferences (FORWARD_NULL) /src/ec/google/chromeec/ec.c: 421 in google_chromeec_set_usb_charge_mode() 415 416 cmd.cmd_code = EC_CMD_USB_CHARGE_SET_MODE; 417 cmd.cmd_version = 0; 418 cmd.cmd_size_in = sizeof(set_mode); 419 cmd.cmd_data_in = &set_mode; 420 cmd.cmd_size_out = 0; >>> CID 1260908: Null pointer dereferences (FORWARD_NULL) >>> Assigning: "cmd.cmd_data_out" = "NULL". 421 cmd.cmd_data_out = NULL; 422 cmd.cmd_dev_index = 0; 423 424 return google_chromeec_command(&cmd); 425 } 426 ** CID 1260807: Memory - illegal accesses (OVERRUN) /src/southbridge/amd/agesa/hudson/imc.c: 78 in enable_imc_thermal_zone() ________________________________________________________________________________________________________ *** CID 1260807: Memory - illegal accesses (OVERRUN) /src/southbridge/amd/agesa/hudson/imc.c: 78 in enable_imc_thermal_zone() 72 FunNum = Fun_80; 73 for (i=0; i<=1; i++) 74 WriteECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader); 75 WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); // function number 76 WaitForEcLDN9MailboxCmdAck(&StdHeader); 77 >>> CID 1260807: Memory - illegal accesses (OVERRUN) >>> Checking "i <= 9" implies that "i" may be up to 9 on the true branch. 78 for (i=2; i<=9; i++) 79 ReadECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader); 80 81 /* enable thermal zone 0 */ 82 regs[2] |= 1; 83 regs[0] = 0; ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/1016?tab=overview To manage Coverity Scan email notifications for "coreboot(a)coreboot.org", click https://scan.coverity.com/subscriptions/edit?email=coreboot%40coreboot.org&… .

5 years, 10 months

Regarding Intel (and Librem)

by Vladimir

Problem with Librem is not just that it isn't fully free yet and doesn't seem to become so in future, but also that it is an Intel-based product. Intel is totally NOT friendly to coreboot project (and open source community in general) - that could be seen by their malevolent actions, such as introduction of Boot Guard "feature". Intel tries to justify them by "it's for your safety" preaching; but, "anytime someone puts a lock on something you own, against your wishes, and doesn't give you the key, they're not doing it for your benefit" (Doctorow's Law) By purchasing a product of a company, you are fully supporting their policy. And that is why it is not good to support Intel by getting Intel-based products and developing for Intel, despite ~75% of x86/x86_64 CPU market is owned by them. You are right, there are some difficulties about AMD products, such as the need to reverse engineer SMU and Atombios firmwares for their APUs. But at least they're not putting deliberate hardware obstacles in their new products, and if they don't become "evil" like Intel (hope so) AMD could be a future of coreboot x86/x86_64 branch. P.S. In addition to Lenovo G505s, I was very happy to find out that - thanks to latest contributors - coreboot is now supporting the ASROCK IMB-A180 and Biostar AM1ML which are based on AMD AM1 platform (architecture family 16h, Puma/Jaguar SoCs are compatible) Maybe some of these products have a potential to be RYF'ed, will see... Best regards, Vladimir Shipovalov On 11 April 2015 at 19:33, Peter Stuge <peter(a)stuge.se> wrote: > Alexandru Gagniuc wrote: > > figured out how to fuse the PCH to disable ME > > Please read ISBN 9781430265719. > > The ME firmware controls the host CPU reset. > > //Peter > > On 10 April 2015 at 08:45, Alexandru Gagniuc <mr.nuke.me(a)gmail.com> wrote: > >> On Monday, April 06, 2015 01:45:32 PM Vladimir wrote: >> > Dear coreboot developers, >> > >> > Francis Rowe (main Libreboot developer) has hinted an idea about adding >> > Lenovo G505S to Coreboot LTS Candidates list of laptops, which is >> hosted at >> > MrNuke's User talk coreboot wiki page. I believe it is an excellent >> idea, >> > because: >> > >> You are free to add it, but keep in mind that anything with an AMD APU >> will >> fail the RYF-certifiable criteria due to SMU and atombios. >> >> If we're going to lower the bar, we should also consider Librem 15. At >> least >> that one has (should have) a much more durable construction and much >> better >> screen. If those guys aren't as full of it as they sound, and have >> figured out >> how to fuse the PCH to disable ME, then RYF'ing a Librem should be less >> work >> than anything APU. >> >> > Best regards, >> Alex >> >> On 8 April 2015 at 12:49, Vladimir <quickcracktime(a)gmail.com> wrote: >> >>> What if A8 model is supported as well, just not tested yet? These APUs >>> are very similar to each other, after all ;) >>> Maybe a knowledgeable coreboot developers, especially those who have >>> ported coreboot to G505S, could tell what parts of code are A10-specific - >>> and, if there is indeed such a code, how to change the parameters of that >>> code to make them suitable for A8 ? >>> >>> In case they don't reply: if you have SPI clip as well as BIOS >>> programmer that supports many chips including MX25L1606E , could try a >>> following scenario: >>> 1) get A8 G505S locally & try to install coreboot >>> 2) if it works, announce it to a mailing list that there's a support and >>> keep a laptop to yourself ; but if it doesn't work - even after playing >>> with parameters - and a laptop is bricked, you could restore a >>> manufacturer's BIOS using SPI clip & BIOS programmer, and then return a >>> laptop to seller... >>> >>> About A10 model - it does not seem to be US-only: there are a lot of >>> offers in Russia, as well as at "developing countries" such as >>> Thailand/India (maybe that stock was inherited from EU countries) But, >>> because of huge quantity of different laptop models/modifications, and >>> dependence of their local availability on local retailers' preference, >>> there are countries which got either a small stock of G505S or none at all! >>> :P And that returns us to "reasonable availability" debate... In my >>> perception: >>> >>> "Reasonable availability" for a laptop model, is when a person is able >>> to get a new laptop (not used/refurbished) - for a price that does not >>> exceed the manufacturer's list price by more than X % of it. (e.g. 25%). >>> That additional condition regarding the list price is necessary, because if >>> there would be some greedy retailers left - who didn't sold out their large >>> stock just because of outrageous unreasonable prices - I wouldn't call this >>> as "reasonably available" ;) >>> >>> As you see, "reasonable availability" is a quite subjective term, >>> because if your country doesn't have a stock of this laptop: >>> *) your price would be not just price of unit but also a shipping price >>> from other country, + possible import taxes >>> *) there are various risks: if, because of your location, you cannot buy >>> a laptop in store after checking its quality, >>> a laptop could have manufacturing defects that are not enough to request >>> a replacement/partial refund, e.g. laws based on ISO 13406-2 standard could >>> allow a seller to refuse a replacement of laptop if there are a few >>> annoying dead pixels. >>> These risks have a different "weight" in the eyes of different people, >>> e.g. many people wouldn't consider it as "reasonably available" even if >>> it's available from neighbor country with a low shipping price, because >>> they do not want to risk. And that makes this term even more subjective and >>> hard to measure by automatic metrics... >>> >>> P.S. Indeed, some laptops that are listed in coreboot "LTS Candidates" >>> list ( http://www.coreboot.org/User_talk:MrNuke/LTS_Candidates ) have >>> A10-5750M as well and seem to be more "reasonably available" than G505S, at >>> least for your country. But, despite having a somewhat similar hardware, >>> nobody ported a coreboot to them yet :P >>> >>> Best regards, >>> Vladimir Shipovalov >>> >>> >>> On 7 April 2015 at 16:17, Emilian Bold <emilian.bold(a)gmail.com> wrote: >>> >>>> My point is not to limit your LTS list to US laptops. US has >>>> *extraordinary* availability for a lot of gear. >>>> >>>> There's also the matter of procurement and warranty. A company won't >>>> bother importing some laptop from outside the EU just because a developer >>>> wants it -- they will look locally and as a last resort within the EU. >>>> >>>> Except some brands (Apple comes to mind) warranty becomes a hassle if >>>> the laptop breaks. Transport costs, long wait time and language issues >>>> complicate matters. >>>> >>>> Amazon Germany seems to have 2 laptops in stock with A10. Amazon >>>> Spain/France/Italy/Netherlands has none. Only Amazon UK seems to have it >>>> without giving a stock warning (but it's sold by a 3d party). >>>> >>>> Anyhow, I don't want to sidetrack this, but the first criteria for the >>>> LTS laptop is "reasonable availability"... >>>> >>>> Perhaps you should have some metric for availability (this could even >>>> be automated somewhat). Pick a list of top electronics sites/stores from a >>>> list of countries and define a formula based on model availability. >>>> >>>> Alternatively, it would be great to support the A8 too! >>>> >>>> To me the the G505S would clearly be a better machine to recommend >>>> compared to an ancient Thinkpad X2xx! >>>> >>>> --emi >>>> >>>> >>>> On Tue, Apr 7, 2015 at 3:28 PM, Vladimir <quickcracktime(a)gmail.com> >>>> wrote: >>>> >>>>> If I am not mistaken, your country is Romania... Unfortunately - if I >>>>> didn't skip something - it looks like Romania went out of A10 stock just a >>>>> couple of weeks ago! However, I found many offers from Hungary, which is >>>>> very close! Some offers are listed on "price list"-type websites (e.g. >>>>> http://www.arukereso.hu/CategorySearch.php?st=g505s+a10 ) while >>>>> others are not listed anywhere (e.g. >>>>> http://www.notebookspecialista.hu/lenovo_ideapad_g505s_59_422983_notebook-1… >>>>> ) >>>>> Nice thing is that these offers usually have A10 + R5 230M, slightly >>>>> faster dual graphics. But the majority of G505S models selling in Europe >>>>> have Win8 pre-installed, so I'm afraid it would be hard to avoid paying >>>>> extra for this bloatware, in your case :P >>>>> >>>>> As for other European countries, it is difficult for me to look >>>>> through the entire EU because there are many countries with many languages. >>>>> I only know English as foreign language, and thats why the majority of >>>>> foreign offers I'm able to find, are in UK/US... >>>>> >>>>> On 6 April 2015 at 23:12, Emilian Bold <emilian.bold(a)gmail.com> wrote: >>>>> >>>>>> Well, the G505S with A10-5750M is explicitly listed as no longer >>>>>> being sold. So it's the A8 or nothing. >>>>>> >>>>>> Could you provide links within the EU with (online) shops still >>>>>> selling the A10 variant and having some actual stock? >>>>>> >>>>>> --emi >>>>>> >>>>>> On Mon, Apr 6, 2015 at 6:45 PM, Vladimir <quickcracktime(a)gmail.com> >>>>>> wrote: >>>>>> >>>>>>> Yes, in addition to A10-5750M based G505S there are also A8 and A6 >>>>>>> ones. But there are some possible problems regarding them: >>>>>>> 1) their price is just slightly lower than with A10 - as result, >>>>>>> price/performance ratio seems to be worse for these models >>>>>>> 2) I'm not sure if it is possible could upgrade their APU from A6/A8 >>>>>>> to A10-5750M after purchase >>>>>>> 3) most importantly: some parameters inside a coreboot source code >>>>>>> for G505S could be A10-specific ; >>>>>>> I am not sure if a current "A10-inclined build" would run on A8/A6 >>>>>>> out of the box, without additional tweaking >>>>>>> >>>>>>> A question from my last letter - about compatibility of G505S >>>>>>> coreboot build with various graphics solutions found in different >>>>>>> modifications, is not addressed yet... to remind, there are three groups of >>>>>>> modifications: >>>>>>> *) only 8650G (no dual graphics) >>>>>>> *) 8650G + AMD HD 8570M (dual graphics) >>>>>>> *) 8650G + AMD R5 M230 (dual graphics, slightly faster) >>>>>>> >>>>>>> P.S. Below is an =incomplete= list of SKUs for A10 G505S models that >>>>>>> I was able to find. If there is a shortage in your country, maybe this list >>>>>>> could assist you in search (those mods with windows 8 are about $50 more >>>>>>> expensive and support evil M$, please dont get them ;-) ) >>>>>>> >>>>>>> 1) only 8650G (no dual graphics) + 4GB + FreeDOS = 59-410323 >>>>>>> 2) only 8650G (no dual graphics) + 8GB + FreeDOS = 59-405169 >>>>>>> 3) only 8650G (no dual graphics) + 4GB + Windows 8 = 59-380131 >>>>>>> 4) only 8650G (no dual graphics) + 6GB + Windows 8 = 59-373010 / >>>>>>> 59-406417 >>>>>>> 5) only 8650G (no dual graphics) + 8GB + Windows 8 = 59-403088 >>>>>>> 6) 8650G + AMD HD 8570M (dual graphics) + 4GB + FreeDOS = 59-405168 >>>>>>> 7) 8650G + AMD HD 8570M (dual graphics) + 6GB + FreeDOS = 59-409773 >>>>>>> 8) 8650G + AMD HD 8570M (dual graphics) + 8GB + FreeDOS = 59-380146 >>>>>>> / 59-387536 >>>>>>> 9) 8650G + AMD HD 8570M (dual graphics) + 4GB + Windows 8 = >>>>>>> 59-407135 / 59410966 >>>>>>> 10) 8650G + AMD HD 8570M (dual graphics) + 6GB + Windows 8 = >>>>>>> 59-382102 >>>>>>> 11) 8650G + AMD HD 8570M (dual graphics) + 8GB + Windows 8 = >>>>>>> 59-401209 >>>>>>> 12) 8650G + AMD R5 M230 (dual graphics, slightly faster) + 4GB + >>>>>>> FreeDOS = 59-410881 >>>>>>> 13) 8650G + AMD R5 M230 (dual graphics, slightly faster) + 8GB + >>>>>>> FreeDOS = 59-410885 >>>>>>> 14) 8650G + AMD R5 M230 (dual graphics, slightly faster) + 4GB + >>>>>>> Windows 8 = 59-408604 >>>>>>> 15) 8650G + AMD R5 M230 (dual graphics, slightly faster) + 8GB + >>>>>>> Windows 8 = 59-410883 >>>>>>> >>>>>>> On 6 April 2015 at 14:20, Emilian Bold <emilian.bold(a)gmail.com> >>>>>>> wrote: >>>>>>> >>>>>>>> I can confirm I'm still able to buy a G505S in my country but it >>>>>>>> seems to have the quad core A8-4500M (not the A10) with a dedicated >>>>>>>> Radeon HD 8570M. >>>>>>>> >>>>>>>> It's a decent machine and it would be great to have it on the >>>>>>>> official LTS list. >>>>>>>> >>>>>>>> Speaking of the list, I cannot find any store selling the Toshiba >>>>>>>> Satellite C50D-A mentioned in the wiki. >>>>>>>> >>>>>>>> --emi >>>>>>>> >>>>>>>> >>>>>>>> On Mon, Apr 6, 2015 at 1:45 PM, Vladimir <quickcracktime(a)gmail.com> >>>>>>>> wrote: >>>>>>>> >>>>>>>>> Dear coreboot developers, >>>>>>>>> >>>>>>>>> Francis Rowe (main Libreboot developer) has hinted an idea about >>>>>>>>> adding Lenovo G505S to Coreboot LTS Candidates list of laptops, which is >>>>>>>>> hosted at MrNuke's User talk coreboot wiki page. I believe it is an >>>>>>>>> excellent idea, because: >>>>>>>>> >>>>>>>>> *1)* Lenovo G505S contains AMD APU, so there is no need to deal >>>>>>>>> with Intel ME/AMT so-called "features" >>>>>>>>> *2)* this APU has Richland architecture: as result (unlike the >>>>>>>>> more recent AMD offerings) it doesn't have "AMD Secure" feature -- based on >>>>>>>>> ARM Trustzone technology which already has some exploits against it; there >>>>>>>>> are security concerns about ARM Trustzone that are similar to concerns >>>>>>>>> about Intel vPro "feature" (remote management etc.) >>>>>>>>> *3)* this APU is A10-5750M, the most powerful mobile APU among >>>>>>>>> Richland designs - as result, this laptop is still very competitive >>>>>>>>> regarding its performance, and also price/performance >>>>>>>>> *4)* Unlike the older HP M6-1035DX amd laptop, Lenovo G505S seems >>>>>>>>> to be a very popular model: even now, more than 1.5 years after its' >>>>>>>>> introduction, there are >200 Internet shops in my large city still selling >>>>>>>>> it new in box - not used/refurbished >>>>>>>>> *5)* Lenovo G505s works without microcode updates, and already >>>>>>>>> has a working Coreboot build (although Video BIOS and SMU firmware have >>>>>>>>> blobs that are still not reverse-engineered; and some minor issues - e.g. >>>>>>>>> ACPI not perfect yet ) >>>>>>>>> >>>>>>>>> These great points are making me wonder, why this interesting >>>>>>>>> laptop still haven't been added to that LTS Candidates list? Does it fail >>>>>>>>> to meet some requirement for LTS candidates in a not-obvious way >>>>>>>>> (RYF-certifiable,Sturdy,Long shelf-life,Cool factor) or there is some >>>>>>>>> not-listed AMD laptop that could be a better candidate? >>>>>>>>> >>>>>>>>> By the way, I have discovered that there are many modifications of >>>>>>>>> Lenovo G505S, which could be divided into three primary groups by their >>>>>>>>> major difference - GPU *(minor differences, such as different >>>>>>>>> size of RAM or hard drive, are not interesting)* >>>>>>>>> GPU modification groups: >>>>>>>>> *1)* only 8650G, which is built-in into APU (no dual graphics) >>>>>>>>> *2)* 8650G + AMD HD 8570M (dual graphics) >>>>>>>>> *3)* 8650G + AMD R5 M230 ( dual graphics, slightly more powerful >>>>>>>>> than "2)" ) >>>>>>>>> Are these modifications all supported by Coreboot? And would be >>>>>>>>> there any additional difficulties regarding modifications with dual >>>>>>>>> graphics? >>>>>>>>> >>>>>>>>> Your answers and opinions will be very welcome >>>>>>>>> Best regards, >>>>>>>>> Vladimir Shipovalov >>>>>>>>> >>>>>>>>> -- >>>>>>>>> coreboot mailing list: coreboot(a)coreboot.org >>>>>>>>> http://www.coreboot.org/mailman/listinfo/coreboot >>>>>>>>> >>>>>>>> >>>>>>>> >>>>>>> >>>>>> >>>>> >>>> >>> >> >

5 years, 10 months

QEMU x86_64 Q35 Automated Test Failure

by Raptor Engineering Automated Test Stand

The QEMU x86_64 Q35 does not boot as of commit c14e42623bede2480284cf500362d545f85f8f69 Commits since last successful test: See attached boot log for details This message was automatically generated from Raptor Engineering's QEMU x86_64 Q35 test stand Raptor Engineering offers coreboot consulting services! Please visit https://www.raptorengineeringinc.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineeringinc.com> regarding any issues stemming from this notification

5 years, 10 months

force https on review.coreboot.org

by Alexander Couzens

Hi, review isn't forcing https. Can we please do this? Otherwise stealing cookies is posibble. Review supports https. There is atm an CACert based certificate and CaCert isn't included in the default root keychain. Thus a normal user will shown a big fat warning, not to connect to review.coreboot.org, because the certificate is unknown and untrusted. I don't have a problem with that and I like CaCert. But if CaCert is the reason not enabling https-only, than let us change to StartSSL or someother SSL authority. Best lynxis PS. Same issue on www.coreboot.org, but stealing review is much more worse than stealing wiki cookies. PPS. Please write a +1 if you're supporting this opinion. -- Alexander Couzens mail: lynxis(a)fe80.eu jabber: lynxis(a)jabber.ccc.de mobile: +4915123277221

5 years, 10 months

Gerrit access rules

by Patrick Georgi

Hi, after deliberation to encourage positive feedback, gerrit rules are changed so that 'reviewers' can now give +2 Code-Reviews. Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Graham Law, Christine Elizabeth Flores

5 years, 10 months

How to assign a fixed resource to PCI BAR?

by WANG FEI

Hi, coreboot folks, I'm trying to assign a fixed resource to a specific PCI BAR, does any know how to do it? Also is there a switch to change the PCI enumeration order? for example, PCI devices enumerate from high device number to low device number? Thanks.

5 years, 10 months

fsp_baytrail default SMM_TSEG_SIZE value

by David Imhoff

Hi, Running the current Coreboot on a Minnowboard Max I ran into the following error when booting: Unable to install SMM permanent handler. Error loading SMM handlers. This results in the boot hanging at the smm_setup_structures() call in write_acpi_tables(). The above error seems to be caused by the SMM_TSEG_SIZE having a value of 0x100000. The install_permanent_handler() function in src/soc/intel/fsp_baytrail/cpu.c uses this value minus CONFIG_SMM_RESERVED_SIZE(=0x100000) as argument to smm_load_module(). smm_load_module() expects the size passed be be at least SMM_DEFAULT_SIZE(=0x10000), but in this case size is 0x100000 - 0x100000 = 0. So smm_load_module() fails, causing the installation of the SMM permanent handlers to fail. I saw most other SOC's, including non-fsp 'baytrail', use a default of 0x800000. Also the smm_region_size() function in src/soc/intel/fsp_baytrail/baytrail/smm.h defaults to 0x800000 if SMM_TSEG_SIZE is equal to 0. When I change the SMM_TSEG_SIZE value to 0x800000 my Minnowboard Max is able to boot. So I wonder what the reason is for setting SMM_TSEG_SIZE to 0x100000 for fsp_baytrail SOC's instead of 0x800000 or 0? Also why is there a difference between the smm_region_size() default and the Kconfig default? Kind regards, David .config: ---------------------------------------------------------------------- # # Automatically generated file; DO NOT EDIT. # coreboot configuration # # # General setup # # CONFIG_EXPERT is not set CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_USE_OPTION_TABLE is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_EARLY_CBMEM_INIT=y # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set CONFIG_RELOCATABLE_MODULES=y # CONFIG_RELOCATABLE_RAMSTAGE is not set CONFIG_BOOTBLOCK_SIMPLE=y # CONFIG_BOOTBLOCK_NORMAL is not set CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_UPDATE_IMAGE is not set # CONFIG_RAM_CODE_SUPPORT is not set # # Mainboard # # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set # CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_ADVANSUS is not set # CONFIG_VENDOR_AMD is not set # CONFIG_VENDOR_AOPEN is not set # CONFIG_VENDOR_APPLE is not set # CONFIG_VENDOR_ARIMA is not set # CONFIG_VENDOR_ARTECGROUP is not set # CONFIG_VENDOR_ASROCK is not set # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AVALUE is not set # CONFIG_VENDOR_AZZA is not set # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BCOM is not set # CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set # CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_IEI is not set CONFIG_VENDOR_INTEL=y # CONFIG_VENDOR_IWAVE is not set # CONFIG_VENDOR_IWILL is not set # CONFIG_VENDOR_JETWAY is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LANNER is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set # CONFIG_VENDOR_NEWISYS is not set # CONFIG_VENDOR_NOKIA is not set # CONFIG_VENDOR_NVIDIA is not set # CONFIG_VENDOR_PACKARDBELL is not set # CONFIG_VENDOR_PCENGINES is not set # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set # CONFIG_VENDOR_SUPERMICRO is not set # CONFIG_VENDOR_TECHNEXION is not set # CONFIG_VENDOR_TI is not set # CONFIG_VENDOR_THOMSON is not set # CONFIG_VENDOR_TRAVERSE is not set # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="intel/minnowmax" CONFIG_MAINBOARD_PART_NUMBER="Minnow Max" CONFIG_MAINBOARD_VENDOR="Intel" CONFIG_MAX_CPUS=16 CONFIG_VGA_BIOS_ID="8086,0f31" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_VGA_BIOS=y # CONFIG_UDELAY_IO is not set CONFIG_DCACHE_RAM_BASE=0xfef00000 CONFIG_DCACHE_RAM_SIZE=0x4000 CONFIG_VGA_BIOS_FILE="../BAY_TRAIL_FSP_KIT/Graphics/INTEL_EMGD.VBIOS_GOLD_VERSION_36_2_3_3698/Vga.dat" CONFIG_MMCONF_BASE_ADDRESS=0xe0000000 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel" # CONFIG_PCI_64BIT_PREF_MEM is not set CONFIG_UART_FOR_CONSOLE=0 CONFIG_ID_SECTION_OFFSET=0x80 CONFIG_RAMTOP=0x200000 CONFIG_BOOT_MEDIA_SPI_BUS=0 CONFIG_TTYS0_LCS=3 # CONFIG_BOARD_INTEL_BAKERSPORT_FSP is not set # CONFIG_BOARD_INTEL_BAYLEYBAY_FSP is not set # CONFIG_BOARD_INTEL_COUGAR_CANYON2 is not set # CONFIG_BOARD_INTEL_D810E2CB is not set # CONFIG_BOARD_INTEL_D945GCLF is not set # CONFIG_BOARD_INTEL_EAGLEHEIGHTS is not set # CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set CONFIG_BOARD_INTEL_MINNOWMAX=y # CONFIG_BOARD_INTEL_MOHONPEAK is not set # CONFIG_BOARD_INTEL_MTARVON is not set # CONFIG_BOARD_INTEL_TRUXTON is not set # CONFIG_BOARD_INTEL_BASKING_RIDGE is not set # CONFIG_BOARD_INTEL_WTM2 is not set CONFIG_INCLUDE_ME=y # CONFIG_LOCK_MANAGEMENT_ENGINE is not set CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x800000 CONFIG_FSP_FILE="../BAY_TRAIL_FSP_KIT/FSP/BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd" CONFIG_MRC_CACHE_LOC_OVERRIDE=0xfff80000 CONFIG_CBFS_SIZE=0x00300000 CONFIG_ENABLE_FSP_FAST_BOOT=y CONFIG_VIRTUAL_ROM_SIZE=0x800000 # CONFIG_POST_IO is not set # CONFIG_POST_DEVICE is not set CONFIG_SEABIOS_MALLOC_UPPERMEMORY=y CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 CONFIG_MAINBOARD_VERSION="1.0" # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set # CONFIG_COREBOOT_ROMSIZE_KB_128 is not set # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set # CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set CONFIG_COREBOOT_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set CONFIG_COREBOOT_ROMSIZE_KB=8192 CONFIG_ROM_SIZE=0x800000 # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set # CONFIG_ARCH_VERSTAGE_ARM64 is not set # CONFIG_ARCH_ROMSTAGE_ARM64 is not set # CONFIG_ARCH_RAMSTAGE_ARM64 is not set # CONFIG_ARCH_USE_SECURE_MONITOR is not set # CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set # CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set # CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set # CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set # CONFIG_ARM64_BOOTBLOCK_CUSTOM is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set # CONFIG_ARCH_VERSTAGE_ARM is not set # CONFIG_ARCH_ROMSTAGE_ARM is not set # CONFIG_ARCH_RAMSTAGE_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set # CONFIG_ARCH_VERSTAGE_ARMV4 is not set # CONFIG_ARCH_ROMSTAGE_ARMV4 is not set # CONFIG_ARCH_RAMSTAGE_ARMV4 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set # CONFIG_ARCH_VERSTAGE_ARMV7 is not set # CONFIG_ARCH_ROMSTAGE_ARMV7 is not set # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set # CONFIG_ARM_BOOTBLOCK_CUSTOM is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_BOOTBLOCK_MIPS is not set # CONFIG_ARCH_VERSTAGE_MIPS is not set # CONFIG_ARCH_ROMSTAGE_MIPS is not set # CONFIG_ARCH_RAMSTAGE_MIPS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_BOOTBLOCK_RISCV is not set # CONFIG_ARCH_VERSTAGE_RISCV is not set # CONFIG_ARCH_ROMSTAGE_RISCV is not set # CONFIG_ARCH_RAMSTAGE_RISCV is not set # CONFIG_RISCV_BOOTBLOCK_CUSTOM is not set # CONFIG_CPU_HAS_BOOTBLOCK_INIT is not set # CONFIG_MAINBOARD_HAS_BOOTBLOCK_INIT is not set CONFIG_ARCH_X86=y CONFIG_ARCH_BOOTBLOCK_X86_32=y CONFIG_ARCH_VERSTAGE_X86_32=y CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_AP_IN_SIPI_WAIT is not set # CONFIG_SIPI_VECTOR_IN_ROM is not set CONFIG_RAMBASE=0x100000 CONFIG_NUM_IPI_STARTS=2 # CONFIG_ROMCC is not set # CONFIG_LATE_CBMEM_INIT is not set CONFIG_PC80_SYSTEM=y # CONFIG_HAVE_CMOS_DEFAULT is not set CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set CONFIG_HPET_ADDRESS=0xfed00000 # CONFIG_MAINBOARD_HAS_CHROMEOS is not set CONFIG_FSP_VENDORCODE_HEADER_PATH="fsp/baytrail" # CONFIG_SYSTEM_TYPE_LAPTOP is not set # # Chipset # # # CPU # # CONFIG_CPU_ALLWINNER_A10 is not set CONFIG_CPU_SPECIFIC_OPTIONS=y CONFIG_XIP_ROM_SIZE=0x10000 # CONFIG_CPU_AMD_AGESA is not set # CONFIG_CPU_AMD_PI is not set # CONFIG_CPU_ARMLTD_CORTEX_A9 is not set CONFIG_BOOTBLOCK_CPU_INIT="soc/intel/fsp_baytrail/bootblock/bootblock.c" CONFIG_SMM_TSEG_SIZE=0x100000 CONFIG_CPU_MICROCODE_CBFS_LOC=0xfff10040 CONFIG_MICROCODE_INCLUDE_PATH="../BAY_TRAIL_FSP_KIT/Microcode/" CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SSE2=y # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set # CONFIG_UDELAY_LAPIC is not set CONFIG_UDELAY_TSC=y CONFIG_TSC_CONSTANT_RATE=y CONFIG_TSC_MONOTONIC_TIMER=y # CONFIG_UDELAY_TIMER2 is not set # CONFIG_TSC_CALIBRATE_WITH_IO is not set # CONFIG_TSC_SYNC_LFENCE is not set CONFIG_TSC_SYNC_MFENCE=y CONFIG_LOGICAL_CPUS=y CONFIG_SMM_TSEG=y CONFIG_SMM_MODULES=y CONFIG_SMM_MODULE_HEAP_SIZE=0x4000 # CONFIG_X86_AMD_FIXED_MTRRS is not set CONFIG_PLATFORM_USES_FSP=y CONFIG_PARALLEL_MP=y # CONFIG_BACKUP_DEFAULT_SMM_REGION is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set CONFIG_CACHE_AS_RAM=y CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD=y CONFIG_CPU_MICROCODE_CBFS_GENERATE=y # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set # CONFIG_CPU_MICROCODE_CBFS_NONE is not set # # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set CONFIG_HEAP_SIZE=0x4000 # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set CONFIG_FSP_LOC=0xfffc0000 CONFIG_MRC_CACHE_SIZE=0x10000 CONFIG_MAX_PIRQ_LINKS=4 # # Southbridge # # CONFIG_AMD_SB_CIMX is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set CONFIG_ME_PATH="../maxfirmware/" # # Super I/O # # # Embedded Controllers # # # SoC # # CONFIG_ENABLE_BUILTIN_COM1 is not set CONFIG_TTYS0_BASE=0x3f8 CONFIG_SOC_INTEL_FSP_BAYTRAIL=y # CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD is not set CONFIG_BAYTRAIL_FSP_SPECIFIC_OPTIONS=y # CONFIG_SOC_MARVELL_BG4CD is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set # CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_QC_IPQ806X is not set # CONFIG_SOC_ROCKCHIP_RK3288 is not set # CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set # CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set # CONFIG_SOC_UCB_RISCV is not set # # Intel FSP # CONFIG_HAVE_FSP_BIN=y CONFIG_ENABLE_MRC_CACHE=y CONFIG_MRC_CACHE_LOC=0xfff50000 CONFIG_USE_GENERIC_FSP_CAR_INC=y CONFIG_FSP_USES_UPD=y # # Devices # # CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set CONFIG_NATIVE_VGA_INIT_USE_EDID=y # CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set # CONFIG_SPD_CACHE is not set CONFIG_PCI=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set # CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_EARLY_PCI_BRIDGE is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_PXE_ROM is not set # CONFIG_SOFTWARE_I2C is not set # # Generic Drivers # # CONFIG_DRIVERS_AS3722_RTC is not set # CONFIG_ELOG is not set # CONFIG_GIC is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set # CONFIG_INTEL_DP is not set # CONFIG_INTEL_DDI is not set # CONFIG_INTEL_EDID is not set # CONFIG_INTEL_INT15 is not set # CONFIG_DRIVER_INTEL_I210 is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_LPC_TPM is not set # CONFIG_DRIVERS_RICOH_RCE822 is not set # CONFIG_DRIVERS_SIL_3114 is not set CONFIG_SPI_FLASH=y CONFIG_SPI_ATOMIC_SEQUENCING=y CONFIG_SPI_FLASH_MEMORY_MAPPED=y # CONFIG_SPI_FLASH_SMM is not set # CONFIG_SPI_FLASH_NO_FAST_READ is not set CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set CONFIG_DRIVERS_UART=y CONFIG_DRIVERS_UART_8250IO=y # CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_DRIVERS_UART_8250MEM is not set # CONFIG_HAVE_UART_SPECIAL is not set # CONFIG_DRIVERS_UART_OXPCIE is not set # CONFIG_DRIVERS_UART_PL011 is not set # CONFIG_HAVE_USBDEBUG is not set # CONFIG_HAVE_USBDEBUG_OPTIONS is not set CONFIG_DEVICE_SPECIFIC_OPTIONS=y # CONFIG_DRIVER_XPOWERS_AXP209 is not set # CONFIG_TPM is not set CONFIG_STACK_SIZE=0x1000 CONFIG_MMCONF_SUPPORT_DEFAULT=y CONFIG_MMCONF_SUPPORT=y # CONFIG_BOOTMODE_STRAPS is not set # # Console # CONFIG_SQUELCH_EARLY_SMP=y CONFIG_CONSOLE_SERIAL=y # # I/O mapped, 8250-compatible # CONFIG_CONSOLE_SERIAL_115200=y # CONFIG_CONSOLE_SERIAL_57600 is not set # CONFIG_CONSOLE_SERIAL_38400 is not set # CONFIG_CONSOLE_SERIAL_19200 is not set # CONFIG_CONSOLE_SERIAL_9600 is not set CONFIG_TTYS0_BAUD=115200 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set # CONFIG_CONSOLE_CBMEM is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_NO_POST is not set # CONFIG_CMOS_POST is not set # CONFIG_CONSOLE_POST is not set CONFIG_HAVE_ACPI_RESUME=y # CONFIG_HAVE_ACPI_SLIC is not set CONFIG_HAVE_HARD_RESET=y CONFIG_HAVE_MONOTONIC_TIMER=y # CONFIG_GENERIC_UDELAY is not set # CONFIG_TIMER_QUEUE is not set CONFIG_HAVE_OPTION_TABLE=y # CONFIG_PIRQ_ROUTE is not set CONFIG_HAVE_SMI_HANDLER=y # CONFIG_PCI_IO_CFG_EXT is not set # CONFIG_IOAPIC is not set # CONFIG_USE_WATCHDOG_ON_BOOT is not set CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y # CONFIG_PER_DEVICE_ACPI_TABLES is not set # CONFIG_COMMON_FADT is not set # # System tables # # CONFIG_GENERATE_MP_TABLE is not set # CONFIG_GENERATE_PIRQ_TABLE is not set CONFIG_GENERATE_SMBIOS_TABLES=y CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Minnow Max" # # Payload # # CONFIG_PAYLOAD_NONE is not set # CONFIG_PAYLOAD_ELF is not set # CONFIG_PAYLOAD_LINUX is not set CONFIG_PAYLOAD_SEABIOS=y # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_TIANOCORE is not set CONFIG_SEABIOS_STABLE=y # CONFIG_SEABIOS_MASTER is not set # CONFIG_SEABIOS_THREAD_OPTIONROMS is not set CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf" CONFIG_COMPRESSED_PAYLOAD_LZMA=y # # Debugging # # CONFIG_GDB_STUB is not set # CONFIG_DEBUG_CBFS is not set # CONFIG_HAVE_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set # CONFIG_HAVE_DEBUG_SMBUS is not set # CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_SMM_RELOCATION is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_TRACE is not set # CONFIG_GENERIC_GPIO_LIB is not set # CONFIG_BOARD_ID_SUPPORT is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set # CONFIG_POWER_BUTTON_FORCE_DISABLE is not set # CONFIG_POWER_BUTTON_IS_OPTIONAL is not set CONFIG_REG_SCRIPT=y CONFIG_MAX_REBOOT_CNT=3 Boot log: ---------------------------------------------------------------------- romstage_main_continue status: 0 hob_list_ptr: 7bb20000 FSP Status: 0x0 PM1_STS = 0x0 PM1_CNT = 0x0 GEN_PMCON1 = 0x1001808 romstage_main_continue: prev_sleep_state = S0 Baytrail Chip Variant: Bay Trail-I (ISG/embedded) MRC v0.100 1 channels of DDR3 @ 1066MHz CBMEM: root @ 7baff000 254 entries. Trying CBFS ramstage loader. CBFS: loading stage @ 0x100000 (221516 bytes), entry @ 0x100000 CBMEM: recovering 3/254 entries from root @ 7baff000 Moving GDT to 7bafc000...ok coreboot-4.0-9183-g5984aad wo apr 15 05:33:27 UTC 2015 ramstage starting... Normal boot. clocks_per_usec: 1333 BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0 CPUID: 00030673 Cores: 2 Revision ID: 0c Stepping: B3 msr(17) = 0000000c90040a3b msr(ce) = 0000040000000a00 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 10731 exit 0 Enumerating buses... enable_dev(Intel BayTrail SoC, 7) CPU_CLUSTER: 0 enabled enable_dev(Intel BayTrail SoC, 6) DOMAIN: 0000 enabled PCI: pci_scan_bus for bus 00 enable_dev(Intel BayTrail SoC, 2) FSP Header Version: 1 FSP Revision: 3.3 PCI: 00:00.0 [8086/0f00] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:02.0 [8086/0f31] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:03.0: Disabling device: 03.0 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:10.0: Disabling device: 10.0 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:11.0: Disabling device: 11.0 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:12.0 [8086/0f16] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:13.0 [8086/0f23] enabled enable_dev(Intel BayTrail SoC, 2) PCI: Static device PCI: 00:14.0 not found, disabling it. enable_dev(Intel BayTrail SoC, 2) PCI: 00:15.0 [8086/0f28] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:17.0: Disabling device: 17.0 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.0 [8086/0f40] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.1: Disabling device: 18.1 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.2 [8086/0f42] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.3: Disabling device: 18.3 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.4: Disabling device: 18.4 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.5: Disabling device: 18.5 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.6 [8086/0f46] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.7 [8086/0f47] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1a.0 [8086/0f18] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1b.0: Disabling device: 1b.0 PCI: 00:1b.0 [8086/0f04] disabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1c.0 subordinate bus PCI Express PCI: 00:1c.0 [8086/0f48] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1c.1: Disabling device: 1c.1 Power management CAP offset 0xa0. enable_dev(Intel BayTrail SoC, 2) PCI: 00:1c.2 subordinate bus PCI Express PCI: 00:1c.2 [8086/0f4c] enabled enable_dev(Intel BayTrail SoC, 2) PCI: Static device PCI: 00:1c.3 not found, disabling it. enable_dev(Intel BayTrail SoC, 2) PCI: 00:1d.0 [8086/0f34] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1e.0 [8086/0f06] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1e.1 [8086/0f08] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1e.2 [8086/0f09] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1e.3 [8086/0f0a] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1e.4 [8086/0f0c] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1e.5 [8086/0f0e] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1f.0 [8086/0f1c] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1f.3 [8086/0f12] enabled PCI: pci_scan_bus for bus 01 PCI: pci_scan_bus returning with max=001 PCI: pci_scan_bus for bus 02 PCI: 02:00.0 [10ec/8168] enabled PCI: pci_scan_bus returning with max=002 PCI: pci_scan_bus returning with max=002 done BS: BS_DEV_ENUMERATE times (us): entry 0 run 305739 exit 0 found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... APIC: 00 missing read_resources UMA, GTT & SMM memory location: 0x7bd00000 UMA, GTT & SMM memory size: 67M FSP memory location: 0x7bb00000 FSP memory size: 2M Available memory below 4GB: 0x7bb00000 (1979M) Available memory above 4GB: 0M Adding PCIe config bar base=0xe0000000 size=0x10000000 Done reading resources. Setting resources... PCI: 00:00.0 missing set_resources PCI: 00:02.0 10 <- [0x00d0000000 - 0x00d03fffff] size 0x00400000 gran 0x16 mem PCI: 00:02.0 18 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem PCI: 00:02.0 20 <- [0x0000002040 - 0x0000002047] size 0x00000008 gran 0x03 io PCI: 00:12.0 10 <- [0x00d0a08000 - 0x00d0a08fff] size 0x00001000 gran 0x0c mem PCI: 00:12.0 14 <- [0x00d0a09000 - 0x00d0a09fff] size 0x00001000 gran 0x0c mem PCI: 00:13.0 10 <- [0x0000002048 - 0x000000204f] size 0x00000008 gran 0x03 io PCI: 00:13.0 14 <- [0x0000002058 - 0x000000205b] size 0x00000004 gran 0x02 io PCI: 00:13.0 18 <- [0x0000002050 - 0x0000002057] size 0x00000008 gran 0x03 io PCI: 00:13.0 1c <- [0x000000205c - 0x000000205f] size 0x00000004 gran 0x02 io PCI: 00:13.0 20 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io PCI: 00:13.0 24 <- [0x00d0a1d000 - 0x00d0a1d7ff] size 0x00000800 gran 0x0b mem PCI: 00:15.0 10 <- [0x00d0400000 - 0x00d05fffff] size 0x00200000 gran 0x15 mem PCI: 00:15.0 14 <- [0x00d0a0a000 - 0x00d0a0afff] size 0x00001000 gran 0x0c mem PCI: 00:18.0 10 <- [0x00d0a00000 - 0x00d0a03fff] size 0x00004000 gran 0x0e mem PCI: 00:18.0 14 <- [0x00d0a0b000 - 0x00d0a0bfff] size 0x00001000 gran 0x0c mem PCI: 00:18.2 10 <- [0x00d0a0c000 - 0x00d0a0cfff] size 0x00001000 gran 0x0c mem PCI: 00:18.2 14 <- [0x00d0a0d000 - 0x00d0a0dfff] size 0x00001000 gran 0x0c mem PCI: 00:18.6 10 <- [0x00d0a0e000 - 0x00d0a0efff] size 0x00001000 gran 0x0c mem PCI: 00:18.6 14 <- [0x00d0a0f000 - 0x00d0a0ffff] size 0x00001000 gran 0x0c mem PCI: 00:18.7 10 <- [0x00d0a10000 - 0x00d0a10fff] size 0x00001000 gran 0x0c mem PCI: 00:18.7 14 <- [0x00d0a11000 - 0x00d0a11fff] size 0x00001000 gran 0x0c mem PCI: 00:1a.0 10 <- [0x00d0600000 - 0x00d06fffff] size 0x00100000 gran 0x14 mem PCI: 00:1a.0 14 <- [0x00d0700000 - 0x00d07fffff] size 0x00100000 gran 0x14 mem PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:1c.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:1c.0 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 mem PCI: 00:1c.2 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 02 io PCI: 00:1c.2 24 <- [0x00d0800000 - 0x00d08fffff] size 0x00100000 gran 0x14 bus 02 prefmem PCI: 00:1c.2 20 <- [0x00d0900000 - 0x00d09fffff] size 0x00100000 gran 0x14 bus 02 mem PCI: 02:00.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 02:00.0 18 <- [0x00d0900000 - 0x00d0900fff] size 0x00001000 gran 0x0c mem64 PCI: 02:00.0 20 <- [0x00d0800000 - 0x00d0803fff] size 0x00004000 gran 0x0e prefmem64 PCI: 00:1d.0 10 <- [0x00d0a1d800 - 0x00d0a1dbff] size 0x00000400 gran 0x0a mem PCI: 00:1e.0 10 <- [0x00d0a04000 - 0x00d0a07fff] size 0x00004000 gran 0x0e mem PCI: 00:1e.0 14 <- [0x00d0a12000 - 0x00d0a12fff] size 0x00001000 gran 0x0c mem PCI: 00:1e.1 10 <- [0x00d0a13000 - 0x00d0a13fff] size 0x00001000 gran 0x0c mem PCI: 00:1e.1 14 <- [0x00d0a14000 - 0x00d0a14fff] size 0x00001000 gran 0x0c mem PCI: 00:1e.2 10 <- [0x00d0a15000 - 0x00d0a15fff] size 0x00001000 gran 0x0c mem PCI: 00:1e.2 14 <- [0x00d0a16000 - 0x00d0a16fff] size 0x00001000 gran 0x0c mem PCI: 00:1e.3 10 <- [0x00d0a17000 - 0x00d0a17fff] size 0x00001000 gran 0x0c mem PCI: 00:1e.3 14 <- [0x00d0a18000 - 0x00d0a18fff] size 0x00001000 gran 0x0c mem PCI: 00:1e.4 10 <- [0x00d0a19000 - 0x00d0a19fff] size 0x00001000 gran 0x0c mem PCI: 00:1e.4 14 <- [0x00d0a1a000 - 0x00d0a1afff] size 0x00001000 gran 0x0c mem PCI: 00:1e.5 10 <- [0x00d0a1b000 - 0x00d0a1bfff] size 0x00001000 gran 0x0c mem PCI: 00:1e.5 14 <- [0x00d0a1c000 - 0x00d0a1cfff] size 0x00001000 gran 0x0c mem PCI: 00:1f.3 10 <- [0x00d0a1dc00 - 0x00d0a1dc1f] size 0x00000020 gran 0x05 mem PCI: 00:1f.3 20 <- [0x0000002020 - 0x000000203f] size 0x00000020 gran 0x05 io Done setting resources. Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 428138 exit 0 Enabling resources... PCI: 00:02.0 subsystem <- 0000/0000 PCI: 00:02.0 cmd <- 07 PCI: 00:12.0 subsystem <- 0000/0000 PCI: 00:12.0 cmd <- 106 PCI: 00:13.0 subsystem <- 0000/0000 PCI: 00:13.0 cmd <- 107 PCI: 00:15.0 subsystem <- 0000/0000 PCI: 00:15.0 cmd <- 102 PCI: 00:18.0 subsystem <- 0000/0000 PCI: 00:18.0 cmd <- 106 PCI: 00:18.2 subsystem <- 0000/0000 PCI: 00:18.2 cmd <- 102 PCI: 00:18.6 subsystem <- 0000/0000 PCI: 00:18.6 cmd <- 102 PCI: 00:18.7 subsystem <- 0000/0000 PCI: 00:18.7 cmd <- 102 PCI: 00:1a.0 subsystem <- 0000/0000 PCI: 00:1a.0 cmd <- 102 PCI: 00:1c.0 bridge ctrl <- 0003 PCI: 00:1c.0 cmd <- 100 PCI: 00:1c.2 bridge ctrl <- 0003 PCI: 00:1c.2 cmd <- 107 PCI: 00:1d.0 subsystem <- 0000/0000 PCI: 00:1d.0 cmd <- 102 PCI: 00:1e.0 subsystem <- 0000/0000 PCI: 00:1e.0 cmd <- 106 PCI: 00:1e.1 subsystem <- 0000/0000 PCI: 00:1e.1 cmd <- 102 PCI: 00:1e.2 subsystem <- 0000/0000 PCI: 00:1e.2 cmd <- 102 PCI: 00:1e.3 subsystem <- 0000/0000 PCI: 00:1e.3 cmd <- 102 PCI: 00:1e.4 subsystem <- 0000/0000 PCI: 00:1e.4 cmd <- 102 PCI: 00:1e.5 subsystem <- 0000/0000 PCI: 00:1e.5 cmd <- 102 PCI: 00:1f.3 subsystem <- 0000/0000 PCI: 00:1f.3 cmd <- 103 PCI: 02:00.0 cmd <- 03 done. BS: BS_DEV_ENABLE times (us): entry 0 run 115150 exit 0 Initializing devices... Root Device init Root Device init 1653 usecs CPU_CLUSTER: 0 init MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Setting up local apic... apic_id: 0x00 done. CPU: Intel(R) Atom(TM) CPU E3825 @ 1.33GHz. Loading module at 00030000 with entry 00030000. filesize: 0x140 memsize: 0x140 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 1 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...done. AP: slot 1 apic_id 4. Waiting for 2nd SIPI to complete...done. Loading module at 00038000 with entry 00038000. filesize: 0x180 memsize: 0x180 Processing 10 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 00038000. Will call 001021c8(00000000) Installing SMM handler to 0x7bd00000 Unable to install SMM permanent handler. Error loading SMM handlers. New SMBASE 0x7bcffc00 Relocation complete. Initializing CPU #0 CPU: vendor Intel device 30673 CPU: family 06, model 37, stepping 03 Init BayTrail core. CPU #0 initialized Initializing CPU #1 CPU: vendor Intel device 30673 CPU: family 06, model 37, stepping 03 Init BayTrail core. Turbo is unavailable CPU #1 initialized Enabling SMIs. GPIO_ROUT = 00000000 ALT_GPIO_SMI = 00000000 CPU_CLUSTER: 0 init 121671 usecs PCI: 00:02.0 init PCI: 00:02.0 init 1751 usecs PCI: 00:12.0 init PCI: 00:12.0 init 1751 usecs PCI: 00:13.0 init PCI: 00:13.0 init 1751 usecs PCI: 00:15.0 init PCI: 00:15.0 init 1750 usecs PCI: 00:18.0 init PCI: 00:18.0 init 1750 usecs PCI: 00:18.2 init PCI: 00:18.2 init 1751 usecs PCI: 00:18.6 init PCI: 00:18.6 init 1751 usecs PCI: 00:18.7 init PCI: 00:18.7 init 1751 usecs PCI: 00:1a.0 init PCI: 00:1a.0 init 1750 usecs PCI: 00:1d.0 init PCI: 00:1d.0 init 1751 usecs PCI: 00:1e.0 init PCI: 00:1e.0 init 1750 usecs PCI: 00:1e.1 init PCI: 00:1e.1 init 1751 usecs PCI: 00:1e.2 init PCI: 00:1e.2 init 1751 usecs PCI: 00:1e.3 init PCI: 00:1e.3 init 1751 usecs PCI: 00:1e.4 init PCI: 00:1e.4 init 1751 usecs PCI: 00:1e.5 init PCI: 00:1e.5 init 1751 usecs PCI: 00:1f.0 init soc: southcluster_init Southbridge APIC ID = 2 PCI_CFG IRQ: Write PCI config space IRQ assignments Warning: PCI Device 2 does not have an IRQ entry, skipping it PCI_CFG IRQ: Finished writing PCI config space IRQ assignments PCI: 00:1f.0 init 23691 usecs PCI: 00:1f.3 init PCI: 00:1f.3 init 1751 usecs PCI: 02:00.0 init PCI: 02:00.0 init 1751 usecs Devices initialized BS: BS_DEV_INIT times (us): entry 0 run 242397 exit 0 Finalize devices... DOMAIN: 0000 final FspNotify(EnumInitPhaseAfterPciEnumeration) Devices finalized BS: BS_POST_DEVICE times (us): entry 0 run 10683 exit 0 BS: BS_OS_RESUME_CHECK times (us): entry 0 run 2 exit 0 === FSP HOB Data Structure === FSP Hoblistptr: 0x7bb20000 HOB 0x7bb20000 is an EFI_HOB_TYPE_HANDOFF (type 0x1) HOB 0x7bb20038 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) HOB 0x7bb200f0 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) HOB 0x7bb201e8 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) HOB 0x7bb21860 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) HOB 0x7bb21890 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) HOB 0x7bb218c0 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) HOB 0x7bb218f0 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) HOB 0x7bb21920 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) HOB 0x7bb21950 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) HOB 0x7bb21980 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb219b0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb219e0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb21a10 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) HOB 0x7bb25a28 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7bb25a60 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb25a90 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) HOB 0x7bb25c40 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb25c70 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb25ca0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb25cd0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb25d00 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb25d30 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb25d60 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb25d90 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb25dc0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb25df0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb25e20 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb25e50 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb25e80 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb25eb0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb25ee0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb25f10 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb25f40 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb25f70 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb25fa0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb25fd0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb26000 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb26030 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb26060 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb26090 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb260c0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7bb260d8 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7bb26118 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7bb26130 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7bb26178 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7bb26188 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7bb261a0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7bb261b0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7bb261c0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7bb261d0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7bb263d8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb26408 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7bb26528 is an EFI_HOB_TYPE_END_OF_HOB_LIST (type 0xffff) === End of FSP HOB Data Structure === Memory Configure Data Hob is not present Not updating MRC data in flash. ACPI: Writing ACPI tables at 7b9d6000. ACPI: * FACS @ 7b9d6210 Length 40ACPI: * DSDT @ 7b9d6250 Length 303fSCI is IRQ9 ACPI: added table 1/32, length now 40 ACPI: * FADT @ 7b9d9290 Length f4ACPI: added table 2/32, length now 44 ACPI: * HPET @ 7b9d9390 Length 38 ACPI: added table 3/32, length now 48 ACPI: * MADT @ 7b9d93d0 Length 5c ACPI: added table 4/32, length now 52 ACPI: * MCFG @ 7b9d9430 Length 3c ACPI: Patching up global NVS in DSDT at offset 0x009f -> 7bafa000 New SMBASE 0x7bd00000

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coreboot April 2015