coreboot April 2015

coreboot@coreboot.org

54 participants
92 discussions

Re: [coreboot] Kernel hang issue "All ACPI Tables successfully acquired"

by The Gluglug

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 X60/T60 couldn't boot on 3.19/higher without acpi=off. See: https://bugzilla.kernel.org/show_bug.cgi?id=93171 This patch fixed it: https://bugzilla.kernel.org/show_bug.cgi?id=93171#c25 And it's being merged: https://bugzilla.kernel.org/show_bug.cgi?id=93171#c32 That probably won't help you, so you'll have to open your own bug report. I used Qemu myself very recently, but I haven't tested GNU/Linux much on it (I use it mostly for testing payloads). On 15/04/15 07:37, Ajoy Das wrote: > Its qemu-system-i386. > > On Tue, Apr 14, 2015 at 11:17 PM, The Gluglug <info(a)gluglug.org.uk> > wrote: > > what computer is this? > > On 14/04/15 03:58, Ajoy Das wrote: >>>> Hi >>>> >>>> I am running coreboot on qemu with the following sequence. >>>> >>>> coreboot -> seabios -> GRUB -> kernel. >>>> >>>> The kernel booting hangs at *All ACPI Tables successfully >>>> acquired* >>>> >>>> coreboot-4.0 kernel 3.19 >>>> >>>> when I pass acpi=off to the kernel command line parameter >>>> the kernel boots fine in this scenario. >>>> >>>> >>>> Is there any specific coreboot option is there to be enabled >>>> for successful booting. or anyone knows of this issue. >>>> >>>> please help >>>> >>>> >>>> Thanks >>>> >>>> >>>> >> > > > -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAEBAgAGBQJVLhpJAAoJEP9Ft0z50c+UI9gH/2WwcYzlgaWmc4TuO09BPVdV 3saFE27F1iClAe9p3MqcziEWySGjaL6p6Y8YhLJIKHF8N0ZyghdratcwLzL68LpX V5HOhw84d/ra24rq1ZMMC7hf6GsUlqgvrefIiVCuApdlPWdDoq5j9X3lEqgC+3Yy jNHh8hLQXbfmV6wJ5ewY+36VubtJ0qMhRPHMcUNrrZozbPBKD+jyZrdw6T/mLguq G2ZYWr8ruWNPH6bi5tBEN6xlmh58sC1O16sb8cUkB8NX5OYAhJ3CQEnGwVF6xvZY B9lz0iQsfqokRCmqUe5vDiq4n8HobbF9DbSu41+oMKOYPMdSDi75Kb+FsZx1BH4= =LesB -----END PGP SIGNATURE-----

5 years, 10 months

Re: [coreboot] Kernel hang issue "All ACPI Tables successfully acquired"

by The Gluglug

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 what computer is this? On 14/04/15 03:58, Ajoy Das wrote: > Hi > > I am running coreboot on qemu with the following sequence. > > coreboot -> seabios -> GRUB -> kernel. > > The kernel booting hangs at *All ACPI Tables successfully > acquired* > > coreboot-4.0 kernel 3.19 > > when I pass acpi=off to the kernel command line parameter the > kernel boots fine in this scenario. > > > Is there any specific coreboot option is there to be enabled for > successful booting. or anyone knows of this issue. > > please help > > > Thanks > > > -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAEBAgAGBQJVLVK0AAoJEP9Ft0z50c+U9hEH/1ioHK9/hZCrKZqDYc+4rPCR 2jcPsaq2OPMX8zq5o6ljP3+Z5gHPyF8hDIMFyJHk5hi19vvxbVmPXMy9dTj1y8rs WGdAqHx/xbbdHh/CWXJ+JzgdZryfD7FN9L5RAXzVBMDjjRouUaI9eTObspSstRLD /LjlaAZdfWWK9doHPCJoeTZ7dJGE6e4GahxDJzCX0sJot2NtiukaTn6cbvPgt47V kStrxyVXxIJykZoxFI5+M1qo38IB6h6oZFOeUpL3MQXQxHnh0Ckmz3F30ySdMyir 7lN64p8utc4kroZtbmSlQVLpHbR7fpcu1opHWPwz0XTqhnwK1G1Oa0i0MAxvbFA= =L/lM -----END PGP SIGNATURE-----

5 years, 10 months

coreboot candidate: Dell Latitude E6400

by The Gluglug

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, This is GM45, like the X200 which is supported in coreboot (and libreboot). The issue: DDR2 RAM (raminit in coreboot for GM45 only supports DDR3, doesn't it?) and EC needs some work. There are a lot of these laptops available online, so I think it's a good porting target for coreboot. It would also be an instant libreboot port, once in coreboot, being GM45. What does the community think about this? Worth it? Regards, Francis Rowe. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAEBAgAGBQJVLVNyAAoJEP9Ft0z50c+UZnIH/0BLbeaqLRXq70huwdgjq2H1 mpB9rrfJ4cxUTd5rvWMNe0NmNsrhBdv2BpZ5bryLZEEa21qbDfP7FsZA0FCuXHdL 4aFk5nsBk1MrCD+6K0yeJrevPviVFEuLr3rTrs9JusKf44AcewTbcLH4zmUJ9VXB eRnVBNz1N7QdahD/ML5aEKNY2EEQxD11i+fNjYBYO1LsHnbJfEsxQGbDC1olSmc1 34ZPhgq8lkYpWodUbYtI1LPvMLcbQYuFC8ySwRhP+ml+zDldqJk5Pcg/fq8DNQiS 4ZDxUluCWXynD1vDFH7KRrtI5aA2t1YFXkbYi3SX3asRl30V+LZeufrvTQyeapc= =OpCs -----END PGP SIGNATURE-----

5 years, 10 months

Re: [coreboot] VGA doesn't work on Mohon Peak

by Kuzmichev Viktor

I did a bit more debugging and actually was able to test the board with different graphics card. So, with the nvidia adapter it works just fine, whereas with the aspeed controller in the same PCIe slot it hangs. I put in attachment to this email two logs, one with nvidia graphics card and another with aspeed controller. However, there's something else I consider worth mensioning. After SeaBIOS outputs 'Running option rom at c000:0003', there also some output appears on the monitor: AST1300/2300 VGA True Color Graphics and Video Accelerator VBIOS Version 0.96.00 DRAM Size: 64MB -Viktor On 19/03/15 21:20, Marc Jones wrote: > > Hi Viktor, > > On Thu, Mar 19, 2015 at 4:23 AM Kuzmichev Viktor > <kuzmichevviktorv(a)gmail.com <mailto:kuzmichevviktorv@gmail.com>> wrote: > > Hello, > > I'm using coreboot + SeaBIOS on Mohon Peak CRB. And I've tried to make > VGA work for a while now. I used this article as a guide: > http://www.coreboot.org/VGA_support > > > Since it is an add-in card, you don't need to extract the VBIOS and > put it into cbfs. The VBIOS on the card will run during the PCI card > enumeration. It seems that there is a problem with that specific > aspeed card and/or VBIOS. You may want to try a different card to > avoid the issue. Please let us know the results if you debug that card > further. > > Regards, > Marc > > Extracting VGA BIOS from vendor BIOS image did not work: > $ ./bios_extract EDVLCRB1.86B.0043.R00.1408290947_MPK.bin > Using file "EDVLCRB1.86B.0043.R00.1408290947_MPK.bin" (8192kB) > Error: Unable to detect BIOS Image type. > > Then, I've downloaded VGA BIOS from here: > http://www.aspeedtech.com/support.php > Mohon Peak uses Aspeed VGA controller AST1300. > > And also, I've extracted Video ROM from /dev/mem: > # dd if=/dev/mem of=vgabios.bin bs=1k count=32 skip=768 > > Neither of them worked. Here's what I've tried. I've tried to add them > via coreboot's menuconfig (' Add VGA BIOS image' option). I've > tried to > add them manually via cbfstool as an optionrom and as a raw file. I've > tried to put them in CBFS under vgaroms/ directory. Here's my latest > ROM-file layout: > $ ./build/cbfstool build/coreboot.rom print > coreboot.rom: 8192 kB, bootblocksize 1024, romsize 8388608, offset > 0x600000 > alignment: 64 bytes, architecture: x86 > > Name Offset Type Size > cmos_layout.bin 0x600000 cmos_layout 1352 > pci1a03,2000.rom 0x600580 optionrom 32768 > fallback/romstage 0x6085c0 stage 26616 > fallback/ramstage 0x60ee00 stage 59904 > fallback/payload 0x61d840 payload 56100 > config 0x62b3c0 raw 4532 > revision 0x62c5c0 raw 708 > pci8086,1f41.rom 0x62c8c0 raw 61952 > vgaroms/pci1a03,2000.rom 0x63bb00 raw 32768 > img/Memtest86+(5.01) 0x643b40 payload 159492 > (empty) 0x66aa80 null 939288 > mrc.cache 0x74ffc0 (unknown) 65536 > cpu_microcode_blob.bin 0x760000 microcode 83968 > (empty) 0x774840 null 46936 > fsp.bin 0x77ffc0 (unknown) 372736 > (empty) 0x7db000 null 150424 > > The entries pci1a03,2000.rom are the VGA ROMs there. I also tried to > remove either of them. I've tested with coreboot option 'Run VGA > Option > ROMs' checked and unchecked without any difference. In SeaBIOS I set > 'VGA Hardware Type (coreboot linear framebuffer)' as the other options > are None, GeodeGX2 and GeodeLX, so coreboot linear framebuffer seemed > more logical. > > I saw this mailing list: > http://www.seabios.org/pipermail/seabios/2015-January/008588.html > but found no solution there and it seems not to be my case as my board > does not hang. > > I put coreboot and SeaBIOS output in the attachment. Debug levels > set to > 7 for both. In coreboot only 'Output verbose CBFS debug messages' > checked in 'Debugging' submenu. > > Is there anything I'm doing wrong or simply missing? > > Viktor > -- > coreboot mailing list: coreboot(a)coreboot.org > <mailto:coreboot@coreboot.org> > http://www.coreboot.org/mailman/listinfo/coreboot >

5 years, 10 months

Kernel hang issue "All ACPI Tables successfully acquired"

by Ajoy Das

Hi I am running coreboot on qemu with the following sequence. coreboot -> seabios -> GRUB -> kernel. The kernel booting hangs at *All ACPI Tables successfully acquired* coreboot-4.0 kernel 3.19 when I pass acpi=off to the kernel command line parameter the kernel boots fine in this scenario. Is there any specific coreboot option is there to be enabled for successful booting. or anyone knows of this issue. please help Thanks

5 years, 10 months

device_t or struct device *|pci_devfn_t

by Alexander Couzens

Hi, there are some patches out in gerrit to use struct device * instead of device_t. I dislike the typedef of device_t but I see the reason - this was done to use the same code in preram stages as well in ramstage. In which way to we want to run? Should we replace device_t with struct device * and pci_devfn_t? Best lynxis Edward's commit replacing device_t with struct device * http://review.coreboot.org/#/c/7138/ http://review.coreboot.org/#/c/7139/ http://review.coreboot.org/#/c/7166/ http://review.coreboot.org/#/c/7169/ http://review.coreboot.org/#/c/7277/ My commit replacing device_t with pci_devfn_t http://review.coreboot.org/#/c/9250/ Add device_t to device ops acpi generators. http://review.coreboot.org/#/c/9598/ -- Alexander Couzens mail: lynxis(a)fe80.eu jabber: lynxis(a)jabber.ccc.de mobile: +4915123277221

5 years, 10 months

HP Pavilion dv7-6025eo support?

by public＠autistici.org

Can support be added for Hewlett-Packard's Pavilion dv7-6025eo laptop computer? Details: Advanced Micro Devices, Incorporated's Turion II P560 processor AMD RS880M microchip as a combination of northbridge and internal graphics processor ATI Mobility Radeon HD 4250 AMD SB820M microchip as the southbridge AMD Radeon HD 6650M as another graphics processor with 1024 MB of discrete memory ITE Technologies, Incorporated's IT8518E as the super I/O chip Winbond's 8-pin Small-Outline Integrated Circuit as the Basic Input/Output System chip soldered into the board "system board ID": 164E # lspci -tvnn -[0000:00]-+-00.0 Advanced Micro Devices, Inc. [AMD] RS880 Host Bridge [1022:9601] +-01.0-[01]--+-05.0 Advanced Micro Devices, Inc. [AMD/ATI] RS880M [Mobility Radeon HD 4225/4250] [1002:9712] | \-05.1 Advanced Micro Devices, Inc. [AMD/ATI] RS880 HDMI Audio [Radeon HD 4200 Series] [1002:970f] +-03.0-[02]----00.0 Advanced Micro Devices, Inc. [AMD/ATI] Whistler [Radeon HD 6630M/6650M/6750M/7670M/7690M] [1002:6741] +-04.0-[03]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168] +-05.0-[04]----00.0 Broadcom Corporation BCM4313 802.11bgn Wireless Network Adapter [14e4:4727] +-06.0-[05]----00.0 Realtek Semiconductor Co., Ltd. RTS5209 PCI Express Card Reader [10ec:5209] +-07.0-[06]----00.0 NEC Corporation uPD720200 USB 3.0 Host Controller [1033:0194] +-11.0 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] [1002:4391] +-12.0 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] +-12.2 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] +-13.0 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] +-13.2 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] +-14.0 Advanced Micro Devices, Inc. [AMD/ATI] SBx00 SMBus Controller [1002:4385] +-14.2 Advanced Micro Devices, Inc. [AMD/ATI] SBx00 Azalia (Intel HDA) [1002:4383] +-14.3 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 LPC host controller [1002:439d] +-14.4-[07]-- +-16.0 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] +-16.2 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] +-18.0 Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration [1022:1200] +-18.1 Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map [1022:1201] +-18.2 Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller [1022:1202] +-18.3 Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control [1022:1203] \-18.4 Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control [1022:1204] # superiotool -dV superiotool r6158 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0x0001, id=0x1885 Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0x0001, id=0x1885 Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0x8518, rev=0x2 Probing for ITE Super I/O (init=it8502e) at 0x4e... Failed. Returned data: id=0x8518, rev=0x2 Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0x8518, rev=0x2 Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0x8518, rev=0x2 Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0x8518, rev=0x2 Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: sid=0x85, srid=0x00 Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0x00, rev=0x00 Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0xff, id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Found SMSC SCH5317 (id=0x85, rev=0x18) at 0x4e No dump available for this Super I/O Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0x85/0x00, rev=0x18 Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O at 0x3f0... PCI device 1106:0686 not found. # flashrom -p internal -V flashrom v0.9.8-unknown on Linux 3.11.10-25-desktop (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.2.0, GCC 4.8.1 20130909 [gcc-4_8-branch revision 202388], little endian Command line (3 args): flashrom -p internal -V Calibrating delay loop... OS timer resolution is 1 usecs, 1118M loops per second, 10 myus = 9 us, 100 myus = 90 us, 1000 myus = 985 us, 10000 myus = 13930 us, 4 myus = 12 us, OK. Initializing internal programmer No coreboot table found. Using Internal DMI decoder. DMI string chassis-type: "Notebook" Laptop detected via DMI. DMI string system-manufacturer: "Hewlett-Packard" DMI string system-product-name: "HP Pavilion dv7 Notebook PC" DMI string system-version: "0593100000244720001020100" DMI string baseboard-manufacturer: "Hewlett-Packard" DMI string baseboard-product-name: "164E" DMI string baseboard-version: "06.1F" W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 85. Please send the output of "flashrom -V -p internal" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. Found ITE EC, ID 0x8518, Rev 0x02 on port 0x4e. ======================================================================== WARNING! You seem to be running flashrom on an unsupported laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See the manpage and http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Aborting. Error: Programmer initialization failed. Maintenance and Service Guide of the computer: http://www.hp.com/ctg/Manual/c02842278.pdf AMD RS880M Databook: http://support.amd.com/TechDocs/46113.pdf AMD RS880M Register Programming Requirements: http://support.amd.com/TechDocs/46141.pdf AMD RS880M Family: Register Reference Guide: http://support.amd.com/TechDocs/46142.pdf AMD RS880 ASIC Family BIOS: Developer’s Guide: http://support.amd.com/TechDocs/46143.pdf AMD SB820M Southbridge Databook: http://support.amd.com/TechDocs/47283.pdf SB800 Family Product Errata: http://support.amd.com/TechDocs/47481.pdf AMD SB800-Series Southbridges Reqister Programming Requirements http://support.amd.com/TechDocs/45481.pdf AMD SB800-Series Southbridges Register Reference Guide: http://support.amd.com/TechDocs/45482.pdf AMD SB800-Series Southbridges BIOS Developer's Guide: http://support.amd.com/TechDocs/45483.pdf

5 years, 10 months

Re: [coreboot] Question on VGA BIOS extraction

by Stefan Reinauer

* Iru Cai <mytbk920423(a)gmail.com> [150330 18:24]: > Hi, > > I'm trying to build Coreboot for ThinkPad X220. I first backup the vendor BIOS, > then use UEFITool to extract a VBIOS. The romheader program detects the ROM's > PCI data structure and reports the device id is 8086:0106, but the VGA > controller's device id is 8086:0126. I extracted the video ROM from a running > X220 memory and use romheader to test it, the result is still 8086:0106. How > could this happen? The same VGA OPROM binary is used for a whole set of different chipsets. However, the PCI header specification does not have a way to express that. The main system firmware has to know that, for a 0x0126 device it has to look for the 0x0106 OPROM. Hence coreboot has a mapping function for most newer (Intel) chipsets. Stefan

5 years, 10 months

Re: [coreboot] GRUB2 is too big as a payload in ThinkPad X201

by Paul Menzel

Dear Iru, welcome to coreboot! Am Donnerstag, den 26.03.2015, 09:33 +0800 schrieb Iru Cai: > I tried to use GRUB2 as a payload when building coreboot for ThinkPad X201, > but it's too big to fit into the rom. The GRUB2 coreboot image without > modules is 2.8M and >800K after compressing, it's still too big. building GRUB directly, I get a different result. $ git describe grub-2.02-beta2-372-g5974d4b $ ./autogen.sh $ ./configure --with-platform=coreboot --enable-boot-time --enable-cache-stats $ make $ edit Makefile Now adapt the rule `default_payload.elf`. default_payload.elf: grub-mkstandalone grub-mkimage pkgdatadir=. ./grub-mkstandalone --grub-mkimage=./grub-mkimage -O i386-coreboot -o $@ --modules='ahci pata ehci uhci ohci usb_keyboard usbms part_msdos xfs ext2 fat at_keyboard part_gpt usbserial_usbdebug cbfs' --install-modules='ls linux search configfile normal cbtime cbls memrw iorw minicmd lsmmap lspci halt reboot hexdump pcidump regexp setpci lsacpi chain test serial multiboot cbmemc linux16 gzio echo help' --fonts= --themes= --locales= -d grub-core/ /boot/grub/grub.cfg=$(srcdir)/coreboot.cfg Remove the modules you don’t need. With *my* ASRock E350M1 setup, I don’t need `pata`, `usbms`, `xfs`, `fat`, `at_keyboard`, `part_gpt` and `usbserial_usbdebug`. I then add `boottime` and `cacheinfo`. $ make default_payload.elf The file is now 578K big and in CBFS the compressed size is a little over 200 KB. $ build/cbfstool build/coreboot.rom print […] fallback/payload 0x5c400 payload 205851 […] […] Thanks, Paul PS: I’d be great if you could just send plain text messages with no HTML parts to mailing lists.

5 years, 10 months

Successful Coreboot install on F2A85-M

by Dominic Walden

Hi All, Just to say I've installed Coreboot on my Asus F2A85-M. Coreboot commit: 9484f5577e65192808f8752552f7f1de22e48a27 (5th April). Chipset: AMD Hudson Winbond flash chip: W25Q64 I used SeaBIOS as payload (which boots GRUB2 on disk). I chose not to use the original VGA Bios from the motherboard. All seems to be working, no problems experienced so far. Let me know if any more information would be of help. I've also attached my config if it will help, but it doesn't vary much from the default. Thanks and keep up the good work!

5 years, 10 months

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