February 2014 - coreboot - mail.coreboot.org

Re: [coreboot] Unable to start correctly coreboot on Asus f2a85-m REV 1.02
by HacKurx Feb. 14, 2014

Feb. 14, 2014

Peter wrote: > You might want to test my patch which exposes the IDS options in Kconfig: Ok thank you I'll test it soon (I'm in the middle of moving). Idwer wrote: > I'll add it to the board's wiki page. Perfect thank you. I am in contact with a responsable from AMD I hope get the Richland AGESA code. Time will tell...

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Re: [coreboot] Ram Init: Intel i945: Timing parameters
by Mohit Gupta Feb. 13, 2014

Feb. 13, 2014

Thanks Peter once again for helpful information. I was reading code line by line and going through i945 Express chipset document, tried to understand register settings and values. Seems to be tough job writing RAM init, and wouldn't have been possible without any documentation. Don't understand why Intel has made DRAM controller setup/Ram-init documentation NDA, and have made chipset documentation public ********************************************************************************************** Important Note This email (including any attachments) contains information which is confidential and may be subject to legal privilege. If you are not the intended recipient you must not use, distribute or copy this email. If you have received this email in error please notify the sender immediately and delete this email. Any views expressed in this email are not necessarily the views of IRESS Limited. It is the duty of the recipient to virus scan and otherwise test the information provided before loading onto any computer system. IRESS Limited does not warrant that the information is free of a virus or any other defect or error. **********************************************************************************************

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Ram Init: Intel i945: Timing parameters
by Mohit Gupta Feb. 13, 2014

Feb. 13, 2014

I am having trouble understanding i945 ram init code especially timing parameters. Can some explain me in layman language? When I go through DDR2 specification, timing related text is too complex and confusing. Interested in getting very simple explanation. Also, i945 ram init code is doing lot of settings in MCH. Is there any step by step documentation available? Regards Mohit Gupta

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Re: [coreboot] Ram Init: Intel i945: Timing parameters
by Mohit Gupta Feb. 13, 2014

Feb. 13, 2014

Thanks Vald ... not possible to break intel safe :).. wondering how coreboot team was able to write i945 ram init? ********************************************************************************************** Important Note This email (including any attachments) contains information which is confidential and may be subject to legal privilege. If you are not the intended recipient you must not use, distribute or copy this email. If you have received this email in error please notify the sender immediately and delete this email. Any views expressed in this email are not necessarily the views of IRESS Limited. It is the duty of the recipient to virus scan and otherwise test the information provided before loading onto any computer system. IRESS Limited does not warrant that the information is free of a virus or any other defect or error. **********************************************************************************************

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Re: [coreboot] Ram-init: Intel i945: sdram_detect_cas_latency_and_ram_speed
by Mohit Gupta Feb. 13, 2014

Feb. 13, 2014

Thanks Peter for your support. I will have a look at provided links. ********************************************************************************************** Important Note This email (including any attachments) contains information which is confidential and may be subject to legal privilege. If you are not the intended recipient you must not use, distribute or copy this email. If you have received this email in error please notify the sender immediately and delete this email. Any views expressed in this email are not necessarily the views of IRESS Limited. It is the duty of the recipient to virus scan and otherwise test the information provided before loading onto any computer system. IRESS Limited does not warrant that the information is free of a virus or any other defect or error. **********************************************************************************************

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coreboot port for macbook2,1
by Mono Feb. 13, 2014

Feb. 13, 2014

Hallo, Would you help me on a coreboot port? I just installed coreboot on a Thinkpad X60 following the wiki. Now I want it on this mid-2007 macbook2,1 too. I read some pages in the wiki and started to collect information about the macbook. it seems it has no superIO chip and I dont know what to think of the ectool output. As I understood by now, not knowing how the ec might interfere with the bios or coreboot is one of the big obstacles, no? I hope that once I would try a coreboot flash, recovery might be possible by an external programmer (which I do not have, yet). the flash chip is the same as on the X60 (I've read the factory bios already) as is the northbridge and southbridge. an usb debug port seems available. I've put the log files here: http://macbook.donderklumpen.de/coreboot/ Any comment about what you think about this and how I should proceed is very much welcome! thanks Mono

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Re: [coreboot] Ram-init: Intel
by Mohit Gupta Feb. 13, 2014

Feb. 13, 2014

Thanks Peter for your support. I will have a look at provided links. Regards Mohit Gupta

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How do I reply to a post?
by Mohit Gupta Feb. 13, 2014

Feb. 13, 2014

Regards Mohit Gupta

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Alias motherboard?
by Oskar Enoksson Feb. 13, 2014

Feb. 13, 2014

I noticed that "AMD Serenade" motherboard is not listed as supported. However, supposedly that motherboard is identical to HP DL145 G1. So, probably using the hp/dl145_g1 motherboard configuration will produce a ROM that works with "AMD Serenade" aswell. Are such alias motherboards handled in any particular way? Should the info at least go into the wiki-page of supported motherboards?

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Ram-init: Intel i945: sdram_detect_cas_latency_and_ram_speed
by Mohit Gupta Feb. 13, 2014

Feb. 13, 2014

I am trying to understand ram initialization process for intel i945 chipset. Would some be able to guide me as what sdram_detect_cas_latency_and_ram_speed is trying to do. I am a newbie, hence, entitled to ask stupid question :) Regards Mohit Gupta

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