coreboot February 2014

coreboot@coreboot.org

52 participants
148 discussions

Acer C710-2856 coreboot+seabios blue screen?
by Justin Roylance 20 Feb '14

20 Feb '14

I recently flashed a coreboot+seabios firmware from johnlewis.ie into my Acer C7 Chromebook. I consider myself pretty adept at this sort of thing and was comfortable doing so, I made sure to choose the correct build for my system and closely followed all the instructions. When I turn on the C7 all I get is a light blue screen. I installed Kubuntu onto a drive and replaced the 16gb SSD with it, I know it was successful to some extent because it boots and I can SSH into it remotely, but the laptop itself always just has a blank blue screen. I backed up my original firmware before I flashed the new one in, but the flashrom utility in Kubuntu says no chipset found and no EEPROM/flash device found. If anyone could point me in the right direction here I would greatly appreciate it.

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SeaVGABIOS with native vga init (Need testers)
by Kevin O'Connor 19 Feb '14

19 Feb '14

I have recently put together a basic implementation of a vgabios for use with displays that are initialized by coreboot. The idea is pretty simple - coreboot initializes the vga hardware and maps a framebuffer into an address in system memory. Then SeaVGABIOS implements the various legacy vga bios functions, but all it does with them is translate them to framebuffer updates. SeaVGABIOS doesn't try to initialize the display, change modes, or modify the vga registers. This might be useful for those wishing to run fewer third-party blobs, for those where a vgabios isn't available at all, and for those wanting a faster boot (I've found proprietary vga bioses to be very slow). I've run some basic tests on this version of SeaVGABIOS on my hardware. However, I don't have one of the boards where coreboot supports native vga init. It would be great if someone with the hardware (looks like stout, x60, and maybe others) could run tests. To build this version of SeaVGABIOS, checkout the testing code from: https://github.com/KevinOConnor/seabios/tree/testing Then run "make menuconfig", turn on building for coreboot (CONFIG_COREBOOT), serial debugging (CONFIG_DEBUG_SERIAL), and enable the coreboot vgabios build (CONFIG_VGA_COREBOOT). The resulting vgabios will be in "out/vgabios.bin" - this file should be placed in CBFS in the file "vgaroms/vgabios.bin". Then launch coreboot with seabios as the payload (one can use the repo above to build seabios also, or use the normal coreboot method of building seabios). Ideally, the seabios menu should appear on the screen and basic OS boot loaders will work. But if not, the debugging info should help track down any problems. -Kevin

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Re: [coreboot] Ram Init: Intel i945: Timing parameters
by Peter Stuge 19 Feb '14

19 Feb '14

Mohit Gupta wrote: > Don't understand why Intel has made DRAM controller setup/Ram-init > documentation NDA, Many people wonder about the same thing. It's not clear. > and have made chipset documentation public The chipset docs aren't really published. Only some parts of them. > ********************************************************************************************** > Important Note > This email (including any attachments) contains information which is > confidential Why are you sending confidential information in plain text to a public mailing list which is archived all on the web? That seems silly. Please make sure not to include any such nonsense disclaimers in your emails at the very least when you participate in open source projects. //Peter

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Re: [coreboot] Coding for free
by Peter Stuge 19 Feb '14

19 Feb '14

Nitin Issac Joy wrote: > I am Nitin Issac Joy, 2nd Year Computer Science Engineering Student from > India, wanting to contribute to coreboot. I want more hand-on experience > with ASM and interfacing which is the reason why I am doing this. > > I know more than basic ASM, well versed in C. That's a good starting point, but you'll quickly have to learn many x86 details. > Can anyone of you guide me? I think you'll find that everyone in the coreboot community is quite busy, and that you will have to learn most things on your own. Start out with building coreboot and running it in QEMU. That doesn't require buying any hardware and can already let you work on many different aspects of booting. If you want to continue with the project you will eventually need to work with hardware, which requires a suitable development environment with some tools and a target system which is not your primary machine. //Peter

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Re: [coreboot] Coding for free
by ron minnich 18 Feb '14

18 Feb '14

how much money do you have to buy hardware that coreboot supports? That's always a first step. ron

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A Growing Concern
by amloerx＠tfwno.gf 18 Feb '14

18 Feb '14

As a privacy and freedom oriented PC/Linux user, it scares me how modern day devices are becoming extremely proprietary. Companies are beginning to ship their laptops/tablets with proprietary EFI systems which have some nasty things in them. I recently purchased a Dell Venue 8 Pro(one of many upcoming 8" windows 8.1(x86) tablets) and while i was searching through its BIOS, i noticed that it had the computrace option activated. After disabling it, i decided to try to put coreboot on it, only to find that its non-existent for my device. Although it says that its disabled, i dont trust it one bit. While it is a beautiful, fast and ultra-portable PC, it bothers me how there are no free alternatives for it. These types of devices are growing in numbers and will most likely continue on through the years. All I ask of you is to try and make EFI alternatives to all these upcoming devices.

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Untangling the UART
by Kyösti Mälkki 18 Feb '14

18 Feb '14

Hey! I have posted first half for series of patches that should untangle the mess of multiple different prototypes for the simple thing of getting some console output out of UART. There is little practical use of being able to compile coreboot with multiple type of UARTs in same build, so we can use same function prototypes for all different type of UARTs once we sort out the issue with passing the base address argument. Solving this part is available for review now on gerrit. Easiest way to access these in gerrit is to find CL 'SMM: Only have console with DEBUG_SMI', and check its dependencies. http://review.coreboot.org/#/c/5142 Thanks, Kyösti

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Re: [coreboot] how to model the Quark architecture
by Peter Stuge 18 Feb '14

18 Feb '14

ron minnich wrote: > I can't understand the point here. > docs or code would help. Aaron Durbin wrote: > Could you please provide explicit examples having c struct fields > represented in devicetree that model another address space? No I can not. I do not have the capacity to deliver the ready-made architecture to you guys. I'm sorry I said anything, I was silly to think that design discussion would be possible. //Peter

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Re: [coreboot] how to model the Quark architecture
by Peter Stuge 18 Feb '14

18 Feb '14

Aaron Durbin wrote: > > I think the most obvious thing is the message port architecture? > > > > Sure, we can skip modeling them and create some global functions for > > sending messages to random ports, but that wouldn't be very impressive.. > > What do you mean by modeling them? Compare with how HT (doesn't) works, or with PCI. > What is an impressive implementation for sending messages to ports? > It's just another address space through index/data pairs. That's exactly what I disagree with. There is an architecture and I would expect coreboot to model it rather than dumping an array of magic number pairs into index/data. The coreboot devicetree doesn't model HT so well - it is treated as "another address space". I think it would be better to avoid repeating such a mistake? //Peter

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Re: [coreboot] how to model the Quark architecture
by Peter Stuge 18 Feb '14

18 Feb '14

Aaron Durbin wrote: > I skimmed through the doc yesterday evening. It looks very much like > BayTrail. What particular differences did you see where it would be > different to cause issues for coreboot? I think the most obvious thing is the message port architecture? Sure, we can skip modeling them and create some global functions for sending messages to random ports, but that wouldn't be very impressive.. //Peter

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coreboot February 2014