coreboot February 2014

coreboot@coreboot.org

52 participants
148 discussions

[RFT] Lenovo convertible tablets X60t, X201t, X230t
by Vladimir 'φ-coder/phcoder' Serbinenko 04 Feb '14

04 Feb '14

Hello, all. I've uploaded digitizer support for X*t variants. Not tested in current form yet (was developped on Jens Erat's X201T during FOSDEM). Please test: - X60t owners: http://review.coreboot.org/#/c/5113/ - X201t owners: http://review.coreboot.org/#/c/5096 - X230t owners: should work without additional support (USB). Please report test result be it either positive or negative.

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Re: [coreboot] Unable to start correctly coreboot on Asus f2a85-m REV 1.02
by Rudolf Marek 04 Feb '14

04 Feb '14

On 31.1.2014 13:53, HacKurx wrote: >> No way. You will need to use serial port. Just plug the header to mainboard and use some USB 2 serial from other computer (together with null >> modem cable) if you need more info please let me know. > Do you have any links, diagram or picture for this method? Thanks Yes sure. You will need at least those things: 1) serial header connector http://www.ebay.com/itm/DB9-Male-RS232-COM-Port-Serial-Header-Cable-for-Asu… You can take any from some old motherboard. Usually there where two variants of pinout. The newer one fits the most mainboards. You need to plug it to a header on the f2a85-m board. (pin1 to the color stripe on the cable) I think it is called "COM header" in the manual. 2) null modem cross cable The header from 1) needs to be plugged to 2) This cable is very common. It is also called "crossed" cable with female/female 9 pin connector. http://www.ebay.com/itm/Serial-RS232-Null-Modem-Cable-Female-to-Female-DB9-… (female / female) 3) USB to serial cable Either find some other computer which has a serial header (and you will need second header from 1)) or buy this convertor. Most of them use pl2303 or ftdi chip which is well supported under linux. http://www.ebay.com/itm/USB-to-RS232-Serial-Port-9-Pin-DB9-Cable-Serial-COM… 4) other computer (any laptop/desktop) Plug in the USB serial with all cables plugged, and use /dev/ttyUSB0 use "minicom" or "hyperterminal" if you use windows. Set it 115200 8N1 (8 byte 1 stop bit no parity) You should see some output of coreboot. Capture it via (ctrl a l shortcut in minicom) to a file and send it back to list. If is something unclear, please let us know. You need to make it up to next Friday. I will be then long time AFK and I will back in March. Thanks Rudolf

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Question about status of coreboot on the Samsung XE303CE ARM Chromebook (snow)
by James MacMahon 04 Feb '14

04 Feb '14

Hi everyone, Quick question: what is the status of coreboot + some payload being used with the Samsung XE303CE ARM Chromebook (snow)? The page at [http://www.coreboot.org/Chromebooks] says 'Snow has das U-Boot nativly installed, but a coreboot port is available.', and the page at [http://www.coreboot.org/Supported_Motherboards] has 'Google Snow - Samsung Exynos 5250' under the 'Motherboards supported in coreboot', but I haven't been able to find any blog / example of anyone actually flashing coreboot + some payload and booting their Chromebook like a regular computer. It seems like there is a port available but no one has tried it from start to finish on the ARM Chromebook (where my definition of finish in this context is 'booting with coreboot to stock Debian Linux', for example). I'm very keen on doing this myself, and was hoping to find some example that I could read through or even follow. This whole process of flashing a new BIOS is very new to me, and I'm wary because of the potential to easily brick my device (however I'm not scared off by reflashing or external chip programming if it comes to it, I'd just like to avoid it). Thanks for your time, James

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Re: [coreboot] Motherboard Not on Support MB List -> Specs
by Vladimir 'φ-coder/phcoder' Serbinenko 03 Feb '14

03 Feb '14

On 03.02.2014 17:37, lee.changhan wrote: > Hi, I have some info about my motherboard here according to the FAQ page > to see if anyone can tell me about the compatibility between my BIOS and > coreboot. > Your motherboard is not compatible with coreboot. > 1. Gigabyte GA-Z77-HD3 Motherboard > Intel(R) Core(TM) i5-3570K CPU @ 3.40GHz > > 2. lspci -tvnn > > -[0000:00]-+-00.0 Intel Corporation Xeon E3-1200 v2/3rd Gen Core > processor DRAM Controller [8086:0150] > +-01.0-[01]--+-00.0 Advanced Micro Devices, Inc. [AMD/ATI] > Caicos [Radeon HD 6450/7450/8450] [1002:6779] > | \-00.1 Advanced Micro Devices, Inc. [AMD/ATI] > Caicos HDMI Audio [Radeon HD 6400 Series] [1002:aa98] > +-14.0 Intel Corporation 7 Series/C210 Series Chipset Family > USB xHCI Host Controller [8086:1e31] > +-16.0 Intel Corporation 7 Series/C210 Series Chipset Family > MEI Controller #1 [8086:1e3a] > +-1a.0 Intel Corporation 7 Series/C210 Series Chipset Family > USB Enhanced Host Controller #2 [8086:1e2d] > +-1b.0 Intel Corporation 7 Series/C210 Series Chipset Family > High Definition Audio Controller [8086:1e20] > +-1c.0-[02]-- > +-1c.2-[03]----00.0 Realtek Semiconductor Co., Ltd. > RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168] > +-1c.3-[04-05]----00.0-[05]-- > +-1d.0 Intel Corporation 7 Series/C210 Series Chipset Family > USB Enhanced Host Controller #1 [8086:1e26] > +-1f.0 Intel Corporation Z77 Express Chipset LPC Controller > [8086:1e44] > +-1f.2 Intel Corporation 7 Series/C210 Series Chipset Family > 4-port SATA Controller [IDE mode] [8086:1e00] > +-1f.3 Intel Corporation 7 Series/C210 Series Chipset Family > SMBus Controller [8086:1e22] > \-1f.5 Intel Corporation 7 Series/C210 Series Chipset Family > 2-port SATA Controller [IDE mode] [8086:1e08] > > 3. superiotool -dV > superiotool r6637 > Probing for ALi Super I/O at 0x3f0... > Failed. Returned data: id=0xffff, rev=0xff > Probing for ALi Super I/O at 0x370... > Failed. Returned data: id=0xffff, rev=0xff > Probing for Fintek Super I/O at 0x2e... > Failed. Returned data: vid=0xffff, id=0xffff > Probing for Fintek Super I/O at 0x4e... > Failed. Returned data: vid=0xffff, id=0xffff > Probing for Fintek Super I/O at 0x2e... > Failed. Returned data: vid=0xffff, id=0xffff > Probing for Fintek Super I/O at 0x4e... > Failed. Returned data: vid=0xffff, id=0xffff > Probing for ITE Super I/O (init=standard) at 0x25e... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=it8502e) at 0x25e... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=it8761e) at 0x25e... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=it8228e) at 0x25e... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=standard) at 0x2e... > Failed. Returned data: id=0x8728, rev=0x1 > Probing for ITE Super I/O (init=it8502e) at 0x2e... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=it8761e) at 0x2e... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=it8228e) at 0x2e... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=standard) at 0x4e... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=it8502e) at 0x4e... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=it8761e) at 0x4e... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=it8228e) at 0x4e... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... > Failed. Returned data: id=0xffff, rev=0xf > Probing for NSC Super I/O at 0x2e... > Failed. Returned data: port=0xff, port+1=0xff > Probing for NSC Super I/O at 0x4e... > Failed. Returned data: port=0xff, port+1=0xff > Probing for NSC Super I/O at 0x15c... > Failed. Returned data: port=0xff, port+1=0xff > Probing for NSC Super I/O at 0x164e... > Failed. Returned data: port=0xff, port+1=0xff > Probing for Nuvoton Super I/O at 0x164e... > Failed. Returned data: chip_id=0xffff > Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... > Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 > Probing for Nuvoton Super I/O at 0x2e... > Failed. Returned data: chip_id=0xffff > Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... > Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 > Probing for Nuvoton Super I/O at 0x4e... > Failed. Returned data: chip_id=0xffff > Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e... > Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 > Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... > Failed. Returned data: id=0xff, rev=0xff > Probing for Winbond Super I/O (init=0x88) at 0x2e... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x89) at 0x2e... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x88) at 0x4e... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x89) at 0x4e... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x88) at 0x3f0... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x89) at 0x3f0... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x88) at 0x370... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x89) at 0x370... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x88) at 0x250... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x89) at 0x250... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for VIA Super I/O at 0x3f0... > PCI device 1106:0686 not found. > Probing for Server Engines Super I/O at 0x2e... > Failed. Returned data: id=0xffff, rev=0xff > No Super I/O found > > 4. flashrom -V > > flashrom v0.9.6.1-r1563 on Linux 3.11.0-15-generic (x86_64) > flashrom is free software, get the source code at http://www.flashrom.org > > flashrom was built with libpci 3.1.9, GCC 4.7.1, little endian > Command line (1 args): flashrom -V > Please select a programmer with the --programmer parameter. > Valid choices are: > internal, dummy, nic3com, nicrealtek, gfxnvidia, drkaiser, satasii, > ft2232_spi, > serprog, buspirate_spi, rayer_spi, pony_spi, nicintel, nicintel_spi, > ogp_spi, > satamv > >

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coreboot port for the ASRock FM2A88M-HD+
by Felix Held 03 Feb '14

03 Feb '14

Hi! I am trying to port the ASRock FM2A88M-HD+ board. Should be a good board for my first coreboot port, since the reference code for the chipset and the datasheet for the superio chip are available. And it's quite inexpensive. I gathered some information and created a wiki page for it: http://www.coreboot.org/Board:asrock/fm2a88m-hd%2B Regards Felix

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Motherboard Not on Support MB List -> Specs
by lee.changhan 03 Feb '14

03 Feb '14

Hi, I have some info about my motherboard here according to the FAQ page to see if anyone can tell me about the compatibility between my BIOS and coreboot. 1. Gigabyte GA-Z77-HD3 Motherboard Intel(R) Core(TM) i5-3570K CPU @ 3.40GHz 2. lspci -tvnn -[0000:00]-+-00.0 Intel Corporation Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller [8086:0150] +-01.0-[01]--+-00.0 Advanced Micro Devices, Inc. [AMD/ATI] Caicos [Radeon HD 6450/7450/8450] [1002:6779] | \-00.1 Advanced Micro Devices, Inc. [AMD/ATI] Caicos HDMI Audio [Radeon HD 6400 Series] [1002:aa98] +-14.0 Intel Corporation 7 Series/C210 Series Chipset Family USB xHCI Host Controller [8086:1e31] +-16.0 Intel Corporation 7 Series/C210 Series Chipset Family MEI Controller #1 [8086:1e3a] +-1a.0 Intel Corporation 7 Series/C210 Series Chipset Family USB Enhanced Host Controller #2 [8086:1e2d] +-1b.0 Intel Corporation 7 Series/C210 Series Chipset Family High Definition Audio Controller [8086:1e20] +-1c.0-[02]-- +-1c.2-[03]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168] +-1c.3-[04-05]----00.0-[05]-- +-1d.0 Intel Corporation 7 Series/C210 Series Chipset Family USB Enhanced Host Controller #1 [8086:1e26] +-1f.0 Intel Corporation Z77 Express Chipset LPC Controller [8086:1e44] +-1f.2 Intel Corporation 7 Series/C210 Series Chipset Family 4-port SATA Controller [IDE mode] [8086:1e00] +-1f.3 Intel Corporation 7 Series/C210 Series Chipset Family SMBus Controller [8086:1e22] \-1f.5 Intel Corporation 7 Series/C210 Series Chipset Family 2-port SATA Controller [IDE mode] [8086:1e08] 3. superiotool -dV superiotool r6637 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0x8728, rev=0x1 Probing for ITE Super I/O (init=it8502e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x164e... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O at 0x164e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x2e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x4e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O at 0x3f0... PCI device 1106:0686 not found. Probing for Server Engines Super I/O at 0x2e... Failed. Returned data: id=0xffff, rev=0xff No Super I/O found 4. flashrom -V flashrom v0.9.6.1-r1563 on Linux 3.11.0-15-generic (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.9, GCC 4.7.1, little endian Command line (1 args): flashrom -V Please select a programmer with the --programmer parameter. Valid choices are: internal, dummy, nic3com, nicrealtek, gfxnvidia, drkaiser, satasii, ft2232_spi, serprog, buspirate_spi, rayer_spi, pony_spi, nicintel, nicintel_spi, ogp_spi, satamv

1 0

Please use Git commit hooks
by Paul Menzel 02 Feb '14

02 Feb '14

Dear coreboot folks, if you push patches please either check them manually or simply let the Git commit hooks do it for you by running `make gitconfig`. I know they take a lot of time especially when you run them the first time in a session. This will be hopefully improved soon. Thanks, Paul

3 2

fixed AMD SPI speed settings (leading to problems on E350M1/USB3)
by Stefan Tauner 02 Feb '14

02 Feb '14

Hi, andor reported a problem where flashrom does reproducibly not work with coreboot but does with the vendor BIOS http://paste.flashrom.org/view.php?id=1614 Apparently it is related to fast reads and/or the frequency. We have forced the fastReadEnable bit in the SPI_Cntrl0 from 1 to 0 and also set NormSpeed in SPI_Cntrl1 to 16.5 Mhz (previously was 0 i.e. 66 MHz) in flashrom and the problem vanished. Coreboot hard codes the fast read setting in src/southbridge/amd/cimx/sb800/bootblock.c: static void enable_spi_fast_mode(void) { u8 byte; u32 dword; device_t dev = PCI_DEV(0, 0x14, 0x03); // set temp MMIO base volatile u32 *spi_base = (void *)0xa0000000; u32 save = pci_io_read_config32(dev, 0xa0); pci_io_write_config32(dev, 0xa0, (u32) spi_base | 2); // early enable of SPI 33 MHz fast mode read byte = spi_base[3]; spi_base[3] = (byte & ~(3 << 14)) | (1 << 14); spi_base[0] = spi_base[0] | (1 << 18); // fast read enable pci_io_write_config32(dev, 0xa0, save); } Marc suggested that this should be configurable in the devicetree or by a kconfig setting. Also, the statements using "byte" do not make a lot of sense to me. Shouldn't that be a u32 instead? The public documentation of the fastReadEnable is lacking any detail and I don't have access to the NDAed version of the RRG. Is my theory correct that the controller uses the 0x0B opcode with a fixed frequency (33 MHz?) instead of 0x03 with the frequency set by NormSpeed? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

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coreboot February 2014