February 2014 - coreboot - mail.coreboot.org

Re: [coreboot] how to model the Quark architecture
by Peter Stuge Feb. 18, 2014

Feb. 18, 2014

ron minnich wrote: > I"m not sure why I would want to start a coreboot port effort with this > UEFI doc as my guide Look past all the UEFI babble. :) The doc is a good description of what needs to be done to bring the platform up, and it's fairly different from what coreboot does so far. //Peter

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Re: [coreboot] how to model the Quark architecture
by Peter Stuge Feb. 18, 2014

Feb. 18, 2014

ron minnich wrote: > would be nice to have some specifics ... "UEFI Firmware Writer's Guide" is a good place to start. http://downloadcenter.intel.com/confirm.aspx?httpDown=http://downloadmirror… > do you want to start a design doc? Maybe the list is OK to begin with? //Peter

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Re: [coreboot] blob matrix filling in
by Peter Stuge Feb. 17, 2014

Feb. 17, 2014

ron minnich wrote: > I suppose I'll make a key for all of coreboot users for quark, > and we'll see how that goes. For anybody who might be working on Quark support: Please note that the Quark architecture does *NOT AT ALL* fit easily into the existing coreboot hardware model, and before all too much time is spent on development I expect discussion on how we'll model Quark in coreboot. I would be quite disappointed if there are suddenly random hacks in gerrit without there having been an actual design effort to allow coreboot to actually model Quark - since all neccessary documentation is readily available. //Peter

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Re: [coreboot] has intel been hacked?
by Gregg Levine Feb. 17, 2014

Feb. 17, 2014

Hello! Wasn't me. Chrome on seven worked perfectly. I am convinced that something might have happened. But given that it wasn't announced, we do not need to worry. ----- Gregg C Levine gregg.drwho8(a)gmail.com "This signature fought the Time Wars, time and again." On Mon, Feb 17, 2014 at 1:29 PM, ron minnich <rminnich(a)gmail.com> wrote: > Yep, I filed a bug with the chrome guys. > > interesting. Somebody at intel told me that chrome on win7 works, the > horror! > > ron > > > On Mon, Feb 17, 2014 at 10:03 AM, mrnuke <mr.nuke.me(a)gmail.com> wrote: >> >> On Monday, February 17, 2014 08:24:12 AM ron minnich wrote: >> > downloadcenter.intel.com >> > >> > gets the following error, and has for some time: >> > >> > Cannot connect to the real downloadcenter.intel.com >> > >> > Something is currently interfering with your secure connection to >> > downloadcenter.intel.com. >> > >> > *Try to reload this page in a few minutes or after switching to a new >> > network.* If you have recently connected to a new Wi-Fi network, finish >> > logging in before reloading. >> > >> > If you were to visit downloadcenter.intel.com right now, you might share >> > private information with an attacker. To protect your privacy, Chrome >> > will >> > not load the page until it can establish a secure connection to the real >> > downloadcenter.intel.com. >> > >> > >> > >> > so, I wonder what it all means? >> >> That's just Chromium/Chrome bleeping up. Any other browser connects just >> fine. >> The SSL cert is valid. >> >> Alec >> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] has intel been hacked?
by mrnuke Feb. 17, 2014

Feb. 17, 2014

On Monday, February 17, 2014 08:24:12 AM ron minnich wrote: > downloadcenter.intel.com > > gets the following error, and has for some time: > > Cannot connect to the real downloadcenter.intel.com > > Something is currently interfering with your secure connection to > downloadcenter.intel.com. > > *Try to reload this page in a few minutes or after switching to a new > network.* If you have recently connected to a new Wi-Fi network, finish > logging in before reloading. > > If you were to visit downloadcenter.intel.com right now, you might share > private information with an attacker. To protect your privacy, Chrome will > not load the page until it can establish a secure connection to the real > downloadcenter.intel.com. > > > > so, I wonder what it all means? That's just Chromium/Chrome bleeping up. Any other browser connects just fine. The SSL cert is valid. Alec

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has intel been hacked?
by ron minnich Feb. 17, 2014

Feb. 17, 2014

downloadcenter.intel.com gets the following error, and has for some time: Cannot connect to the real downloadcenter.intel.com Something is currently interfering with your secure connection to downloadcenter.intel.com. *Try to reload this page in a few minutes or after switching to a new network.* If you have recently connected to a new Wi-Fi network, finish logging in before reloading. If you were to visit downloadcenter.intel.com right now, you might share private information with an attacker. To protect your privacy, Chrome will not load the page until it can establish a secure connection to the real downloadcenter.intel.com. so, I wonder what it all means?

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blob matrix filling in
by ron minnich Feb. 17, 2014

Feb. 17, 2014

I'm slowly filling in the blob matrix; see http://www.coreboot.org/Blob_Matrix. If somebody wants to hunt down the signing utility let me know. I suppose I'll make a key for all of coreboot users for quark, and we'll see how that goes. ron

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Wyse S10 Geode GX2
by andrew＠cogman.info Feb. 17, 2014

Feb. 17, 2014

Hi, I'm fairly new at this and I'm trying to get coreboot and SeaBIOS working on a Wyse S10 and I've hit a problem and wondered if anyone can help. I've compiled the reference toolchain and used that with the latest Git version and the one mentioned in Fijam's blog (http://fijam.eu.org/blog/how-to-put-coreboot-on-wyse-s30s50/) but they both stop at the same place. I've obtained a copy of the GX2 VSA (through methods I probably can't mention here), but it's a different size to the one Fijam used? Is this a fault with the VSA or have I made a rookie mistake somewhere? .config and bootlog attached. Thanks, Andrew

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Re: [coreboot] Wyse S10 Geode GX2
by andrew＠cogman.info Feb. 17, 2014

Feb. 17, 2014

> andrew(a)cogman.info wrote: >> it's a different size to the one Fijam used? > Check if it is gzip-compressed. Thank you for the quick reply. It doesn't appear to be a gzip file - file reports it as a "COM executable for DOS" >> .config and bootlog attached. > Sorry, no attachments. Make sure that they are text/plain. Sorry, my mistake I'll copy them directly here. boot_log: coreboot-4.0-5512-g6e56de3 Sun Feb 16 17:30:48 GMT 2014 starting... done cpuRegInit Ram1.00 Ram2.00 sdram_set_spd_register Check DIMM 0 Check DIMM 1 Check DDR MAX AUTOSIZE DIMM 0 Check present MODBANKS FIELDBANKS SPDNUMROWS SPDBANKDENSITY DIMMSIZE BEFORT CTZ TEST DIMM SIZE>7 PAGESIZE MAXCOLADDR >11address test RDMSR CF07 WRMSR CF07 ALL DONE AUTOSIZE DIMM 1 Check present set cas latency set all latency MSR MC_CF8F_DATA (20000019) value is 18000108:696332a3 set emrs set ref rate Ram3 sdram_enable step 2 sdram_enable step 3 sdram_enable step 4 sdram_enable step 6 sdram_enable step 7 sdram_enable step 8 RAM DLL lock Ram4 ram setup done Trying CBFS ramstage loader. CBFS: loading stage fallback/coreboot_ram @ 0x100000 (139264 bytes), entry @ 0x100000 coreboot-4.0-5512-g6e56de3 Sun Feb 16 17:30:48 GMT 2014 booting... clocks_per_usec: 366 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:0e.0: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:0f.2: enabled 1 PCI: 00:0f.3: enabled 1 PCI: 00:0f.4: enabled 1 PCI: 00:0f.5: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 Compare with tree... Root Device: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:0e.0: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:0f.2: enabled 1 PCI: 00:0f.3: enabled 1 PCI: 00:0f.4: enabled 1 PCI: 00:0f.5: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 scan_static_bus for Root Device >> Entering northbridge.c: enable_dev with path 6 >> Entering northbridge.c: pci_domain_enable Enter northbridge_init_early writeglmsr: MSR 0x10000020, val 0x20000000:0x000fff80 writeglmsr: MSR 0x10000021, val 0x20000000:0x080fffe0 sizeram: _MSR MC_CF07_DATA: 10077014:00003500 sizeram: sizem 0x200 SysmemInit: enable for 512MBytes SysmemInit: MSR 0x10000028, val 0x2000001f:0xfdf00100 sizeram: _MSR MC_CF07_DATA: 10077014:00003500 sizeram: sizem 0x200 SMMGL0Init: 536739840 bytes SMMGL0Init: offset is 0x40400000 SMMGL0Init: MSR 0x10000026, val 0x2dfbe040:0x400fffe0 writeglmsr: MSR 0x10000080, val 0x00000000:0x00000003 writeglmsr: MSR 0x40000020, val 0x20000000:0x000fff80 writeglmsr: MSR 0x40000021, val 0x20000000:0x080fffe0 sizeram: _MSR MC_CF07_DATA: 10077014:00003500 sizeram: sizem 0x200 SysmemInit: enable for 512MBytes SysmemInit: MSR 0x40000029, val 0x2000001f:0xfdf00100 SMMGL1Init: SMMGL1Init: MSR 0x40000023, val 0x20000040:0x400fffe0 writeglmsr: MSR 0x40000080, val 0x00000000:0x00000001 writeglmsr: MSR 0x400000e3, val 0x60000000:0x033000f0 CPU_RCONF_DEFAULT (1808): 0x25FFFC02:0x11FFDF00 CPU_RCONF_BYPASS (180A): 0x00000000 : 0x00000000 Enabling cache GLPCI R1: system msr.lo 0x00100130 msr.hi 0x1ffdf000 GLPCI R2: system msr.lo 0x40400120 msr.hi 0x4041f000 Exit northbridge_init_early Doing cpubug fixes for rev 0x21 CPU_BUG:eng2900 Done cpubug fixes Not Doing ChipsetFlashSetup() ---------- CPU ------------ MSR 0x00001700 is now 0x00000000:0x00100000 MSR 0x00001800 is now 0x00002000:0x00000022 MSR 0x00001808 is now 0x25FFFC02:0x11FFDF00 MSR 0x0000180A is now 0x00000000:0x00000000 MSR 0x0000180B is now 0x21212121:0x21212121 MSR 0x0000180C is now 0x21212121:0x21212121 MSR 0x0000180D is now 0x21212121:0x21212121 MSR 0x0000180E is now 0x00000001:0x00000001 MSR 0x0000180F is now 0x00000001:0x00000001 MSR 0x4C00000F is now 0x830D415A:0x8EA0AD6A ---------- GLIU 0 ------------ MSR 0x10000020 is now 0x20000000:0x000FFF80 MSR 0x10000021 is now 0x20000000:0x080FFFE0 MSR 0x10000022 is now 0x000000FF:0xFFF00000 MSR 0x10000023 is now 0x000000FF:0xFFF00000 MSR 0x10000024 is now 0x000000FF:0xFFF00000 MSR 0x10000025 is now 0x000000FF:0xFFF00000 MSR 0x10000026 is now 0x2DFBE040:0x400FFFE0 MSR 0x10000027 is now 0x000000FF:0xFFF00000 MSR 0x10000028 is now 0x2000001F:0xFDF00100 MSR 0x10000029 is now 0x00000000:0x000FFFFF MSR 0x1000002A is now 0x00000000:0x000FFFFF MSR 0x1000002B is now 0x00000000:0x000FFFFF MSR 0x1000002C is now 0x2000FFFF:0xFFFF0003 MSR 0x100000E0 is now 0x000000FF:0xFFF00000 MSR 0x100000E1 is now 0x000000FF:0xFFF00000 MSR 0x100000E2 is now 0x000000FF:0xFFF00000 MSR 0x100000E3 is now 0x00000000:0x00000000 MSR 0x100000E4 is now 0x00000000:0x00000000 MSR 0x100000E5 is now 0x00000000:0x00000000 MSR 0x100000E6 is now 0x00000000:0x00000000 MSR 0x100000E7 is now 0x00000000:0x00000000 MSR 0x100000E8 is now 0x00000000:0x00000000 MSR 0x10000080 is now 0x00000000:0x00000003 ---------- GLIU 1 ------------ MSR 0x40000020 is now 0x20000000:0x000FFF80 MSR 0x40000021 is now 0x20000000:0x080FFFE0 MSR 0x40000022 is now 0x000000FF:0xFFF00000 MSR 0x40000023 is now 0x20000040:0x400FFFE0 MSR 0x40000024 is now 0x000000FF:0xFFF00000 MSR 0x40000025 is now 0x000000FF:0xFFF00000 MSR 0x40000026 is now 0x000000FF:0xFFF00000 MSR 0x40000027 is now 0x000000FF:0xFFF00000 MSR 0x40000028 is now 0x000000FF:0xFFF00000 MSR 0x40000029 is now 0x2000001F:0xFDF00100 MSR 0x4000002A is now 0x00000000:0x000FFFFF MSR 0x4000002B is now 0x00000000:0x000FFFFF MSR 0x4000002C is now 0x00000000:0x000FFFFF MSR 0x4000002D is now 0x2000FFFF:0xFFFF0003 MSR 0x400000E0 is now 0x000000FF:0xFFF00000 MSR 0x400000E1 is now 0x000000FF:0xFFF00000 MSR 0x400000E2 is now 0x000000FF:0xFFF00000 MSR 0x400000E3 is now 0x60000000:0x033000F0 MSR 0x400000E4 is now 0x00000000:0x00000000 MSR 0x400000E5 is now 0x00000000:0x00000000 MSR 0x400000E6 is now 0x00000000:0x00000000 MSR 0x400000E7 is now 0x00000000:0x00000000 MSR 0x400000E8 is now 0x00000000:0x00000000 MSR 0x40000080 is now 0x00000000:0x00000001 ---------- RCONF ------------ MSR 0x00001810 is now 0x00000000:0x00000000 MSR 0x00001811 is now 0x00000000:0x00000000 MSR 0x00001812 is now 0x00000000:0x00000000 MSR 0x00001813 is now 0x00000000:0x00000000 MSR 0x00001814 is now 0x00000000:0x00000000 MSR 0x00001815 is now 0x00000000:0x00000000 MSR 0x00001816 is now 0x00000000:0x00000000 MSR 0x00001817 is now 0x00000000:0x00000000 ---------- VARIA ------------ MSR 0x51300010 is now 0x00000000:0x00000000 MSR 0x51400014 is now 0x00000000:0x04070003 MSR 0x51400015 is now 0x00000000:0x00000071 ---------- PCI ------------ MSR 0x50002010 is now 0xFFF030F8:0x001A0215 MSR 0x50002011 is now 0x00000300:0x00000100 MSR 0x50002014 is now 0x00000000:0x00FFFF00 MSR 0x50002015 is now 0x35353535:0x35353535 MSR 0x50002016 is now 0x35353535:0x35353535 MSR 0x50002017 is now 0x35353535:0x35353535 MSR 0x50002018 is now 0x0009F000:0x00000130 MSR 0x50002019 is now 0x1FFDF000:0x00100130 MSR 0x5000201A is now 0x4041F000:0x40400120 MSR 0x5000201B is now 0x00000000:0x00000000 MSR 0x5000201E is now 0x00000000:0x00000F00 MSR 0x5000201F is now 0x00000000:0x0000006B ---------- LPC/UART DMA ------------ MSR 0x51400040 is now 0x00000000:0x00000000 MSR 0x51400041 is now 0x00000000:0x0000009C MSR 0x51400042 is now 0x00000000:0x000000D1 MSR 0x51400043 is now 0x00000000:0x000000FE MSR 0x51400044 is now 0x00000000:0x000000FF MSR 0x51400045 is now 0x00000000:0x000000BC MSR 0x51400046 is now 0x00000000:0x000000C9 MSR 0x51400047 is now 0x00000000:0x0000005E MSR 0x51400048 is now 0x00000000:0x000000FF MSR 0x51400049 is now 0x00000000:0x000000FF ---------- DIVIL IRQ ------------ MSR 0x51400020 is now 0x00000000:0x00000000 MSR 0x51400021 is now 0x00000000:0x00000000 MSR 0x51400022 is now 0x00000000:0x00000000 MSR 0x51400023 is now 0x00000000:0x00000000 MSR 0x51400024 is now 0x00000000:0x0000FFFF ---------- DIVIL LBAR ----------- MSR 0x5140000C is now 0x0000F001:0x00006100 MSR 0x51400010 is now 0x00000000:0x00000000 MSR 0x51400011 is now 0x00000000:0x00000000 IOR 0x00006120 is now 0x3DFBC204 IOR 0x00006138 is now 0xFFFFFFFF IOR 0x00006124 is now 0xFFFFFFFF IOR 0x000061E0 is now 0xFFFFFFFF Preparing for VSA... Real mode stub @00000600: 867 bytes CBFS: loading stage vsa @ 0x60000 (153593 bytes), entry @ 0x60020 VSA: Buffer @00060000 *[0k]=ba VSA: Signature *[0x20-0x23] is b0:10:e6:80 Calling VSA module... Unsupported software interrupt #0x15 eax 0xbea7 Unsupported software interrupt #0x15 eax 0xbea4 ... VSA module returned. VSM: VSA2 VR signature verified. Graphics init... VRC_VG value: 0x0a10 DOMAIN: 0000 enabled >> Entering northbridge.c: enable_dev with path 7 CPU_CLUSTER: 0 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 >> Entering northbridge.c: enable_dev with path 2 PCI: 00:01.0 [100b/0028] ops PCI: 00:01.0 [100b/0028] enabled >> Entering northbridge.c: enable_dev with path 2 PCI: 00:01.1 [100b/0030] enabled cs5536: southbridge_enable: dev is 00116800 PCI: 00:0e.0 [10ec/8139] enabled cs5536: southbridge_enable: dev is 00116898 PCI: 00:0f.0 [1022/2090] bus ops PCI: 00:0f.0 [1022/2090] enabled cs5536: southbridge_enable: dev is 00116930 PCI: 00:0f.2 [1022/209a] ops PCI: 00:0f.2 [1022/209a] enabled cs5536: southbridge_enable: dev is 001169c8 PCI: 00:0f.3 [1022/2093] enabled cs5536: southbridge_enable: dev is 00116a60 PCI: 00:0f.4 [1022/2094] enabled cs5536: southbridge_enable: dev is 00116af8 PCI: 00:0f.5 [1022/2095] enabled PCI: 00:0f.6 [1022/2096] enabled PCI: 00:0f.7 [1022/2097] enabled scan_static_bus for PCI: 00:0f.0 scan_static_bus for PCI: 00:0f.0 done PCI: pci_scan_bus returning with max=000 scan_static_bus for Root Device done done found VGA at PCI: 00:01.1 Setting up VGA for PCI: 00:01.1 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 DOMAIN: 0000 read_resources bus 0 link: 0 DOMAIN: 0000 read_resources bus 0 link: 0 done CPU_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources CPU_CLUSTER: 0 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 DOMAIN: 0000 DOMAIN: 0000 child on link 0 PCI: 00:01.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 10 PCI: 00:01.1 PCI: 00:01.1 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10 PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 14 PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 18 PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c PCI: 00:0e.0 PCI: 00:0e.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 00:0e.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14 PCI: 00:0f.0 PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:0f.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14 PCI: 00:0f.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 18 PCI: 00:0f.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 1c PCI: 00:0f.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 20 PCI: 00:0f.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 24 PCI: 00:0f.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:0f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:0f.2 PCI: 00:0f.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:0f.3 PCI: 00:0f.3 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 10 PCI: 00:0f.4 PCI: 00:0f.4 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:0f.5 PCI: 00:0f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:0f.6 PCI: 00:0f.6 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 10 PCI: 00:0f.7 PCI: 00:0f.7 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:0e.0 10 * [0x0 - 0xff] io PCI: 00:0f.0 14 * [0x400 - 0x4ff] io PCI: 00:0f.0 20 * [0x800 - 0x87f] io PCI: 00:0f.3 10 * [0x880 - 0x8ff] io PCI: 00:0f.0 18 * [0xc00 - 0xc3f] io PCI: 00:0f.0 24 * [0xc40 - 0xc7f] io PCI: 00:0f.0 1c * [0xc80 - 0xc9f] io PCI: 00:0f.2 20 * [0xca0 - 0xcaf] io PCI: 00:0f.0 10 * [0xcb0 - 0xcb7] io PCI: 00:01.0 10 * [0xcb8 - 0xcbb] io DOMAIN: 0000 compute_resources_io: base: cbc size: cbc align: 8 gran: 0 limit: ffff done DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:01.1 10 * [0x0 - 0xffffff] mem PCI: 00:01.1 14 * [0x1000000 - 0x1003fff] mem PCI: 00:01.1 18 * [0x1004000 - 0x1007fff] mem PCI: 00:01.1 1c * [0x1008000 - 0x100bfff] mem PCI: 00:0f.6 10 * [0x100c000 - 0x100dfff] mem PCI: 00:0f.4 10 * [0x100e000 - 0x100efff] mem PCI: 00:0f.5 10 * [0x100f000 - 0x100ffff] mem PCI: 00:0f.7 10 * [0x1010000 - 0x1010fff] mem PCI: 00:0e.0 14 * [0x1011000 - 0x10110ff] mem DOMAIN: 0000 compute_resources_mem: base: 1011100 size: 1011100 align: 24 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: DOMAIN: 0000 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 00:01.1 constrain_resources: PCI: 00:0e.0 constrain_resources: PCI: 00:0f.0 constrain_resources: PCI: 00:0f.2 constrain_resources: PCI: 00:0f.3 constrain_resources: PCI: 00:0f.4 constrain_resources: PCI: 00:0f.5 constrain_resources: PCI: 00:0f.6 constrain_resources: PCI: 00:0f.7 avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ffff avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit febfffff Setting resources... DOMAIN: 0000 allocate_resources_io: base:1000 size:cbc align:8 gran:0 limit:ffff Assigned: PCI: 00:0e.0 10 * [0x1000 - 0x10ff] io Assigned: PCI: 00:0f.0 14 * [0x1400 - 0x14ff] io Assigned: PCI: 00:0f.0 20 * [0x1800 - 0x187f] io Assigned: PCI: 00:0f.3 10 * [0x1880 - 0x18ff] io Assigned: PCI: 00:0f.0 18 * [0x1c00 - 0x1c3f] io Assigned: PCI: 00:0f.0 24 * [0x1c40 - 0x1c7f] io Assigned: PCI: 00:0f.0 1c * [0x1c80 - 0x1c9f] io Assigned: PCI: 00:0f.2 20 * [0x1ca0 - 0x1caf] io Assigned: PCI: 00:0f.0 10 * [0x1cb0 - 0x1cb7] io Assigned: PCI: 00:01.0 10 * [0x1cb8 - 0x1cbb] io DOMAIN: 0000 allocate_resources_io: next_base: 1cbc size: cbc align: 8 gran: 0 done DOMAIN: 0000 allocate_resources_mem: base:fd000000 size:1011100 align:24 gran:0 limit:febfffff Assigned: PCI: 00:01.1 10 * [0xfd000000 - 0xfdffffff] mem Assigned: PCI: 00:01.1 14 * [0xfe000000 - 0xfe003fff] mem Assigned: PCI: 00:01.1 18 * [0xfe004000 - 0xfe007fff] mem Assigned: PCI: 00:01.1 1c * [0xfe008000 - 0xfe00bfff] mem Assigned: PCI: 00:0f.6 10 * [0xfe00c000 - 0xfe00dfff] mem Assigned: PCI: 00:0f.4 10 * [0xfe00e000 - 0xfe00efff] mem Assigned: PCI: 00:0f.5 10 * [0xfe00f000 - 0xfe00ffff] mem Assigned: PCI: 00:0f.7 10 * [0xfe010000 - 0xfe010fff] mem Assigned: PCI: 00:0e.0 14 * [0xfe011000 - 0xfe0110ff] mem DOMAIN: 0000 allocate_resources_mem: next_base: fe011100 size: 1011100 align: 24 gran: 0 done Root Device assign_resources, bus 0 link: 0 >> Entering northbridge.c: pci_domain_set_resources CBMEM region 1f7c0000-1f7dffff (cbmem_late_set_table) DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.1 10 <- [0x00fd000000 - 0x00fdffffff] size 0x01000000 gran 0x18 mem PCI: 00:01.1 14 <- [0x00fe000000 - 0x00fe003fff] size 0x00004000 gran 0x0e mem PCI: 00:01.1 18 <- [0x00fe004000 - 0x00fe007fff] size 0x00004000 gran 0x0e mem PCI: 00:01.1 1c <- [0x00fe008000 - 0x00fe00bfff] size 0x00004000 gran 0x0e mem PCI: 00:0e.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:0e.0 14 <- [0x00fe011000 - 0x00fe0110ff] size 0x00000100 gran 0x08 mem PCI: 00:0f.0 10 <- [0x0000001cb0 - 0x0000001cb7] size 0x00000008 gran 0x03 io PCI: 00:0f.0 14 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io PCI: 00:0f.0 18 <- [0x0000001c00 - 0x0000001c3f] size 0x00000040 gran 0x06 io PCI: 00:0f.0 1c <- [0x0000001c80 - 0x0000001c9f] size 0x00000020 gran 0x05 io PCI: 00:0f.0 20 <- [0x0000001800 - 0x000000187f] size 0x00000080 gran 0x07 io PCI: 00:0f.0 24 <- [0x0000001c40 - 0x0000001c7f] size 0x00000040 gran 0x06 io PCI: 00:0f.2 20 <- [0x0000001ca0 - 0x0000001caf] size 0x00000010 gran 0x04 io PCI: 00:0f.3 10 <- [0x0000001880 - 0x00000018ff] size 0x00000080 gran 0x07 io PCI: 00:0f.4 10 <- [0x00fe00e000 - 0x00fe00efff] size 0x00001000 gran 0x0c mem PCI: 00:0f.5 10 <- [0x00fe00f000 - 0x00fe00ffff] size 0x00001000 gran 0x0c mem PCI: 00:0f.6 10 <- [0x00fe00c000 - 0x00fe00dfff] size 0x00002000 gran 0x0d mem PCI: 00:0f.7 10 <- [0x00fe010000 - 0x00fe010fff] size 0x00001000 gran 0x0c mem DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 DOMAIN: 0000 DOMAIN: 0000 child on link 0 PCI: 00:01.0 DOMAIN: 0000 resource base 1000 size cbc align 8 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base fd000000 size 1011100 align 24 gran 0 limit febfffff flags 40040200 index 10000100 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a DOMAIN: 0000 resource base c0000 size 1f720000 align 0 gran 0 limit 0 flags e0004200 index b PCI: 00:01.0 PCI: 00:01.0 resource base 1cb8 size 4 align 2 gran 2 limit ffff flags 40000100 index 10 PCI: 00:01.1 PCI: 00:01.1 resource base fd000000 size 1000000 align 24 gran 24 limit febfffff flags 60000200 index 10 PCI: 00:01.1 resource base fe000000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 14 PCI: 00:01.1 resource base fe004000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 18 PCI: 00:01.1 resource base fe008000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 1c PCI: 00:0e.0 PCI: 00:0e.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 index 10 PCI: 00:0e.0 resource base fe011000 size 100 align 8 gran 8 limit febfffff flags 60000200 index 14 PCI: 00:0f.0 PCI: 00:0f.0 resource base 1cb0 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:0f.0 resource base 1400 size 100 align 8 gran 8 limit ffff flags 60000100 index 14 PCI: 00:0f.0 resource base 1c00 size 40 align 6 gran 6 limit ffff flags 60000100 index 18 PCI: 00:0f.0 resource base 1c80 size 20 align 5 gran 5 limit ffff flags 60000100 index 1c PCI: 00:0f.0 resource base 1800 size 80 align 7 gran 7 limit ffff flags 60000100 index 20 PCI: 00:0f.0 resource base 1c40 size 40 align 6 gran 6 limit ffff flags 60000100 index 24 PCI: 00:0f.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:0f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:0f.2 PCI: 00:0f.2 resource base 1ca0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:0f.3 PCI: 00:0f.3 resource base 1880 size 80 align 7 gran 7 limit ffff flags 60000100 index 10 PCI: 00:0f.4 PCI: 00:0f.4 resource base fe00e000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 PCI: 00:0f.5 PCI: 00:0f.5 resource base fe00f000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 PCI: 00:0f.6 PCI: 00:0f.6 resource base fe00c000 size 2000 align 13 gran 13 limit febfffff flags 60000200 index 10 PCI: 00:0f.7 PCI: 00:0f.7 resource base fe010000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 Done allocating resources. Enabling resources... PCI: 00:01.0 cmd <- 05 PCI: 00:01.1 subsystem <- 0000/0000 PCI: 00:01.1 cmd <- 03 PCI: 00:0e.0 subsystem <- 0000/0000 PCI: 00:0e.0 cmd <- 03 PCI: 00:0f.0 cmd <- 09 PCI: 00:0f.2 cmd <- 01 PCI: 00:0f.3 subsystem <- 0000/0000 PCI: 00:0f.3 cmd <- 01 PCI: 00:0f.4 subsystem <- 0000/0000 PCI: 00:0f.4 cmd <- 02 PCI: 00:0f.5 subsystem <- 0000/0000 PCI: 00:0f.5 cmd <- 02 PCI: 00:0f.6 cmd <- 02 PCI: 00:0f.7 cmd <- 02 done. Initializing devices... Root Device init S50 ENTER init S50 EXIT init CPU_CLUSTER: 0 init >> Entering northbridge.c: cpu_bus_init Initializing CPU #0 CPU: vendor NSC device 552 CPU: family 05, model 05, stepping 02 geode_gx2_init Enabling cache Oops, exception 0 while executing option rom Unexpected Exception: 0 @ 00:00000000 - Halting Code: 0 eflags: 00000000 eax: 00000000 ebx: 00000000 ecx: 00000000 edx: 00000000 edi: 00000000 esi: 00000000 ebp: 00000000 esp: 00000000 ffffffc0: 00 00 00 00 00 00 00 00 ffffffc8: 00 00 00 00 00 00 00 00 ffffffd0: 00 00 00 00 00 00 00 00 ffffffd8: 00 00 00 00 00 00 00 00 ffffffe0: 00 00 00 00 00 00 00 00 ffffffe8: 00 00 00 00 00 00 00 00 fffffff0: e9 fd fc ff ff 00 00 00 fffffff8: e9 5f fd ff d0 fc ff ff 00000000: 00 10 00 00 09 10 00 00 00000008: 12 10 00 00 1b 10 00 00 00000010: 24 10 00 00 2d 10 00 00 00000018: 36 10 00 00 3f 10 00 00 00000020: 48 10 00 00 51 10 00 00 00000028: 5a 10 00 00 63 10 00 00 00000030: 6c 10 00 00 75 10 00 00 00000038: 7e 10 00 00 87 10 00 00 .config: # # Automatically generated make config: don't edit # coreboot version: 4.0-5512-g6e56de3 # Sun Feb 16 17:25:53 2014 # # # General setup # # CONFIG_EXPERT is not set CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" # CONFIG_ALT_CBFS_LOAD_PAYLOAD is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_SCANBUILD_ENABLE is not set # CONFIG_CCACHE is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y # CONFIG_EARLY_CBMEM_INIT is not set # CONFIG_DYNAMIC_CBMEM is not set # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set # # Mainboard # # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set # CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_ADVANSUS is not set # CONFIG_VENDOR_ADVANTECH is not set # CONFIG_VENDOR_AMD is not set # CONFIG_VENDOR_AOPEN is not set # CONFIG_VENDOR_ARIMA is not set # CONFIG_VENDOR_ARTECGROUP is not set # CONFIG_VENDOR_ASI is not set # CONFIG_VENDOR_ASROCK is not set # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AVALUE is not set # CONFIG_VENDOR_AXUS is not set # CONFIG_VENDOR_AZZA is not set # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BCOM is not set # CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_EAGLELION is not set # CONFIG_VENDOR_ECS is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set # CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_IEI is not set # CONFIG_VENDOR_INTEL is not set # CONFIG_VENDOR_IWAVE is not set # CONFIG_VENDOR_IWILL is not set # CONFIG_VENDOR_JETWAY is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LANNER is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set # CONFIG_VENDOR_NEWISYS is not set # CONFIG_VENDOR_NOKIA is not set # CONFIG_VENDOR_NVIDIA is not set # CONFIG_VENDOR_PCENGINES is not set # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set # CONFIG_VENDOR_SUPERMICRO is not set # CONFIG_VENDOR_TECHNEXION is not set # CONFIG_VENDOR_TECHNOLOGIC is not set # CONFIG_VENDOR_TELEVIDEO is not set # CONFIG_VENDOR_TI is not set # CONFIG_VENDOR_THOMSON is not set # CONFIG_VENDOR_TRAVERSE is not set # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set CONFIG_VENDOR_WYSE=y CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="wyse/s50" CONFIG_MAINBOARD_PART_NUMBER="s50" CONFIG_IRQ_SLOT_COUNT=3 CONFIG_MAINBOARD_VENDOR="Wyse" CONFIG_MAX_CPUS=1 CONFIG_RAMTOP=0x200000 CONFIG_HEAP_SIZE=0x4000 CONFIG_RAMBASE=0x100000 CONFIG_DRIVERS_PS2_KEYBOARD=y # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set # CONFIG_VGA_BIOS is not set # CONFIG_CONSOLE_POST is not set # CONFIG_UDELAY_IO is not set CONFIG_DCACHE_RAM_BASE=0xc8000 CONFIG_DCACHE_RAM_SIZE=0x04000 CONFIG_SERIAL_CPU_INIT=y CONFIG_ACPI_SSDTX_NUM=0 # CONFIG_PCI_64BIT_PREF_MEM is not set CONFIG_ID_SECTION_OFFSET=0x80 CONFIG_STACK_SIZE=0x1000 CONFIG_XIP_ROM_SIZE=0x10000 # CONFIG_MMCONF_SUPPORT_DEFAULT is not set # CONFIG_VGA is not set CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Wyse" CONFIG_MAINBOARD_VERSION="1.0" CONFIG_CPU_ADDR_BITS=32 CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set CONFIG_LOGICAL_CPUS=y # CONFIG_IOAPIC is not set # CONFIG_SMP is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 CONFIG_BOARD_WYSE_S50=y CONFIG_BOARD_ROMSIZE_KB_256=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set # CONFIG_COREBOOT_ROMSIZE_KB_128 is not set # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set CONFIG_COREBOOT_ROMSIZE_KB_1024=y # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set # CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set CONFIG_COREBOOT_ROMSIZE_KB=1024 CONFIG_ROM_SIZE=0x100000 # CONFIG_ENABLE_POWER_BUTTON is not set CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="s50" CONFIG_ARCH_X86=y # CONFIG_ARCH_ARMV7 is not set # # Architecture (x86) # CONFIG_X86_ARCH_OPTIONS=y # CONFIG_SIPI_VECTOR_IN_ROM is not set CONFIG_MAX_REBOOT_CNT=3 CONFIG_NUM_IPI_STARTS=2 CONFIG_X86_BOOTBLOCK_SIMPLE=y # CONFIG_X86_BOOTBLOCK_NORMAL is not set CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_UPDATE_IMAGE is not set # CONFIG_ROMCC is not set CONFIG_PC80_SYSTEM=y # CONFIG_HAVE_CMOS_DEFAULT is not set CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set CONFIG_HPET_ADDRESS=0xfed00000 CONFIG_HAVE_ARCH_MEMSET=y CONFIG_HAVE_ARCH_MEMCPY=y CONFIG_HAVE_ARCH_MEMMOVE=y # CONFIG_MAINBOARD_HAS_CHROMEOS is not set # # Chipset # # # CPU # CONFIG_CPU_SPECIFIC_OPTIONS=y CONFIG_CPU_AMD_GEODE_GX2=y CONFIG_GEODE_VSA=y CONFIG_GEODE_VSA_FILE=y CONFIG_VSA_FILENAME="/home/aj/Downloads/coreboot/vsa2.bin" # CONFIG_CPU_AMD_AGESA is not set CONFIG_HAVE_INIT_TIMER=y CONFIG_HIGH_SCRATCH_MEMORY_SIZE=0x0 CONFIG_SMM_TSEG_SIZE=0 # CONFIG_SSE2 is not set # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set # CONFIG_UDELAY_LAPIC is not set CONFIG_UDELAY_TSC=y # CONFIG_TSC_CONSTANT_RATE is not set # CONFIG_TSC_MONOTONIC_TIMER is not set # CONFIG_UDELAY_TIMER2 is not set # CONFIG_TSC_CALIBRATE_WITH_IO is not set # CONFIG_TSC_SYNC_LFENCE is not set # CONFIG_TSC_SYNC_MFENCE is not set # CONFIG_CACHE_ROM is not set # CONFIG_SMM_TSEG is not set # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PARALLEL_MP is not set CONFIG_CACHE_AS_RAM=y CONFIG_AP_SIPI_VECTOR=0xfffff000 # CONFIG_SUPPORT_CPU_UCODE_IN_CBFS is not set # CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set CONFIG_CPU_MICROCODE_CBFS_NONE=y # # Northbridge # CONFIG_NORTHBRIDGE_AMD_GX2=y # CONFIG_GX2_VIDEO_MB_4MB is not set CONFIG_GX2_VIDEO_MB_8MB=y # CONFIG_GX2_VIDEO_MB_16MB is not set # CONFIG_GX2_VIDEO_MB_32MB is not set # CONFIG_GX2_VIDEO_MB_64MB is not set # CONFIG_GX2_VIDEO_MB_128MB is not set # CONFIG_GX2_VIDEO_MB_256MB is not set # CONFIG_GX2_VIDEO_MB_CMOS is not set CONFIG_VIDEO_MB=8 CONFIG_GX2_PROCESSOR_MHZ_366=y CONFIG_GX2_PROCESSOR_MHZ=366 # CONFIG_NORTHBRIDGE_AMD_AGESA is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set CONFIG_CBFS_SIZE=0x100000 CONFIG_MAX_PIRQ_LINKS=4 # # Southbridge # CONFIG_SOUTHBRIDGE_AMD_CS5536=y # CONFIG_AMD_SB_CIMX is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_AMD_SB_SPI_TX_LEN=4 # CONFIG_SPI_FLASH is not set # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set # # Super I/O # # # Embedded Controllers # # # SoC # # # Devices # # CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y # CONFIG_PCI_OPTION_ROM_RUN_YABEL is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set CONFIG_PCI=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_AGP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set # CONFIG_PCIEXP_ASPM is not set CONFIG_PCI_BUS_SEGN_BITS=0 # # VGA BIOS # # # Display # # CONFIG_FRAMEBUFFER_SET_VESA_MODE is not set # CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set # # PXE ROM # # CONFIG_PXE_ROM is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # # Generic Drivers # # CONFIG_DRIVERS_I2C_RTD2132 is not set # CONFIG_INTEL_DP is not set # CONFIG_INTEL_DDI is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVERS_OXFORD_OXPCIE is not set # CONFIG_DRIVER_PARADE_PS8625 is not set # CONFIG_TPM is not set # CONFIG_RTL8168_ROM_DISABLE is not set # CONFIG_DRIVERS_SIL_3114 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set # CONFIG_MMCONF_SUPPORT is not set # # Console # CONFIG_EARLY_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y CONFIG_CONSOLE_SERIAL=y CONFIG_CONSOLE_SERIAL8250=y CONFIG_CONSOLE_SERIAL_COM1=y # CONFIG_CONSOLE_SERIAL_COM2 is not set # CONFIG_CONSOLE_SERIAL_COM3 is not set # CONFIG_CONSOLE_SERIAL_COM4 is not set CONFIG_TTYS0_BASE=0x3f8 CONFIG_CONSOLE_SERIAL_115200=y # CONFIG_CONSOLE_SERIAL_57600 is not set # CONFIG_CONSOLE_SERIAL_38400 is not set # CONFIG_CONSOLE_SERIAL_19200 is not set # CONFIG_CONSOLE_SERIAL_9600 is not set CONFIG_TTYS0_BAUD=115200 CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_HAVE_USBDEBUG is not set # CONFIG_HAVE_USBDEBUG_OPTIONS is not set # CONFIG_CONSOLE_NE2K is not set # CONFIG_CONSOLE_CBMEM is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_NO_POST is not set # CONFIG_CMOS_POST is not set CONFIG_IO_POST=y CONFIG_IO_POST_PORT=0x80 CONFIG_HAVE_UART_IO_MAPPED=y # CONFIG_HAVE_UART_MEMORY_MAPPED is not set # CONFIG_HAVE_UART_SPECIAL is not set # CONFIG_HAVE_ACPI_RESUME is not set # CONFIG_HAVE_ACPI_SLIC is not set # CONFIG_HAVE_HARD_RESET is not set # CONFIG_HAVE_MONOTONIC_TIMER is not set # CONFIG_HAVE_OPTION_TABLE is not set CONFIG_PIRQ_ROUTE=y # CONFIG_HAVE_SMI_HANDLER is not set # CONFIG_PCI_IO_CFG_EXT is not set # CONFIG_USE_WATCHDOG_ON_BOOT is not set # CONFIG_GFXUMA is not set # CONFIG_RELOCATABLE_MODULES is not set # CONFIG_HAVE_REFCODE_BLOB is not set CONFIG_HAVE_PIRQ_TABLE=y # # System tables # # CONFIG_GENERATE_ACPI_TABLES is not set # CONFIG_GENERATE_MP_TABLE is not set CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y # # Payload # # CONFIG_PAYLOAD_NONE is not set # CONFIG_PAYLOAD_ELF is not set # CONFIG_PAYLOAD_LINUX is not set CONFIG_PAYLOAD_SEABIOS=y # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_TIANOCORE is not set CONFIG_SEABIOS_STABLE=y # CONFIG_SEABIOS_MASTER is not set CONFIG_PAYLOAD_FILE="$(obj)/seabios/out/bios.bin.elf" CONFIG_COMPRESSED_PAYLOAD_LZMA=y # # Debugging # # CONFIG_GDB_STUB is not set # CONFIG_DEBUG_CBFS is not set # CONFIG_HAVE_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set # CONFIG_DEBUG_PIRQ is not set # CONFIG_HAVE_DEBUG_SMBUS is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_REALMODE_DEBUG is not set # CONFIG_TRACE is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set CONFIG_POWER_BUTTON_FORCE_DISABLE=y # CONFIG_POWER_BUTTON_IS_OPTIONAL is not set Thanks, Andrew

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Re: [coreboot] Asus f2a85-m binary blobs?
by Dominic Walden Feb. 17, 2014

Feb. 17, 2014

David Hubbard <david.c.hubbard+coreboot(a)gmail.com> writes: > > I think your answer is pretty well answered here: > http://www.coreboot.org/Binary_situation > > The section "recent AMD" covers the f2a85-m binary situation. Thanks, this answers my question nicely. Dominic

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