coreboot February 2014

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148 discussions

Re: [coreboot] Unable to start correctly coreboot on Asus f2a85-m REV 1.02
by Scott Duplichan 01 Mar '14

01 Mar '14

HacKurx [mailto:hackurx@gmail.com] wrote: ]> David wrote: ]> It would still be helpful if you can post the details for this stick. ]1 Corsair CMV4GX3M1A1333C9 (4Gb & 1,5 Volt) ]http://www.ldlc.com/fiche/PB00104214.html ] ]> You may also want to post the output of "git diff" for others who may want to try Richland on the F2A85-]M. ]Ok, no problem :) ]http://pastebin.com/sTFzE5YN ] ]> Scott wrote: ]> you could try adding your cupid to the list ]One more step :) ]http://pastebin.com/kD2zmbua It looks like the wrong file was modified. That probably causes Orochi code to be used instead of Trinity as desired. Only change the one file in the family15tn directory: diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index f396201..1dbc064 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -123,6 +123,7 @@ static struct device_operations cpu_dev_ops = { static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, 0x610f00 }, /* TN-A0 */ + { X86_VENDOR_AMD, 0x610f31 }, /* RL-A1 (HACK) */ { 0, 0 }, }; Here is an optional change. That first hack that changes == to != is quite unreadable and confusing. I believe the following is a better solution. Also remember that running Trinity agesa on Richland is a hack and hopefully a temporary solution. Possible problems are: 1) desired microcode patch is not available 2) Any Richland errata workarounds embedded in the agesa code are not present 3) There might be some differences between Trinity and Richland recommended register settings. diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnLogicalIdTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnLogicalIdTables.c index 8157b57..bfcaa9a 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnLogicalIdTables.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnLogicalIdTables.c @@ -86,6 +86,12 @@ STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF15TnLogicalIdAndRevArray[] = 0x6101, AMD_F15_TN_A1 }, + + { // HACK: let Richland run Trinity agesa code + 0x6131, + AMD_F15_TN_A1 + }, + { 0x6100, 0x0000000000000100ull ]Thanks, ] ]2014-02-26 23:20 GMT+01:00 Scott Duplichan <scott(a)notabs.org>: ]> HacKurx [mailto:hackurx@gmail.com] wrote: ]> ]> ]> David wrote: ]> ]> With just 1 stick in the A1 slot, please post a pastebin of the console ]> ]> output. ]> ] ]> ]Perfect! It is perfectly detailed, the cpu is not recognized: ]> ]http://pastebin.com/2Lbew82b ]> ]> you could try adding your cupid to the list in ]> src/cpu/amd/agesa/family15tn/model_15_init.c: ]> ]> static struct cpu_device_id cpu_table[] = { ]> { X86_VENDOR_AMD, 0x610f00 }, /* TN-A0 */ ]> { X86_VENDOR_AMD, 0x610f31 }, /* RL-A1 */ ]> { 0, 0 }, ]> }; ]> Thanks, ]> Scott ]> ]> ]> ]Thanks, best regards, ] ]-- ]Best regards, ] ]HacKurx ]www.hackurx.info

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Please attach logs and not put them on pastebin service on mailing list (was: Unable to start correctly coreboot on Asus f2a85-m REV 1.02)
by Paul Menzel 27 Feb '14

27 Feb '14

Dear HacKurx, could you please attach the logs and not put them on some pastebin service. Pastebin is good for IRC in my opinion, but for mailing lists attachments are not useful as it is in one place. Thanks, Paul

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Re: [coreboot] Unable to start correctly coreboot on Asus f2a85-m REV 1.02
by David Hubbard 27 Feb '14

27 Feb '14

On Thu, Feb 27, 2014 at 2:53 PM, HacKurx <hackurx(a)gmail.com> wrote: > > David wrote: > > It would still be helpful if you can post the details for this stick. > 1 Corsair CMV4GX3M1A1333C9 (4Gb & 1,5 Volt) > http://www.ldlc.com/fiche/PB00104214.html > > > You may also want to post the output of "git diff" for others who may > want to try Richland on the F2A85-M. > Ok, no problem :) > http://pastebin.com/sTFzE5YN > > > Scott wrote: > > you could try adding your cupid to the list > One more step :) > http://pastebin.com/kD2zmbua > Ok, this is actually a step backward. In your previous output ( http://pastebin.com/2Lbew82b) I see "agesawrapper_amdinitpost failed: 4" on line 4296. In this latest output it only gets a little farther and dies at "Fch OEM config in INIT ENV Done". Try doing a full power cycle of the board and see if you get something better. I've seen coreboot die at "Fch OEM config in INIT ENV Done" doing a reboot, but I could fix it with a power cycle. This is really the point where you can start to dig in and try to get Richland working in coreboot. I'm probably of only limited usefulness, but others may have a better idea what needs to happen. Regards, David

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Re: [coreboot] Unable to start correctly coreboot on Asus f2a85-m REV 1.02
by Scott Duplichan 27 Feb '14

27 Feb '14

HacKurx [mailto:hackurx@gmail.com] wrote: ]> David wrote: ]> With just 1 stick in the A1 slot, please post a pastebin of the console ]> output. ] ]Perfect! It is perfectly detailed, the cpu is not recognized: ]http://pastebin.com/2Lbew82b you could try adding your cupid to the list in src/cpu/amd/agesa/family15tn/model_15_init.c: static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, 0x610f00 }, /* TN-A0 */ { X86_VENDOR_AMD, 0x610f31 }, /* RL-A1 */ { 0, 0 }, }; Thanks, Scott ]Thanks, best regards,

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Re: [coreboot] how to model the Quark architecture
by Peter Stuge 27 Feb '14

27 Feb '14

Stojsavljevic, Zoran wrote: > This what I have proposed binds to current Coreboot FSP support/framework Even though seamless integration of FSP with upstream coreboot is probably what Intel would want that approach is not neccessarily a satisfactory solutoin for the greater coreboot community. If Intel contributes squaky clean changes for coreboot which add support for the FSP then we can perhaps have further discussion. //Peter

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Re: [coreboot] Unable to start correctly coreboot on Asus f2a85-m REV 1.02
by David Hubbard 26 Feb '14

26 Feb '14

On Wed, Feb 26, 2014 at 12:54 PM, HacKurx <hackurx(a)gmail.com> wrote: > > David wrote: > > With just 1 stick in the A1 slot, please post a pastebin of the console > > output. > > Perfect! It is perfectly detailed, the cpu is not recognized: > http://pastebin.com/2Lbew82b > > Great, this is another big step in the right direction. It would still be helpful if you can post the details for this stick. You may also want to post the output of "git diff" for others who may want to try Richland on the F2A85-M. At this point, you'll need to study the code and find out exactly where it is dying. There may be someone who can spot it quickly, but I'm unsure of exactly what the issue is. I do think the line "Initializing devices" may mean that this is related to the devicetree code. It has successfully run the first part of AGESA, specifically initializing the memory controller, PCI-E, so you have a sort-of-working system.

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Re: [coreboot] Unable to start correctly coreboot on Asus f2a85-m REV 1.02
by HacKurx 26 Feb '14

26 Feb '14

> David wrote: > With just 1 stick in the A1 slot, please post a pastebin of the console > output. Perfect! It is perfectly detailed, the cpu is not recognized: http://pastebin.com/2Lbew82b Thanks, best regards,

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`DEBUG_INTEL_ME` (incorrectly) only selected for Intel BD82x6x
by Paul Menzel 26 Feb '14

26 Feb '14

Dear coreboot folks, looking through `src/console/Kconfig` I noticed if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8 # Only visible with the right southbridge and loglevel. config DEBUG_INTEL_ME bool "Verbose logging for Intel Management Engine" default n help Enable verbose logging for Intel Management Engine driver that is present on Intel 6-series chipsets. endif which seems odd as currently other chipsets needing the Intel Management Engine were submitted. $ git grep DEBUG_INTEL_ME src/Kconfig:config DEBUG_INTEL_ME src/southbridge/intel/bd82x6x/me.c:#if CONFIG_DEBUG_INTEL_ME src/southbridge/intel/bd82x6x/me_8.x.c:#if CONFIG_DEBUG_INTEL_ME src/southbridge/intel/fsp_bd82x6x/me.c:#if CONFIG_DEBUG_INTEL_ME src/southbridge/intel/fsp_bd82x6x/me_8.x.c:#if CONFIG_DEBUG_INTEL_ME src/southbridge/intel/ibexpeak/me.c:#if CONFIG_DEBUG_INTEL_ME src/southbridge/intel/lynxpoint/me_9.x.c:#if CONFIG_DEBUG_INTEL_ME src/southbridge/intel/lynxpoint/me_9.x.c:#if CONFIG_DEBUG_INTEL_ME src/southbridge/intel/lynxpoint/me_9.x.c:#if CONFIG_DEBUG_INTEL_ME src/southbridge/intel/lynxpoint/me_9.x.c:#if CONFIG_DEBUG_INTEL_ME I am unable to test this, so it would be great if somebody else could fix this. Thanks, Paul

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Re: [coreboot] Unable to start correctly coreboot on Asus f2a85-m REV 1.02
by David Hubbard 26 Feb '14

26 Feb '14

On Tue, Feb 25, 2014 at 1:39 PM, HacKurx <hackurx(a)gmail.com> wrote: > > Scott wrote: > > > > The cupid is not found because trinity support is included but > > richland support is needed. I do not know if forcing the trinity > > code to run on richland will work, but you could try it. One way > > to try it is to change the == to != on line 255 of file > > vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.c. > > Thank you very much, it is more verbose: > http://pastebin.com/Nszbv9p1 > > What do you think from this? > This is significant progress. It is trying to initialize the memory controller. Several people (myself included) have had problems in the past getting DDR3 memory to work, so we might be able to help you. Please check that the memory voltage in your .config matches your memory. Choices are 1.5V or 1.65V. Can you also reply with all the details for your memory? Please try removing all but 1 stick and put that one in the A1 slot. (See the motherboard manual for the slot numbering.) If that doesn't work you can try the other slots, but you will want to get 1 stick working before trying dual-channel etc. With just 1 stick in the A1 slot, please post a pastebin of the console output. If you have access to any other DDR3 RAM, especially if it is rated for a lower speed than your current RAM, you may want to try that also. Regards, David

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Re: [coreboot] Unable to start correctly coreboot on Asus f2a85-m REV 1.02
by Scott Duplichan 25 Feb '14

25 Feb '14

HacKurx [mailto:hackurx@gmail.com] wrote: ]Thank you for adding this great feature that I hope will be added by ]default in Kconfig. ]Unfortunately, this option has no more help me to solve my problem ]with the richland architecture. Your board is probably crashing at line 252 of file: vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.c SubFamilyIdPtr[j] ((CONST CPU_LOGICAL_ID_XLAT **)&CpuLogicalIdAndRevPtr, &LogicalIdEntries, &LogicalFamily, StdHeader); The reason is that the loop is processing each element of table F15LogicalIdTable until a match is found. But that table includes a NULL terminator (line 1176 of file: vendorcode/amd/agesa/f15tn/Include/ OptionFamily15hInstall.h) This means that if no CPUID match is found, a NULL function pointer will be called. That problem is an agesa bug that shows up only when an unsupported cpu is found. The cupid is not found because trinity support is included but richland support is needed. I do not know if forcing the trinity code to run on richland will work, but you could try it. One way to try it is to change the == to != on line 255 of file vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.c. Thanks, Scott

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coreboot February 2014