coreboot July 2013

coreboot@coreboot.org

45 participants
108 discussions

Re: [coreboot] Well supported energy efficient HTPC motherboard
by Oliver Schinagl 22 Jul '13

22 Jul '13

On 22-07-13 10:47, David Hubbard wrote: > Hi Oliver, > > By "hold those the recommendations" -- did you mean, "do those hold the > number one position as a recommendation" ? Can you clarify this question? "Get this board and it works really well!" ;) > > On Mon, Jul 22, 2013 at 2:07 AM, Oliver Schinagl > <oliver+list(a)schinagl.nl <mailto:oliver+list@schinagl.nl>> wrote: > > I see E-350 boards and F2A85 boards as being WiP/Supported but hold > those the recommendations? > > > You should be able to use either the ASRock E350M1 or F2A85 for an HTPC > board. I'm not personally familiar with the E350 status, but the only > issue from the wiki is after a reboot, and an HTPC could just be powered > off and back on. The F2A85 audio may have problems but only due to > incomplete ACPI tables, which can be fixed easily enough. E350 boards seem to be a dying breed (but tend to be better supported because they've been around for a while) > > Since you are looking for an HTPC it sounds like you are interested in > power usage and noise levels. I put the F2A85 with an A10-5800K on a > Kill-A-Watt and it idles at 52W when displaying text, or 35W after X11 > has started. Most likely, any socket FM2 chip from AMD will have a > similar idle load. Peak load is 110W which is close enough to the rated > TDP of 100W to make a power estimate easy for any CPU you choose. Ouch, those are pretty big numbers. I was acking towards the Asus F2A85 aswell but will probably look at a very power efficient APU variant. Don't they come in 65W TDP's? Granted these tdp's are including a GPU. I'm also leaning towards an external video card, due to the shared memory thing. Then again, it doesn't do a whole lot of heavy lifting so that shouldn't really be an issue. > > The stock heatsink/fan is nearly silent and does not get loud even under > a full CPU load. If you actually want a fully silent PC you should > probably get a larger heatsink/fan. My F2A85 system's power supply makes > more noise than the CPU fan. I have a fanless PSU in my HTPC box ;) So maybe i'll get a huge heatsink (2 very silent exhaust fans do exist) or keep my zalman that I currently use. > > Hope that helps, It does indeed, but due to financial situation right now, may have to put this off for a few months anyway. It never hurts to look around and see what's ot there and what's supported. > David

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Re: [coreboot] ASUS m5a88-v AGESA port (bulldozer): Linux does not set up SATA drives
by Paul Menzel 21 Jul '13

21 Jul '13

Dear Sebastian, Am Donnerstag, den 04.07.2013, 23:14 +0200 schrieb Sebastian Parborg: > I've made some more progress in this matter. I got rid of more coreboot log > errors and warning messages. I also managed to get rid off most of the > warnings the linux kernel prints when it boots. congrats! > However it seems like the linux kernel can't mount the sata drives. It > fails with "ata1: softreset failed (1st FIS failed)" please look at the > attached logs for more info. > > I find it really strange that it fails because I can use grub2 to browse > the and read the sata drives without any problem. > > It seems like I'm really close in getting this to work so I would be really > happy if any of you guys could help me out. I don't know what I can do to > fix this. There seem to be still some issues reported by Linux before the SATA error and the Oops afterward. [ 0.000000] WARNING: Bogus (zero) I/O APIC address found in table, skipping! No idea. [ 0.672053] pci0000:00: Requesting ACPI _OSC control (0x1d) [ 0.672909] pci0000:00: ACPI _OSC request failed (AE_NOT_FOUND), returned control mask: 0x1d [ 0.673907] ACPI _OSC control for PCIe not granted, disabling ASPM This should have been fixed for the other boards already. Make sure you have these fixes. Also make sure to set these up as separate commits so review is easier. [ 0.759288] pci 0000:00:01.0: BAR 15: can't assign mem pref (size 0x20000000) [ 0.766428] pci 0000:01:05.0: BAR 0: can't assign mem pref (size 0x20000000) [ 0.773482] pci 0000:01:05.0: BAR 0: trying firmware assignment [mem 0xc0000000-0xdfffffff pref] [ 0.782266] pci 0000:01:05.0: BAR 0: [mem 0xc0000000-0xdfffffff pref] conflicts with reserved [mem 0xbffe0000-0xdfffffff] [ 0.793226] pci 0000:00:01.0: PCI bridge to [bus 01-01] [ 0.798458] pci 0000:00:01.0: bridge window [io 0x1000-0x1fff] [ 0.804556] pci 0000:00:01.0: bridge window [mem 0xe0100000-0xe02fffff] [ 0.811357] pci 0000:00:09.0: PCI bridge to [bus 02-02] [ 0.816586] pci 0000:00:09.0: bridge window [io 0x2000-0x2fff] [ 0.822687] pci 0000:00:09.0: bridge window [mem 0xe0300000-0xe03fffff] [ 0.829473] pci 0000:00:0a.0: PCI bridge to [bus 03-03] [ 0.834707] pci 0000:00:0a.0: bridge window [mem 0xe0400000-0xe04fffff] [ 0.841495] pci 0000:00:14.4: PCI bridge to [bus 06-06] [ 0.846736] pci 0000:00:15.0: PCI bridge to [bus 04-04] [ 0.851969] pci 0000:00:15.1: PCI bridge to [bus 05-05] [ 0.857197] pci 0000:00:15.1: bridge window [io 0x3000-0x3fff] [ 0.863301] pci 0000:00:15.1: bridge window [mem 0xe0000000-0xe00fffff 64bit pref] [ 0.871067] pci 0000:00:15.0: can't derive routing for PCI INT A [ 0.877076] pci 0000:00:15.0: PCI INT A: no GSI [ 0.881633] pci 0000:00:15.1: can't derive routing for PCI INT A [ 0.887639] pci 0000:00:15.1: PCI INT A: no GSI The above might be a problem. As coreboot is responsible for setting PCI up as far as I know, there might be still a problem. If I were you, I would try to fix the above errors first. Often solving these, also fixes errors after it too. > I've attached three log files coreboot_log.txt is just the coreboot log, > kernel_log.txt is the what the kernel prints when it boot with my coreboot > rom and kernel_vanilla.txt is with the original bios image. Could you attach a diff of the two `kernel_log.txt` (without the time stamps) please? Two more ideas coming to my mind. First try to boot from an USB medium (from SeaBIOS for example) and look how far that goes and if you can compare lspci output from there. Maybe a newer Linux kernel also helps there. Try to play with the Linux kernel pata and ahci/libahi. `libahci` has an option `skip_host_reset` (`/sbin/modinfo libahci`). No idea if that helps and if there even is an option to avoid setting up the SATA controller into AHCI mode. Thanks, Paul

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Asrock E350M1 option roms
by Reiner Luett 21 Jul '13

21 Jul '13

Hello, I like to boot Grub from HDD in AHCI modus, but I can't get it working with the defaults for now. It only last until I power off the system. Where I could obtain the option roms for AHCI and the IMC firmware. Do I need to contact AMD or is it possible to extract it from the UEFI? I only have had success with the video bios and PXE. Please help! Best regards, Reiner --

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unsupported mb questions (amd fam10h)
by Roman Elshin 21 Jul '13

21 Jul '13

I try to get coreboot working with asrock 880g pro3 board. First problem: spd eprom say that memory ddr1600 capable, but it is not so, is there are right way to limit memory frequency at ddr1333? Other problem, may be related as machine with broken memory are very unpredictable: boot process stop with "It is not SB800 or SB810" message. I try to enable sb850 by this patch, but looks like it is not enough, most of time coreboot does not detect hdd. Sometimes in very rare case it is possible to boot from sata. Are sb850 supported by coreboot? ----------------------------------------------------------------------- diff -urN a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c --- a/src/southbridge/amd/sb800/early_setup.c 2012-07-14 19:00:40.000000000 +0400 +++ b/src/southbridge/amd/sb800/early_setup.c 2012-07-14 21:49:54.000000000 +0400 @@ -94,7 +94,10 @@ rev = REV_SB800_A11; } else if (rev_id == 0x41) { rev = REV_SB800_A12; - } else { + } else if (rev_id == 0x42) { + rev = REV_SB800_A13; + } + else { die("It is not SB800 or SB810\r\n"); } diff -urN a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h --- a/src/southbridge/amd/sb800/sb800.h 2012-07-14 19:00:40.000000000 +0400 +++ b/src/southbridge/amd/sb800/sb800.h 2012-07-14 21:49:10.000000000 +0400 @@ -48,7 +48,7 @@ #define REV_SB800_A11 0x11 #define REV_SB800_A12 0x12 - +#define REV_SB800_A13 0x13 #ifdef __PRE_RAM__ void sb800_lpc_port80(void); -------------------------------------------------------------------------

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Asus F2A85-M: is seabios patch still needed?
by David Hubbard 21 Jul '13

21 Jul '13

Hi Rudolf, I just tried booting coreboot with vgabios.bin as per http://www.coreboot.org/ASUS_F2A85-M but *without* the seabios patch there. The system boots ok, the on-CPU graphics are initialized, and everything seems to be working. I am using seabios head (ed88f6515c18d9520efa4a41ccb70038dfbe43f9) and coreboot head (4c2ebeba78e437df2d156a4c68f1fb15b62926f5). I could attempt a bisection search to find when the patch was last needed. However, can you or Sage Engineering confirm this? I can update the wiki entry for the board if the patch is not needed any more. Thanks, David

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Initial Kabini Wrapper Code
by Bruce Griffith 18 Jul '13

18 Jul '13

AGESA wrapper code is submitted into the community for the AMD Kabini processor and its embedded Yangtze southbridge. The Kabini AGESA code is not ready. The code I submitted into Gerrit today is not useful until the AGESA code is released. This is preliminary code for review. Bruce Griffith

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Re: [coreboot] coreboot rom file
by Peter Stuge 17 Jul '13

17 Jul '13

El Nerdo wrote: > I know that there might be a problem making the coreboot rom in > certain linux distros so do you know of a distro that has a good > compatibility in order to achieve this build? Most if not all distributions will be usable as long as you make sure to run: make crossgcc inside the coreboot source tree as the first command. This will build a working toolchain which can then be used to build coreboot. Verify that crossgcc has succeeded like so: cat .xcompile //Peter

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Re: [coreboot] coreboot rom file
by ron minnich 17 Jul '13

17 Jul '13

what we might do is extract the coreboot image and replace the fallback payload with seabios. We can try this at the tutorial (which I'm going to miss :-( ron

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coreboot rom file
by El Nerdo 17 Jul '13

17 Jul '13

Greetings! I was wondering if anyone has the coreboot romfile with the seabios payload already made for the Acer C7 chromebook. I would like to flash mine with it. If not, then I will attempt to make my own in Linux. I know that there might be a problem making the coreboot rom in certain linux distros so do you know of a distro that has a good compatibility in order to achieve this build? Final question, once I have a coreboot rom how to I start the flashrom utility in chome os dev mode? What are the commands to flash it? Thanks for any help.

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Re: [coreboot] Supported laptops (again), treacherous computing
by Nikita Karetnikov 13 Jul '13

13 Jul '13

> If somebody wants a laptop with coreboot today, that has vendor > support, get an acer c7 chromebook. If you can stand the keyboard, > which you really want to test. But it's an incredible deal. What do you mean by "vendor support"? Does it require any non-free components? Does it come with embedded options, and are they actually treacherous?

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coreboot July 2013