coreboot July 2013

coreboot@coreboot.org

45 participants
108 discussions

Re: [coreboot] new, need help and whatnot
by David Giard 26 Jul '13

26 Jul '13

I ended up using a raspberry pi before i even read David's reply, went on without an itch. I did see a light go green on the board though. Maybe i was lucky. Will remember to put a temporary jumper on the reset switch header next time. Thx On Thu, Jul 25, 2013 at 9:37 PM, David Hendricks <dhendrix(a)google.com>wrote: > On Wed, Jul 24, 2013 at 5:37 PM, David Giard <swe3tdave(a)gmail.com> wrote: > >> Hi everyone, >> >> This is my second email the first one did not get through, i think.. >> Anyway, this is a copy of the first one, with a few changes.. :) >> >> i'm new here(obviously), >> > > welcome! > > i've been talking to a few members already, after generating these logs, i >> played with flashrom and ended up with a Brick. I already ordered a Bus >> Pirate, and i already received my soic clips, so all is not lost. >> >> i have an Intel S3420GPLC Server Motherboard. Specs are here: >> http://download.intel.com/support/motherboards/server/s3420gp/sb/s3420gp_tp… >> >> msrtool.log is empty, got a core dump. >> >> rom.bin is here: >> https://docs.google.com/file/d/0Bx4lQySb-zrCT0RmVlB4d2pGa00/edit?usp=sharing >> >> Thankfully the rom looks complete so i should be able to unbrick the >> thing.. The board has an ME and a BMC, and yes i know that's probably why i >> ended up with a brick. I mean i could see the big warning sign in the docs, >> i just, well, wanted to learn something... :P There is a recovery bios on >> the thing, but it does not seems to work right now... ;) To think that i'm >> actually laughing about it is really something... :) >> >> i hope you guys can use these logs(see attached files).. :) >> > > Sounds like you've already identified the problem and are well on your way > to recovering your board. There are a few caveats though: > - Some boards do not isolate the ROM circuitry well, and your programmer > (Bus Pirate) may backpower motherboard components such as the ME, which > will attempt to boot and interfere with flashrom. So you may need to hold > the board in reset while you flash using the Bus Pirate in order for it to > be successful. > > - It is possible that when you read the ROM content earlier on that the ME > interfered by changing the SPI address and doing something while flashrom > was running. If that happened, your image may be corrupt and will need to > get a new firmware image from Intel's website and flash it instead. > > Good luck! > > > -- > David Hendricks (dhendrix) > Systems Software Engineer, Google Inc. >

1 0

Re: [coreboot] Samsung 550 Chromebook own Coreboot
by John Lewis 26 Jul '13

26 Jul '13

Well this is all I get if I have both ME and System agent enabled in menuconfig. And, yes, I did it all again from scratch in case. Thoughts? Name Offset Type Size cmos_layout.bin 0x700000 cmos_layout 1120 pci8086,0106.rom 0x7004c0 optionrom 65536 cpu_microcode_blob.bin 0x710500 microcode 20544 fallback/romstage 0x7155c0 stage 36127 fallback/coreboot_ram 0x71e340 stage 293960 fallback/payload 0x765fc0 payload 103784 (empty) 0x77f580 null 2584 mrc.cache 0x77ffc0 (unknown) 0 (empty) 0x780000 null 130968 mrc.bin 0x79ffc0 (unknown) 195732 (empty) 0x7cfcc0 null 49880 spd.bin 0x7dbfc0 (unknown) 1536 (empty) 0x7dc600 null 144216 On 23/07/2013 23:06, ron minnich wrote: > uh, yeah there needs to be an me.bin. mrc.bin is the code that runs > on > x86 to turn on memory.

2 1

Re: [coreboot] new, need help and whatnot
by David Hendricks 25 Jul '13

25 Jul '13

On Wed, Jul 24, 2013 at 5:37 PM, David Giard <swe3tdave(a)gmail.com> wrote: > Hi everyone, > > This is my second email the first one did not get through, i think.. > Anyway, this is a copy of the first one, with a few changes.. :) > > i'm new here(obviously), > welcome! i've been talking to a few members already, after generating these logs, i > played with flashrom and ended up with a Brick. I already ordered a Bus > Pirate, and i already received my soic clips, so all is not lost. > > i have an Intel S3420GPLC Server Motherboard. Specs are here: > http://download.intel.com/support/motherboards/server/s3420gp/sb/s3420gp_tp… > > msrtool.log is empty, got a core dump. > > rom.bin is here: > https://docs.google.com/file/d/0Bx4lQySb-zrCT0RmVlB4d2pGa00/edit?usp=sharing > > Thankfully the rom looks complete so i should be able to unbrick the > thing.. The board has an ME and a BMC, and yes i know that's probably why i > ended up with a brick. I mean i could see the big warning sign in the docs, > i just, well, wanted to learn something... :P There is a recovery bios on > the thing, but it does not seems to work right now... ;) To think that i'm > actually laughing about it is really something... :) > > i hope you guys can use these logs(see attached files).. :) > Sounds like you've already identified the problem and are well on your way to recovering your board. There are a few caveats though: - Some boards do not isolate the ROM circuitry well, and your programmer (Bus Pirate) may backpower motherboard components such as the ME, which will attempt to boot and interfere with flashrom. So you may need to hold the board in reset while you flash using the Bus Pirate in order for it to be successful. - It is possible that when you read the ROM content earlier on that the ME interfered by changing the SPI address and doing something while flashrom was running. If that happened, your image may be corrupt and will need to get a new firmware image from Intel's website and flash it instead. Good luck! -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

1 0

Re: [coreboot] Supported laptops (again), treacherous computing
by Nikita Karetnikov 25 Jul '13

25 Jul '13

> How do you want to help? You can get a Thinkpad right now, with the best > coreboot has to offer, knowing full well it isn't 100% free (yet). Well, I'm still not sure about that. Could you elaborate on non-free components? This page [1] is not clear about microcode, for instance. > You can start a porting effort for those AMD laptops. I don't have the needed skills. Moreover, I'm not even sure that I would be able to install Coreboot on a supported laptop. IIUC, even if I get one with a supported chipset, it might not work, right? I mentioned Thinkpads for two reasons: I thought they don't need proprietary components, and they are quite popular among Coreboot people. [1] http://www.coreboot.org/Thinkpad_X60s#proprietary_components_status

4 4

new, need help and whatnot
by David Giard 25 Jul '13

25 Jul '13

Hi again, This is the files i said i would be uploading once my motherboard is unbricked. Its a compressed archive, it contains: flashrom-erase.bricking1.log flashrom-write.bricking1.log rom.after.bricking1.bin - This is what was read from the rom before unbricking. secondrom.bin - This is the second rom, the documentation says that its attached to the bmc, and my guess is that it also contains the recovery bios. https://docs.google.com/file/d/0Bx4lQySb-zrCRFpJTkZkWjdRNUk/edit?usp=sharing Thanks, David

1 0

new, need help and whatnot
by David Giard 24 Jul '13

24 Jul '13

Hi everyone, This is my second email the first one did not get through, i think.. Anyway, this is a copy of the first one, with a few changes.. :) i'm new here(obviously), not sure what i'm going into, anyway, i've been following this page: http://www.coreboot.org/Laptop i know i dont have a Laptop.. i have a server, just did not find any other page to help me generate the needed logs. i've been talking to a few members already, after generating these logs, i played with flashrom and ended up with a Brick. I already ordered a Bus Pirate, and i already received my soic clips, so all is not lost. i have an Intel S3420GPLC Server Motherboard. Specs are here: http://download.intel.com/support/motherboards/server/s3420gp/sb/s3420gp_tp… msrtool.log is empty, got a core dump. rom.bin is here: https://docs.google.com/file/d/0Bx4lQySb-zrCT0RmVlB4d2pGa00/edit?usp=sharing Thankfully the rom looks complete so i should be able to unbrick the thing.. The board has an ME and a BMC, and yes i know that's probably why i ended up with a brick. I mean i could see the big warning sign in the docs, i just, well, wanted to learn something... :P There is a recovery bios on the thing, but it does not seems to work right now... ;) To think that i'm actually laughing about it is really something... :) i hope you guys can use these logs(see attached files).. :) Oh, one last thing, i have a log of the two commands i used to get my brick.. the files are just in a raid 0 right now and i've been waiting for their motherboard to be unbricked to get to them.. hopefully they will be of use to someone if i can ever upload them to you guys.. thx, David

1 0

Re: [coreboot] Samsung 550 Chromebook own Coreboot
by Aaron Durbin 24 Jul '13

24 Jul '13

Just so the mailing list sees that this worked. On Wed, Jul 24, 2013 at 10:54 AM, John Lewis <jlewis(a)johnlewis.ie> wrote: > Aaron, you're a star. I now have a SeaBIOS prompt and it's trying to boot > off the HD. :)))))))))))))))))) > > > On 24/07/2013 16:39, Aaron Durbin wrote: > >> On Wed, Jul 24, 2013 at 10:32 AM, John Lewis <jlewis(a)johnlewis.ie> wrote: >> >>> On 24/07/2013 16:16, Aaron Durbin wrote: >>> >>>> A couple things to change: CONFIG_CPU_ADDR_BITS=36 >>>> CONFIG_SPI_FLASH_NO_FAST_READ=y >>> >>> Okay will change and try again, just in case. I did notice there are 3 >>> different binaries in the 3rdparty/northbridge/intel/sandybridge >>> directory. Perhaps I should try systemagent-sandybridge.bin instead? >> >> >> It's a little more complicated. Looking at >> http://review.coreboot.org/#/c/3568/I think you'll need to do the >> >> following: >> >> git revert 1cc3416f5fb58883fdad7192856c258c01909fd7 >> >> Then set the mrc blob path to systemagent-sandybridge.bin. >> >> You might be hitting the same issues Kyosti was hitting. >> >> Lemme know how it goes. >> >>>> I *don't* think this is causing you grief, but these are different >>>> from the chromium repo. Also, you .config shows a 4MiB cbfs, but that >>>> doesn't jive with the cbfstool output from a previous email where it >>>> looked to be set to 1MiB. >>> >>> I had to increase the CBFS size to add the extra me.bin manually, >>> guess I can change it back if it makes any difference? >>> >>>> On Wed, Jul 24, 2013 at 9:51 AM, Aaron Durbin <adurbin(a)chromium.org >>>> [2]> wrote: >>>> >>>>> The config looks sane. I take it there i no serial port to see what >>>>> is going on. Kyosti has worked with this using usb debug. He has >>>>> also built upstream for lumpy. Kyosti, can you provide any guidance >>>>> for John? I don't have a lumpy to play with at my disposal. This >>>>> might be a mismatch withe system agent again (mrc.bin). I'm not >>>>> sure if that was ever resolved. On Wed, Jul 24, 2013 at 9:09 AM, >>>>> John Lewis <jlewis(a)johnlewis.ie [1][5]> wrote: >>>>> >>>>>> Aaron, On 24/07/2013 14:36, Aaron Durbin wrote: >>>>>> >>>>>>> John, Are you checking out the blobs repo into 3rdparty? In >>>>>>> that repo there are the following blobs for lumpy: >>> >>> >> > Yes.http://review.coreboot.org/gitweb?p=blobs.git;a=tree;f=mainboard/samsun… >>> >>> >>>> quote> [4] The descriptor and me blobs don't live in cbfs. They live >>>> >>>> in the rom but not as cbfs files. Yeah, I guessed it was something >>>> like that. I basically asked Ron that question an hour or so ago but >>>> forgot to cc the list. >>> >>> quote> Links: ------ [1] mailto:jlewis@johnlewis.ie [3] [2] >>> mailto:peter@stuge.se [4] [3] mailto:coreboot@coreboot.org [5] [4] >>> >> > http://review.coreboot.org/gitweb?p=blobs.git;a=tree;f=mainboard/samsung/lu… >>> >>> [6] [5] mailto:jlewis@johnlewis.ie [7] > > > > Links: > ------ > [1] mailto:jlewis@johnlewis.ie > [2] mailto:adurbin@chromium.org > [3] mailto:jlewis@johnlewis.ie > [4] mailto:peter@stuge.se > [5] mailto:coreboot@coreboot.org > [6] > http://review.coreboot.org/gitweb?p=blobs.git;a=tree;f=mainboard/samsung/lu… > [7] mailto:jlewis@johnlewis.ie

1 0

Re: [coreboot] Samsung 550 Chromebook own Coreboot
by John Lewis 24 Jul '13

24 Jul '13

On 24/07/2013 16:16, Aaron Durbin wrote: > A couple things to change: > > CONFIG_CPU_ADDR_BITS=36 > CONFIG_SPI_FLASH_NO_FAST_READ=y > Okay will change and try again, just in case. I did notice there are 3 different binaries in the 3rdparty/northbridge/intel/sandybridge directory. Perhaps I should try systemagent-sandybridge.bin instead? > I *don't* think this is causing you grief, but these are different > from the chromium repo. > > Also, you .config shows a 4MiB cbfs, but that doesn't jive with the > cbfstool output from a previous email where it looked to be set to > 1MiB. I had to increase the CBFS size to add the extra me.bin manually, guess I can change it back if it makes any difference? > > On Wed, Jul 24, 2013 at 9:51 AM, Aaron Durbin <adurbin(a)chromium.org> > wrote: > >> The config looks sane. I take it there i no serial port to see what >> is >> going on. Kyosti has worked with this using usb debug. He has also >> built upstream for lumpy. Kyosti, can you provide any guidance for >> John? I don't have a lumpy to play with at my disposal. This might >> be a >> mismatch withe system agent again (mrc.bin). I'm not sure if that >> was >> ever resolved. On Wed, Jul 24, 2013 at 9:09 AM, John Lewis >> <jlewis(a)johnlewis.ie [5]> wrote: >> >>> Aaron, On 24/07/2013 14:36, Aaron Durbin wrote: >>> >>>> John, Are you checking out the blobs repo into 3rdparty? In that >>>> repo there are the following blobs for lumpy: >>> >> > Yes.http://review.coreboot.org/gitweb?p=blobs.git;a=tree;f=mainboard/samsun… >>> [4] >>> >>>> The descriptor and me blobs don't live in cbfs. They live in the >>>> rom but not as cbfs files. >>> Yeah, I guessed it was something like that. I basically asked Ron >>> that question an hour or so ago but forgot to cc the list. Links: ------ [1] mailto:jlewis@johnlewis.ie [2] mailto:peter@stuge.se [3] mailto:coreboot@coreboot.org [4] http://review.coreboot.org/gitweb?p=blobs.git;a=tree;f=mainboard/samsung/lu… [5] mailto:jlewis@johnlewis.ie

2 1

Re: [coreboot] Samsung 550 Chromebook own Coreboot
by Aaron Durbin 24 Jul '13

24 Jul '13

A couple things to change: CONFIG_CPU_ADDR_BITS=36 CONFIG_SPI_FLASH_NO_FAST_READ=y I *don't* think this is causing you grief, but these are different from the chromium repo. Also, you .config shows a 4MiB cbfs, but that doesn't jive with the cbfstool output from a previous email where it looked to be set to 1MiB. On Wed, Jul 24, 2013 at 9:51 AM, Aaron Durbin <adurbin(a)chromium.org> wrote: > The config looks sane. I take it there i no serial port to see what is > going on. Kyosti has worked with this using usb debug. He has also > built upstream for lumpy. Kyosti, can you provide any guidance for > John? I don't have a lumpy to play with at my disposal. This might be > a mismatch withe system agent again (mrc.bin). I'm not sure if that > was ever resolved. > > On Wed, Jul 24, 2013 at 9:09 AM, John Lewis <jlewis(a)johnlewis.ie> wrote: >> Aaron, >> >> >> On 24/07/2013 14:36, Aaron Durbin wrote: >> >>> John, >>> >>> Are you checking out the blobs repo into 3rdparty? In that repo there >>> are the following blobs for lumpy: >>> >> >> Yes. >> >> >>> >> http://review.coreboot.org/gitweb?p=blobs.git;a=tree;f=mainboard/samsung/lu… >>> >>> >>> The descriptor and me blobs don't live in cbfs. They live in the rom >>> but not as cbfs files. >>> >> >> Yeah, I guessed it was something like that. I basically asked Ron that >> question an hour or so ago but forgot to cc the list. >> >> >>> Offset 0: >>> descriptor.bin >>> Offset 0 + sizeof(descriptor.bin): >>> me.bin >>> Offset 0 + sizeof(descriptor.bin) + sizeof(me.bin): >>> Usable rom space for corebot. This should be 6MiB. i.e. descriptor + >>> me.bin take 2MiB (there is some rounding). >>> >>> The mrc.bin needs to be at a fixed location in the address space (and >>> fixed location in rom) in order to work correctly. >>> >>> You will need adjust the CONFIG_ paths in your .config for the build >>> to work. Looking at src/southbridge/intel/bd82x6x/Makefile.inc I see >>> CONFIG_HAVE_ME_BIN needs to be set to y and CONFIG_ME_BIN_PATH needs >>> to be set accordingly like I provided my previous example for mrc.bin. >> >> >> AFAIK the paths I have are correct since the build finishes without error. >> >> >>> >>> Could you provide more details of your .config and the location of the >>> blobs on your local file system? This sounds like a simple build issue >>> in that the pieces aren't being placed in the proper places. I'm >>> guessing the default path locations in the Kconfigs just don't line up >>> correctly -- thus leading to some manual intervention. >>> >> >> Blobs are in 3rdparty/mainboard/samsung/lumpy and >> 3rdparty/northbridge/intel/sandybridge >> >> Here is my .config: >> >> # >> # Automatically generated make config: don't edit >> # coreboot version: 4.0-4562-g026ff3e >> # Wed Jul 24 12:57:28 2013 >> # >> >> # >> # General setup >> # >> # CONFIG_EXPERT is not set >> CONFIG_LOCALVERSION="" >> CONFIG_CBFS_PREFIX="fallback" >> # CONFIG_ALT_CBFS_LOAD_PAYLOAD is not set >> CONFIG_COMPILER_GCC=y >> # CONFIG_COMPILER_LLVM_CLANG is not set >> # CONFIG_SCANBUILD_ENABLE is not set >> # CONFIG_CCACHE is not set >> # CONFIG_USE_OPTION_TABLE is not set >> # CONFIG_COMPRESS_RAMSTAGE is not set >> # CONFIG_INCLUDE_CONFIG_FILE is not set >> CONFIG_EARLY_CBMEM_INIT=y >> # CONFIG_DYNAMIC_CBMEM is not set >> # CONFIG_COLLECT_TIMESTAMPS is not set >> CONFIG_USE_BLOBS=y >> # CONFIG_COVERAGE is not set >> >> # >> # Mainboard >> # >> # CONFIG_VENDOR_AAEON is not set >> # CONFIG_VENDOR_ABIT is not set >> # CONFIG_VENDOR_ADLINK is not set >> # CONFIG_VENDOR_ADVANSUS is not set >> # CONFIG_VENDOR_ADVANTECH is not set >> # CONFIG_VENDOR_AMD is not set >> # CONFIG_VENDOR_AOPEN is not set >> # CONFIG_VENDOR_ARIMA is not set >> # CONFIG_VENDOR_ARTECGROUP is not set >> # CONFIG_VENDOR_ASI is not set >> # CONFIG_VENDOR_ASROCK is not set >> # CONFIG_VENDOR_ASUS is not set >> # CONFIG_VENDOR_A_TREND is not set >> # CONFIG_VENDOR_AVALUE is not set >> # CONFIG_VENDOR_AXUS is not set >> # CONFIG_VENDOR_AZZA is not set >> # CONFIG_VENDOR_BACHMANN is not set >> # CONFIG_VENDOR_BCOM is not set >> # CONFIG_VENDOR_BIFFEROS is not set >> # CONFIG_VENDOR_BIOSTAR is not set >> # CONFIG_VENDOR_BROADCOM is not set >> # CONFIG_VENDOR_COMPAQ is not set >> # CONFIG_VENDOR_DIGITALLOGIC is not set >> # CONFIG_VENDOR_DMP is not set >> # CONFIG_VENDOR_EAGLELION is not set >> # CONFIG_VENDOR_ECS is not set >> # CONFIG_VENDOR_EMULATION is not set >> # CONFIG_VENDOR_GETAC is not set >> # CONFIG_VENDOR_GIGABYTE is not set >> # CONFIG_VENDOR_GOOGLE is not set >> # CONFIG_VENDOR_HP is not set >> # CONFIG_VENDOR_IBASE is not set >> # CONFIG_VENDOR_IBM is not set >> # CONFIG_VENDOR_IEI is not set >> # CONFIG_VENDOR_INTEL is not set >> # CONFIG_VENDOR_IWAVE is not set >> # CONFIG_VENDOR_IWILL is not set >> # CONFIG_VENDOR_JETWAY is not set >> # CONFIG_VENDOR_KONTRON is not set >> # CONFIG_VENDOR_LANNER is not set >> # CONFIG_VENDOR_LENOVO is not set >> # CONFIG_VENDOR_LIPPERT is not set >> # CONFIG_VENDOR_MITAC is not set >> # CONFIG_VENDOR_MSI is not set >> # CONFIG_VENDOR_NEC is not set >> # CONFIG_VENDOR_NEWISYS is not set >> # CONFIG_VENDOR_NOKIA is not set >> # CONFIG_VENDOR_NVIDIA is not set >> # CONFIG_VENDOR_PCENGINES is not set >> # CONFIG_VENDOR_RCA is not set >> # CONFIG_VENDOR_RODA is not set >> CONFIG_VENDOR_SAMSUNG=y >> # CONFIG_VENDOR_SIEMENS is not set >> # CONFIG_VENDOR_SOYO is not set >> # CONFIG_VENDOR_SUNW is not set >> # CONFIG_VENDOR_SUPERMICRO is not set >> # CONFIG_VENDOR_TECHNEXION is not set >> # CONFIG_VENDOR_TECHNOLOGIC is not set >> # CONFIG_VENDOR_TELEVIDEO is not set >> # CONFIG_VENDOR_TI is not set >> # CONFIG_VENDOR_THOMSON is not set >> # CONFIG_VENDOR_TRAVERSE is not set >> # CONFIG_VENDOR_TYAN is not set >> # CONFIG_VENDOR_VIA is not set >> # CONFIG_VENDOR_WINENT is not set >> # CONFIG_VENDOR_WYSE is not set >> CONFIG_BOARD_SPECIFIC_OPTIONS=y >> CONFIG_MAINBOARD_DIR="samsung/lumpy" >> CONFIG_MAINBOARD_PART_NUMBER="Lumpy" >> CONFIG_IRQ_SLOT_COUNT=18 >> CONFIG_MAINBOARD_VENDOR="SAMSUNG" >> CONFIG_MAX_CPUS=8 >> CONFIG_RAMTOP=0x200000 >> CONFIG_HEAP_SIZE=0x4000 >> CONFIG_RAMBASE=0x100000 >> CONFIG_VGA_BIOS_ID="8086,0106" >> CONFIG_DRIVERS_PS2_KEYBOARD=y >> CONFIG_ONBOARD_VGA_IS_PRIMARY=y >> CONFIG_VGA_BIOS=y >> # CONFIG_CONSOLE_POST is not set >> # CONFIG_UDELAY_IO is not set >> CONFIG_DCACHE_RAM_BASE=0xff7f0000 >> CONFIG_DCACHE_RAM_SIZE=0x10000 >> # CONFIG_SERIAL_CPU_INIT is not set >> CONFIG_ACPI_SSDTX_NUM=0 >> CONFIG_VGA_BIOS_FILE="pci8086,0106.rom" >> # CONFIG_PCI_64BIT_PREF_MEM is not set >> CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 >> CONFIG_ID_SECTION_OFFSET=0x80 >> CONFIG_XIP_ROM_SIZE=0x10000 >> # CONFIG_BOARD_GOOGLE_BUTTERFLY is not set >> # CONFIG_BOARD_GOOGLE_LINK is not set >> # CONFIG_BOARD_GOOGLE_PARROT is not set >> # CONFIG_BOARD_GOOGLE_PIT is not set >> # CONFIG_BOARD_GOOGLE_SNOW is not set >> # CONFIG_BOARD_GOOGLE_STOUT is not set >> CONFIG_MMCONF_SUPPORT_DEFAULT=y >> CONFIG_MRC_FILE="3rdparty/northbridge/intel/sandybridge/systemagent-r6.bin" >> CONFIG_HAVE_IFD_BIN=y >> CONFIG_HAVE_ME_BIN=y >> # CONFIG_HAVE_GBE_BIN is not set >> CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Samsung" >> # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set >> CONFIG_LOGICAL_CPUS=y >> CONFIG_IOAPIC=y >> CONFIG_SMP=y >> CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 >> # CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL is not set >> # CONFIG_USBDEBUG is not set >> # CONFIG_K8_REV_F_SUPPORT is not set >> CONFIG_BOARD_SAMSUNG_LUMPY=y >> # CONFIG_BOARD_SAMSUNG_STUMPY is not set >> CONFIG_CPU_ADDR_BITS=32 >> CONFIG_BOARD_ROMSIZE_KB_8192=y >> # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set >> # CONFIG_COREBOOT_ROMSIZE_KB_128 is not set >> # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set >> # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set >> # CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set >> # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set >> # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set >> CONFIG_COREBOOT_ROMSIZE_KB_8192=y >> # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set >> CONFIG_COREBOOT_ROMSIZE_KB=8192 >> CONFIG_ROM_SIZE=0x800000 >> CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" >> CONFIG_MAINBOARD_VERSION="1.0" >> CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Lumpy" >> CONFIG_ARCH_X86=y >> # CONFIG_ARCH_ARMV7 is not set >> >> # >> # Architecture (x86) >> # >> CONFIG_X86_ARCH_OPTIONS=y >> CONFIG_MARK_GRAPHICS_MEM_WRCOMB=y >> # CONFIG_AP_IN_SIPI_WAIT is not set >> # CONFIG_SIPI_VECTOR_IN_ROM is not set >> CONFIG_STACK_SIZE=0x1000 >> CONFIG_MAX_REBOOT_CNT=3 >> CONFIG_NUM_IPI_STARTS=2 >> CONFIG_X86_BOOTBLOCK_SIMPLE=y >> # CONFIG_X86_BOOTBLOCK_NORMAL is not set >> CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" >> # CONFIG_UPDATE_IMAGE is not set >> # CONFIG_ROMCC is not set >> CONFIG_PC80_SYSTEM=y >> CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/sandybridge/bootblock.c" >> # CONFIG_HAVE_CMOS_DEFAULT is not set >> CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/bd82x6x/bootblock.c" >> CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y >> # CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set >> CONFIG_HPET_ADDRESS=0xfed00000 >> CONFIG_HAVE_ARCH_MEMSET=y >> CONFIG_HAVE_ARCH_MEMCPY=y >> CONFIG_HAVE_ARCH_MEMMOVE=y >> >> # >> # Chipset >> # >> >> # >> # CPU >> # >> CONFIG_BOOTBLOCK_CPU_INIT="cpu/intel/model_206ax/bootblock.c" >> CONFIG_SOCKET_SPECIFIC_OPTIONS=y >> CONFIG_CPU_SPECIFIC_OPTIONS=y >> # CONFIG_CPU_AMD_AGESA is not set >> CONFIG_HAVE_INIT_TIMER=y >> CONFIG_HIGH_SCRATCH_MEMORY_SIZE=0x0 >> CONFIG_CPU_INTEL_MODEL_206AX=y >> CONFIG_SMM_TSEG_SIZE=0x800000 >> CONFIG_ENABLE_VMX=y >> CONFIG_MICROCODE_INCLUDE_PATH="src/cpu/intel/model_206ax" >> CONFIG_SSE2=y >> CONFIG_CPU_INTEL_SOCKET_RPGA989=y >> CONFIG_CACHE_MRC_BIN=y >> # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set >> CONFIG_UDELAY_LAPIC=y >> # CONFIG_LAPIC_MONOTONIC_TIMER is not set >> # CONFIG_UDELAY_TSC is not set >> # CONFIG_UDELAY_TIMER2 is not set >> # CONFIG_TSC_CALIBRATE_WITH_IO is not set >> # CONFIG_TSC_SYNC_LFENCE is not set >> CONFIG_TSC_SYNC_MFENCE=y >> CONFIG_CACHE_ROM=y >> CONFIG_SMM_TSEG=y >> # CONFIG_SMM_MODULES is not set >> # CONFIG_X86_AMD_FIXED_MTRRS is not set >> # CONFIG_CAR_MIGRATION is not set >> CONFIG_CACHE_AS_RAM=y >> CONFIG_AP_SIPI_VECTOR=0xfffff000 >> CONFIG_MMX=y >> CONFIG_SSE=y >> CONFIG_CPU_MICROCODE_IN_CBFS=y >> CONFIG_CPU_MICROCODE_CBFS_GENERATE=y >> # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set >> # CONFIG_CPU_MICROCODE_CBFS_NONE is not set >> >> # >> # Northbridge >> # >> CONFIG_VIDEO_MB=0 >> # CONFIG_NORTHBRIDGE_AMD_AGESA is not set >> # CONFIG_AMD_NB_CIMX is not set >> # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set >> CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y >> CONFIG_CACHE_MRC_SIZE_KB=256 >> CONFIG_MRC_CACHE_BASE=0xff800000 >> CONFIG_EXTERNAL_MRC_BLOB=y >> CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x4000 >> CONFIG_HAVE_MRC=y >> CONFIG_CBFS_SIZE=0x400000 >> CONFIG_HPET_MIN_TICKS=0x80 >> CONFIG_MAX_PIRQ_LINKS=4 >> >> # >> # Southbridge >> # >> CONFIG_EHCI_BAR=0xfef00000 >> CONFIG_EHCI_DEBUG_OFFSET=0xa0 >> # CONFIG_AMD_SB_CIMX is not set >> # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set >> # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set >> CONFIG_SPI_FLASH=y >> CONFIG_AMD_SB_SPI_TX_LEN=4 >> CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y >> CONFIG_SOUTH_BRIDGE_OPTIONS=y >> # CONFIG_SERIRQ_CONTINUOUS_MODE is not set >> # CONFIG_BUILD_WITH_FAKE_IFD is not set >> CONFIG_IFD_BIN_PATH="3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin" >> CONFIG_ME_BIN_PATH="3rdparty/mainboard/$(MAINBOARDDIR)/me.bin" >> # CONFIG_LOCK_MANAGEMENT_ENGINE is not set >> # CONFIG_LOCK_SPI_ON_RESUME is not set >> >> # >> # Super I/O >> # >> CONFIG_SUPERIO_SMSC_MEC1308=y >> >> # >> # Embedded Controllers >> # >> CONFIG_EC_SMSC_MEC1308=y >> >> # >> # Devices >> # >> # CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set >> # CONFIG_MULTIPLE_VGA_ADAPTERS is not set >> CONFIG_PCI=y >> # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set >> CONFIG_PCIX_PLUGIN_SUPPORT=y >> CONFIG_PCIEXP_PLUGIN_SUPPORT=y >> CONFIG_AGP_PLUGIN_SUPPORT=y >> CONFIG_CARDBUS_PLUGIN_SUPPORT=y >> CONFIG_PCIEXP_COMMON_CLOCK=y >> CONFIG_PCIEXP_ASPM=y >> CONFIG_PCI_BUS_SEGN_BITS=0 >> >> # >> # VGA BIOS >> # >> >> # >> # PXE ROM >> # >> # CONFIG_PXE_ROM is not set >> >> # >> # Generic Drivers >> # >> # CONFIG_ELOG is not set >> CONFIG_DRIVERS_GENERIC_IOAPIC=y >> # CONFIG_IPMI_KCS is not set >> # CONFIG_DRIVER_MAXIM_MAX77686 is not set >> # CONFIG_DRIVERS_OXFORD_OXPCIE is not set >> # CONFIG_DRIVER_PARADE_PS8625 is not set >> CONFIG_TPM=y >> CONFIG_RTL8168_ROM_DISABLE=y >> CONFIG_DRIVERS_SIL_3114=y >> # CONFIG_SPI_FLASH_SMM is not set >> CONFIG_SPI_FLASH_EON=y >> CONFIG_SPI_FLASH_MACRONIX=y >> CONFIG_SPI_FLASH_SPANSION=y >> CONFIG_SPI_FLASH_SST=y >> CONFIG_SPI_FLASH_STMICRO=y >> CONFIG_SPI_FLASH_WINBOND=y >> # CONFIG_SPI_FLASH_NO_FAST_READ is not set >> CONFIG_SPI_FLASH_GIGADEVICE=y >> # CONFIG_DRIVER_TI_TPS65090 is not set >> CONFIG_MMCONF_SUPPORT=y >> >> # >> # Console >> # >> CONFIG_EARLY_CONSOLE=y >> # CONFIG_CONSOLE_SERIAL is not set >> # CONFIG_SPKMODEM is not set >> CONFIG_HAVE_USBDEBUG=y >> # CONFIG_CONSOLE_NE2K is not set >> # CONFIG_CONSOLE_CBMEM is not set >> CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y >> # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set >> # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set >> # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set >> # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set >> # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set >> # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set >> # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set >> # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set >> # CONFIG_CONSOLE_LOGBUF is not set >> # CONFIG_NO_POST is not set >> # CONFIG_CMOS_POST is not set >> CONFIG_IO_POST=y >> CONFIG_IO_POST_PORT=0x80 >> CONFIG_HAVE_UART_IO_MAPPED=y >> # CONFIG_HAVE_UART_MEMORY_MAPPED is not set >> # CONFIG_HAVE_UART_SPECIAL is not set >> CONFIG_HAVE_ACPI_RESUME=y >> # CONFIG_HAVE_ACPI_SLIC is not set >> CONFIG_HAVE_HARD_RESET=y >> # CONFIG_HAVE_MONOTONIC_TIMER is not set >> CONFIG_HAVE_OPTION_TABLE=y >> # CONFIG_PIRQ_ROUTE is not set >> CONFIG_HAVE_SMI_HANDLER=y >> # CONFIG_PCI_IO_CFG_EXT is not set >> CONFIG_CACHE_ROM_SIZE=0x400000 >> CONFIG_USE_WATCHDOG_ON_BOOT=y >> # CONFIG_VGA is not set >> CONFIG_GFXUMA=y >> # CONFIG_RELOCATABLE_MODULES is not set >> CONFIG_HAVE_ACPI_TABLES=y >> >> # >> # System tables >> # >> CONFIG_MULTIBOOT=y >> CONFIG_GENERATE_ACPI_TABLES=y >> CONFIG_GENERATE_MP_TABLE=y >> # CONFIG_GENERATE_PIRQ_TABLE is not set >> CONFIG_GENERATE_SMBIOS_TABLES=y >> >> # >> # Payload >> # >> # CONFIG_PAYLOAD_NONE is not set >> # CONFIG_PAYLOAD_ELF is not set >> CONFIG_PAYLOAD_SEABIOS=y >> # CONFIG_PAYLOAD_FILO is not set >> # CONFIG_PAYLOAD_TIANOCORE is not set >> CONFIG_SEABIOS_STABLE=y >> # CONFIG_SEABIOS_MASTER is not set >> CONFIG_PAYLOAD_FILE="$(obj)/seabios/out/bios.bin.elf" >> # CONFIG_COMPRESSED_PAYLOAD_LZMA is not set >> # CONFIG_COMPRESSED_PAYLOAD_NRV2B is not set >> >> # >> # Debugging >> # >> # CONFIG_GDB_STUB is not set >> # CONFIG_DEBUG_CBFS is not set >> # CONFIG_HAVE_DEBUG_RAM_SETUP is not set >> # CONFIG_HAVE_DEBUG_CAR is not set >> # CONFIG_HAVE_DEBUG_SMBUS is not set >> # CONFIG_DEBUG_SMI is not set >> # CONFIG_DEBUG_SMM_RELOCATION is not set >> # CONFIG_DEBUG_MALLOC is not set >> # CONFIG_DEBUG_ACPI is not set >> # CONFIG_DEBUG_TPM is not set >> # CONFIG_DEBUG_SPI_FLASH is not set >> # CONFIG_DEBUG_INTEL_ME is not set >> # CONFIG_TRACE is not set >> # CONFIG_RAMINIT_SYSINFO is not set >> # CONFIG_ENABLE_APIC_EXT_ID is not set >> CONFIG_WARNINGS_ARE_ERRORS=y >> # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set >> # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set >> # CONFIG_POWER_BUTTON_FORCE_DISABLE is not set >> # CONFIG_POWER_BUTTON_IS_OPTIONAL is not set >> CONFIG_CHROMEOS=y >> >> # >> # ChromeOS >> # >> CONFIG_VBNV_OFFSET=0x26 >> CONFIG_VBNV_SIZE=0x10 >> # CONFIG_CHROMEOS_RAMOOPS is not set >> CONFIG_FLASHMAP_OFFSET=0x00610000 >> # CONFIG_VBOOT_VERIFY_FIRMWARE is not set >> # CONFIG_NO_TPM_RESUME is not set >> >>> -Aaron >>> >>> On Wed, Jul 24, 2013 at 6:30 AM, John Lewis <jlewis(a)johnlewis.ie> wrote: >>> >>>> Well, that didn't work, although the fan briefly span up, which I >>>> didn't notice before. I also tried building your beloved Parrot, and >>>> that is missing me.bin too. On 24/07/2013 11:26, John Lewis wrote: >>>> >>>>> I realise that this may well not work for reasons I don't understand, >>>>> but I have manually added the me.bin file to coreboot.rom using >>>>> cbfstool. Worth a try, I thought. On 24/07/2013 07:38, ron minnich >>>>> wrote: >>>>> >>>>>> On Tue, Jul 23, 2013 at 9:44 PM, Peter Stuge <peter(a)stuge.se >>>>>> [1][1]> wrote: >>>>>> >>>>>>> I guess eliminating that deployment/release process completely is >>>>>>> the reason to just always work directly upstream. >>>>>> >>>>>> well, that deploy/release process is not going to be eliminated. >>>>>> I'm just working on some ideas to make things better in the context >>>>>> of that process, which I think is doable. I'm just grateful John is >>>>>> a patient and reasonable guy :-) ron >>>> >>>> -- coreboot mailing list: coreboot(a)coreboot.org [2] >>>> http://www.coreboot.org/mailman/listinfo/coreboot [3]

1 0

Re: [coreboot] Samsung 550 Chromebook own Coreboot
by John Lewis 24 Jul '13

24 Jul '13

I realise that this may well not work for reasons I don't understand, but I have manually added the me.bin file to coreboot.rom using cbfstool. Worth a try, I thought. On 24/07/2013 07:38, ron minnich wrote: > On Tue, Jul 23, 2013 at 9:44 PM, Peter Stuge <peter(a)stuge.se> wrote: > >> I guess eliminating that deployment/release process completely is >> the >> reason to just always work directly upstream. > > well, that deploy/release process is not going to be eliminated. I'm > just working on some ideas to make things better in the context of > that process, which I think is doable. I'm just grateful John is a > patient and reasonable guy :-) > > ron

2 2

← Newer
1
2
3
4
5
6
7
8
...
11
Older →

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot July 2013