coreboot July 2013

coreboot@coreboot.org

45 participants
108 discussions

Re: [coreboot] [flashrom] Enabling Dediprog by default in flashrom
by Stefan Tauner 06 Jul '13

06 Jul '13

On Tue, 2 Jul 2013 00:12:28 -0300 Alexandre Pereira da Silva <aletes.xgr(a)gmail.com> wrote: > I think its safe to use a read opcode by default. > > The DediProg can't reach high clock rates, well below the limit for the > normal read on most memories. > > I have a DediProg available for testing. > > Thanks. The problem is not so much the frequency but the opcode used. We just don't know what DediProg does if a chip does not provide fast read support. You do not happen to have a logic analyser and a very old SPI flash chip w/o fast read support, do you? :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Jenkins: No space left on device
by Christoph Grenz 06 Jul '13

06 Jul '13

Hello, Jenkins currently seems to fail randomly on some patches (an example: [1]). The console output contains lots of "No space left on device" messages so the cause might just be a full hard drive. Could someone with console access to Jenkins check this? Thanks, Christoph [1] http://qa.coreboot.org/job/coreboot-gerrit/7143/console

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Gerrit: Please revert back to giving -1/+1 right to new users
by Paul Menzel 06 Jul '13

06 Jul '13

Dear coreboot folks, since the permission changes in Gerrit some months ago, we had to spent a lot of time in #coreboot on <irc.freenode.net> and in Gerrit to find out, that new Gerrit users could not vote with -1/+1 in Gerrit reviews. Most of the time, Patrick had to be contacted and he had to manually give the voting permission to the person. As I am not aware of any abuses of this right and as -1/+1 does not have a lot of impact in the current review process, it would be awesome if you could configure Gerrit to give -1/+1 to new users by default again. Thanks, Paul

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Re: [coreboot] ASUS m5a88-v AGESA port (bulldozer)
by David Hubbard 05 Jul '13

05 Jul '13

Hi Sebastian, On Thu, Jul 4, 2013 at 3:14 PM, Sebastian Parborg <darkdefende(a)gmail.com>wrote: > I've made some more progress in this matter. I got rid of more coreboot > log errors and warning messages. I also managed to get rid off most of the > warnings the linux kernel prints when it boots. > However it seems like the linux kernel can't mount the sata drives. It > fails with "ata1: softreset failed (1st FIS failed)" please look at the > attached logs for more info. > > I find it really strange that it fails because I can use grub2 to browse > the and read the sata drives without any problem. > > It seems like I'm really close in getting this to work so I would be > really happy if any of you guys could help me out. I don't know what I can > do to fix this. > > Just as a hint, please extract the ACPI DSDT tables when you boot with the vendor BIOS. The AHCI controller typically needs some special init steps which are stored there. David

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Re: [coreboot] What is the purpose of hard_reset function?
by Andrew Wu 05 Jul '13

05 Jul '13

I checked the datasheet and did some testing, Vortex86EX doesn't support cf9 port. And I found the "hard_reset" function is mostly called from vendor-dependent code. The only generic functions that call hard_reset are root_dev_reset in src/device/root_device.c and debug_init in src/drivers/generic/debug/debug_dev.c. For Vortex86EX, maybe hard_reset is not that important? 2013/7/5 ron minnich <rminnich(a)gmail.com>: > over time, we've found that not all boards implement hard reset in any > kind of standard way. In many cases, the cf9 reset works fine; on > other cases, a different sequence is needed. > > I have to ask a question for your question: how does your chipset > support hard reset? Via a write to cf9 or ... > > thanks! > > ron

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Re: [coreboot] What is the purpose of hard_reset function?
by Andrew Wu 05 Jul '13

05 Jul '13

Hi, Your Vortex86 is too old, its internal architecture is completely different with new Vortex86EX. So my port of coreboot won't work on it. :( To buy our product, it depends on which country you live. :) 2013/7/4 matti christensen <mattic(a)iki.fi> > > Hello > > i have a 200 mhz box w sis soc that looks like the box on > http://www.vortex86.com/index2.html - some guestions; > > --- do you think your port of coreboot might work on this previous brand also ? > --- where can i buy your board or whole box ? > > /mc > > On 7/4/13, Andrew Wu <andrewwu.tw(a)gmail.com> wrote: > > Hello, > > > > I am porting coreboot to our own product(Vortex86EX). I see there is a > > function called "hard_reset". Some boards implements this function, and > > some don't. Looks like each different mainboard has different > > implementation of hard_reset. > > > > Now I just wrote a blank hard_reset function, but maybe it is not right. > > > > So what is the purpose of this function? What should I put inside this > > function? To reset the system, why not just use system port(92h port)? > > > > > -- > ---keep-IT-simple---

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Re: [coreboot] ASUS m5a88-v AGESA port (bulldozer)
by darkdefende＠gmail.com 04 Jul '13

04 Jul '13

Idwer Vollering writes: > Done. Thanks for attaching the log for me. Some recent commits to coreboot master seems to have solved my problem with the pci scan hang. Now I don't have to hack around it any more. However it still freezes after it's done (?) loading seabios. I have uploaded my changes to https://github.com/DarkDefender/coreboot if anyone want's to look at them. I've tried to enable more debugging options in the "OptionsIds.h" for AGESA but it doesn't seem to do anything. The asserts are triggered druing boot are still the same as before. I've tried to look at it but I didn't really understand what I should change to solve them.

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Re: [coreboot] What is the purpose of hard_reset function?
by ron minnich 04 Jul '13

04 Jul '13

over time, we've found that not all boards implement hard reset in any kind of standard way. In many cases, the cf9 reset works fine; on other cases, a different sequence is needed. I have to ask a question for your question: how does your chipset support hard reset? Via a write to cf9 or ... thanks! ron

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Re: [coreboot] What is the purpose of hard_reset function?
by Myles Watson 04 Jul '13

04 Jul '13

I've seen it used for HyperTransport. HT settings survive a warm_reset, but not a hard_reset. I'm not sure if that's the only case, though. Thanks, Myles On Thu, Jul 4, 2013 at 1:23 PM, Andrew Wu <andrewwu.tw(a)gmail.com> wrote: > Hello, > > I am porting coreboot to our own product(Vortex86EX). I see there is a > function called "hard_reset". Some boards implements this function, and > some don't. Looks like each different mainboard has different > implementation of hard_reset. > > Now I just wrote a blank hard_reset function, but maybe it is not right. > > So what is the purpose of this function? What should I put inside this > function? To reset the system, why not just use system port(92h port)? > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] What is the purpose of hard_reset function?
by matti christensen 04 Jul '13

04 Jul '13

Hello i have a 200 mhz box w sis soc that looks like the box on http://www.vortex86.com/index2.html - some guestions; --- do you think your port of coreboot might work on this previous brand also ? --- where can i buy your board or whole box ? /mc On 7/4/13, Andrew Wu <andrewwu.tw(a)gmail.com> wrote: > Hello, > > I am porting coreboot to our own product(Vortex86EX). I see there is a > function called "hard_reset". Some boards implements this function, and > some don't. Looks like each different mainboard has different > implementation of hard_reset. > > Now I just wrote a blank hard_reset function, but maybe it is not right. > > So what is the purpose of this function? What should I put inside this > function? To reset the system, why not just use system port(92h port)? > -- ---keep-IT-simple---

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coreboot July 2013