coreboot February 2013

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Patch merged into coreboot/master: 1c270b1 armv7: update coreboot tables for armv7
by gerrit＠coreboot.org 09 Feb '13

09 Feb '13

the following patch was just integrated into master: commit 1c270b155863e48a2b2a6d855c6b7ea2f38ef8c6 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 8 18:02:31 2013 -0800 armv7: update coreboot tables for armv7 This is a first-pass attempt at cleaning up the coreboot tables for ARM. The most noticable difference is that there is no longer both a high and a low table. Change-Id: I5ba87ad57bf9a697b733511182c0326825071617 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2329 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Feb 9 03:22:17 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sat Feb 9 05:05:22 2013, giving +2 See http://review.coreboot.org/2329 for details. -gerrit

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Patch merged into coreboot/master: 896edc2 snow: do something useful in ramstage()
by gerrit＠coreboot.org 09 Feb '13

09 Feb '13

the following patch was just integrated into master: commit 896edc28af423cedbb6eab6d0a83c090e3fb2ef5 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 8 18:04:59 2013 -0800 snow: do something useful in ramstage() This cleans up Snow's trivial ramstage, gives it a coreboot table address and calls hardwaremain(). Change-Id: I84c904bcfd57a5f9eb3969de8a496f01e43bc2f6 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2328 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Feb 9 03:14:17 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sat Feb 9 05:03:29 2013, giving +2 See http://review.coreboot.org/2328 for details. -gerrit

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Patch merged into coreboot/master: b73d904 armv7/snow: add BL1_SIZE_KB and get rid of magic constants
by gerrit＠coreboot.org 09 Feb '13

09 Feb '13

the following patch was just integrated into master: commit b73d904cff574bb8447c75457a07353a81100ad5 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 8 19:10:33 2013 -0800 armv7/snow: add BL1_SIZE_KB and get rid of magic constants This adds a BL1_SIZE_KB config variable so that we can get rid of some magic constants. Change-Id: I9dbcfb407d3f8e367be5d943e95b032ce88b0ad0 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2332 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Feb 9 04:30:46 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sat Feb 9 05:01:31 2013, giving +2 See http://review.coreboot.org/2332 for details. -gerrit

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Patch merged into coreboot/master: 3001c5b armv7: include $(obj)/config.h when building bootblock
by gerrit＠coreboot.org 09 Feb '13

09 Feb '13

the following patch was just integrated into master: commit 3001c5b69c85414e8d762610794dd0dafc3c1813 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 8 19:09:04 2013 -0800 armv7: include $(obj)/config.h when building bootblock Explicitly including it allows us to get rid of some magic constants in the bootblock linker script. Change-Id: I095899babc997addce6b383f00e5ebf135e99d5e Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2331 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Feb 9 04:22:13 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sat Feb 9 05:00:58 2013, giving +2 See http://review.coreboot.org/2331 for details. -gerrit

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New patch to review for coreboot: 335101f armv7/snow: add BL1_SIZE_KB and get rid of magic constants
by David Hendricks 09 Feb '13

09 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2332 -gerrit commit 335101f9e6b9252c1ea66065fdcc58547643a956 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 8 19:10:33 2013 -0800 armv7/snow: add BL1_SIZE_KB and get rid of magic constants This adds a BL1_SIZE_KB config variable so that we can get rid of some magic constants. Change-Id: I9dbcfb407d3f8e367be5d943e95b032ce88b0ad0 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/bootblock.inc | 2 +- src/arch/armv7/bootblock.lds | 2 +- src/cpu/samsung/exynos5250/Kconfig | 4 ++++ 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc index 1eb8e11..82d801e 100644 --- a/src/arch/armv7/bootblock.inc +++ b/src/arch/armv7/bootblock.inc @@ -36,7 +36,7 @@ _bl1: * on ARM, which is 8KB in size and it is prepended to the * reset vector */ - .skip 8192 + .skip CONFIG_BL1_SIZE_KB .globl _start _start: b reset diff --git a/src/arch/armv7/bootblock.lds b/src/arch/armv7/bootblock.lds index 90e37a0..fc58601 100644 --- a/src/arch/armv7/bootblock.lds +++ b/src/arch/armv7/bootblock.lds @@ -25,7 +25,7 @@ OUTPUT_ARCH(arm) TARGET(binary) SECTIONS { - ROMLOC = 0x2023400 - 8192; + ROMLOC = CONFIG_BOOTBLOCK_BASE - CONFIG_BL1_SIZE_KB; /* This section might be better named .setup */ .rom ROMLOC : { diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 0b07b90..3e61087 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -14,6 +14,10 @@ config SATA_AHCI bool default n +config BL1_SIZE_KB + int + default 8192 + # Example SRAM/iRAM map for Exynos5250 platform: # # 0x0202_0000: vendor-provided BL1

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New patch to review for coreboot: 02ceb90 armv7: include $(obj)/config.h when building bootblock
by David Hendricks 09 Feb '13

09 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2331 -gerrit commit 02ceb90004009b5d0a2ff054bcf649e9a12424f8 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 8 19:09:04 2013 -0800 armv7: include $(obj)/config.h when building bootblock Explicitly including it allows us to get rid of some magic constants in the bootblock linker script. Change-Id: I095899babc997addce6b383f00e5ebf135e99d5e Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/Makefile.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 0471b94..2c5d8c6 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -239,9 +239,9 @@ $(objgenerated)/bootblock.inc: $(src)/arch/armv7/$(subst ",,$(CONFIG_BOOTBLOCK_S $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld $$(bootblock-objs) $(stages) @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -m armelf_linux_eabi -static -o $@.tmp -L$(obj) $< -T $(objgenerated)/bootblock.ld + $(LD) -m armelf_linux_eabi -include $(obj)/config.h -static -o $@.tmp -L$(obj) $< -T $(objgenerated)/bootblock.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld -Wl,--start-group $(objgenerated)/bootblock.o $(bootblock-objs) $(stages) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -nostartfiles -include $(obj)/config.h -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld -Wl,--start-group $(objgenerated)/bootblock.o $(bootblock-objs) $(stages) $(LIBGCC_FILE_NAME) -Wl,--end-group endif ################################################################################

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New patch to review for coreboot: 248125b cbfstool: Fix crash on image without bootblock in end of ROM.
by Hung-Te Lin 09 Feb '13

09 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2330 -gerrit commit 248125b58607192f493eb1c4ce3ccb968d029f73 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Sat Feb 9 10:38:55 2013 +0800 cbfstool: Fix crash on image without bootblock in end of ROM. On platforms with CBFS data filling end of ROM image without bootblock in the end (ex, ARM), calculation of "next valid entry" may exceed ROM image buffer in memory and raise segmentation fault when we try to compare its magic value. To fix this, always check if the entry address is inside ROM image buffer. Verified to build and boot successfully on qemu/x86 and armv7/snow. Change-Id: I117d6767a5403be636eea2b23be1dcf2e1c88839 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- util/cbfstool/cbfs_image.c | 26 +++++++++++++++----------- util/cbfstool/cbfs_image.h | 2 +- 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 5c2ac26..2cdbf23 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -112,7 +112,7 @@ static int cbfs_fix_legacy_size(struct cbfs_image *image) { struct cbfs_file *entry, *first = NULL, *last = NULL; for (first = entry = cbfs_find_first_entry(image); - entry && cbfs_is_valid_entry(entry); + entry && cbfs_is_valid_entry(image, entry); entry = cbfs_find_next_entry(image, entry)) { last = entry; } @@ -352,7 +352,7 @@ int cbfs_add_entry(struct cbfs_image *image, struct buffer *buffer, cbfs_walk(image, cbfs_merge_empty_entry, NULL); for (entry = cbfs_find_first_entry(image); - entry && cbfs_is_valid_entry(entry); + entry && cbfs_is_valid_entry(image, entry); entry = cbfs_find_next_entry(image, entry)) { entry_type = ntohl(entry->type); @@ -429,7 +429,7 @@ int cbfs_add_entry(struct cbfs_image *image, struct buffer *buffer, struct cbfs_file *cbfs_get_entry(struct cbfs_image *image, const char *name) { struct cbfs_file *entry; for (entry = cbfs_find_first_entry(image); - entry && cbfs_is_valid_entry(entry); + entry && cbfs_is_valid_entry(image, entry); entry = cbfs_find_next_entry(image, entry)) { if (strcasecmp(CBFS_NAME(entry), name) == 0) { DEBUG("cbfs_get_entry: found %s\n", name); @@ -574,7 +574,7 @@ int cbfs_print_entry_info(struct cbfs_image *image, struct cbfs_file *entry, struct cbfs_payload_segment *payload; FILE *fp = (FILE *)arg; - if (!cbfs_is_valid_entry(entry)) { + if (!cbfs_is_valid_entry(image, entry)) { ERROR("cbfs_print_entry_info: Invalid entry at 0x%x\n", cbfs_get_entry_addr(image, entry)); return -1; @@ -643,7 +643,7 @@ int cbfs_merge_empty_entry(struct cbfs_image *image, struct cbfs_file *entry, next = cbfs_find_next_entry(image, entry); - while (next && cbfs_is_valid_entry(next)) { + while (next && cbfs_is_valid_entry(image, next)) { type = ntohl(next->type); if (type == CBFS_COMPONENT_DELETED) { type = CBFS_COMPONENT_NULL; @@ -675,7 +675,7 @@ int cbfs_walk(struct cbfs_image *image, cbfs_entry_callback callback, int count = 0; struct cbfs_file *entry; for (entry = cbfs_find_first_entry(image); - entry && cbfs_is_valid_entry(entry); + entry && cbfs_is_valid_entry(image, entry); entry = cbfs_find_next_entry(image, entry)) { count ++; if (callback(image, entry, arg) != 0) @@ -730,7 +730,7 @@ struct cbfs_file *cbfs_find_next_entry(struct cbfs_image *image, struct cbfs_file *entry) { uint32_t addr = cbfs_get_entry_addr(image, entry); int align = ntohl(image->header->align); - assert(entry && cbfs_is_valid_entry(entry)); + assert(entry && cbfs_is_valid_entry(image, entry)); addr += ntohl(entry->offset) + ntohl(entry->len); addr = align_up(addr, align); return (struct cbfs_file *)(image->buffer.data + addr); @@ -741,9 +741,13 @@ uint32_t cbfs_get_entry_addr(struct cbfs_image *image, struct cbfs_file *entry) return (int32_t)((char *)entry - image->buffer.data); } -int cbfs_is_valid_entry(struct cbfs_file *entry) { - return (entry &&memcmp(entry->magic, CBFS_FILE_MAGIC, - sizeof(entry->magic)) == 0); +int cbfs_is_valid_entry(struct cbfs_image *image, struct cbfs_file *entry) { + return (entry && + (char *)entry >= image->buffer.data && + (char *)entry + sizeof(entry->magic) < + image->buffer.data + image->buffer.size && + memcmp(entry->magic, CBFS_FILE_MAGIC, + sizeof(entry->magic)) == 0); } int cbfs_init_entry(struct cbfs_file *entry, @@ -818,7 +822,7 @@ int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name, * by ELF loader and positioned by cbfs_add_entry. */ for (entry = cbfs_find_first_entry(image); - entry && cbfs_is_valid_entry(entry); + entry && cbfs_is_valid_entry(image, entry); entry = cbfs_find_next_entry(image, entry)) { uint32_t type = ntohl(entry->type); diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index 676efde..57bbfa1 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -114,7 +114,7 @@ struct cbfs_file *cbfs_find_next_entry(struct cbfs_image *image, uint32_t cbfs_get_entry_addr(struct cbfs_image *image, struct cbfs_file *entry); /* Returns 1 if entry has valid data (by checking magic number), otherwise 0. */ -int cbfs_is_valid_entry(struct cbfs_file *entry); +int cbfs_is_valid_entry(struct cbfs_image *image, struct cbfs_file *entry); /* Print CBFS component information. */ int cbfs_print_directory(struct cbfs_image *image);

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New patch to review for coreboot: d365ad8 armv7: update coreboot tables for armv7
by David Hendricks 09 Feb '13

09 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2329 -gerrit commit d365ad8d4fbd5952cac855588140499efa3fb59e Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 8 18:02:31 2013 -0800 armv7: update coreboot tables for armv7 This is a first-pass attempt at cleaning up the coreboot tables for ARM. The most noticable difference is that there is no longer both a high and a low table. Change-Id: I5ba87ad57bf9a697b733511182c0326825071617 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/boot/coreboot_table.c | 81 +++++++++++++-------------- src/arch/armv7/boot/tables.c | 60 ++++++-------------- src/arch/armv7/include/arch/coreboot_tables.h | 5 +- 3 files changed, 61 insertions(+), 85 deletions(-) diff --git a/src/arch/armv7/boot/coreboot_table.c b/src/arch/armv7/boot/coreboot_table.c index b2d88aa..ed105a4 100644 --- a/src/arch/armv7/boot/coreboot_table.c +++ b/src/arch/armv7/boot/coreboot_table.c @@ -559,11 +559,13 @@ struct lb_memory *get_lb_mem(void) return mem_ranges; } +#if 0 static void build_lb_mem_range(void *gp, struct device *dev, struct resource *res) { struct lb_memory *mem = gp; new_lb_memory_range(mem, LB_MEM_RAM, res->base, res->size); } +#endif static struct lb_memory *build_lb_mem(struct lb_header *head) { @@ -573,11 +575,15 @@ static struct lb_memory *build_lb_mem(struct lb_header *head) mem = lb_memory(head); mem_ranges = mem; + /* FIXME: implement this */ +#if 0 /* Build the raw table of memory */ search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, build_lb_mem_range, mem); - lb_cleanup_memory_ranges(mem); +#endif + /* FIXME: things die in cleanup_memory_ranges(), skip for now */ +// lb_cleanup_memory_ranges(mem); return mem; } @@ -596,47 +602,27 @@ static void add_lb_reserved(struct lb_memory *mem) } unsigned long write_coreboot_table( - unsigned long low_table_start, unsigned long low_table_end, - unsigned long rom_table_start, unsigned long rom_table_end) + unsigned long table_start, unsigned long table_end) { struct lb_header *head; struct lb_memory *mem; + unsigned long fini; -#if CONFIG_WRITE_HIGH_TABLES - printk(BIOS_DEBUG, "Writing high table forward entry at 0x%08lx\n", - low_table_end); - head = lb_table_init(low_table_end); - lb_forward(head, (struct lb_header*)rom_table_end); - - low_table_end = (unsigned long) lb_table_fini(head, 0); - printk(BIOS_DEBUG, "New low_table_end: 0x%08lx\n", low_table_end); - printk(BIOS_DEBUG, "Now going to write high coreboot table at 0x%08lx\n", - rom_table_end); - - head = lb_table_init(rom_table_end); - rom_table_end = (unsigned long)head; - printk(BIOS_DEBUG, "rom_table_end = 0x%08lx\n", rom_table_end); -#else - if(low_table_end > (0x1000 - sizeof(struct lb_header))) { /* after 4K */ - /* We need to put lbtable on to [0xf0000,0x100000) */ - head = lb_table_init(rom_table_end); - rom_table_end = (unsigned long)head; - } else { - head = lb_table_init(low_table_end); - low_table_end = (unsigned long)head; - } -#endif + printk(BIOS_DEBUG, "table_start: 0x%lx, table_end: 0x%lx\n", + table_start, table_end); + head = lb_table_init(table_start); + + printk(BIOS_DEBUG, "Writing table forward entry at 0x%08lx\n", + table_end); + lb_forward(head, (struct lb_header*)table_end); - printk(BIOS_DEBUG, "Adjust low_table_end from 0x%08lx to ", low_table_end); - low_table_end += 0xfff; // 4K aligned - low_table_end &= ~0xfff; - printk(BIOS_DEBUG, "0x%08lx \n", low_table_end); + table_end = (unsigned long) head + head->table_bytes; - /* The Linux kernel assumes this region is reserved */ - printk(BIOS_DEBUG, "Adjust rom_table_end from 0x%08lx to ", rom_table_end); - rom_table_end += 0xffff; // 64K align - rom_table_end &= ~0xffff; - printk(BIOS_DEBUG, "0x%08lx \n", rom_table_end); + /* FIXME(dhendrix): do we need this? */ + printk(BIOS_DEBUG, "Adjust table_end from 0x%08lx to ", table_end); + table_end += 0xfff; // 4K aligned + table_end &= ~0xfff; + printk(BIOS_DEBUG, "0x%08lx \n", table_end); #if CONFIG_USE_OPTION_TABLE { @@ -655,21 +641,29 @@ unsigned long write_coreboot_table( } #endif /* Record where RAM is located */ + /* FIXME(dhendrix): add global resources */ + printk(BIOS_DEBUG, "%s: head: 0x%p\n", __func__, head); mem = build_lb_mem(head); + /* FIXME: we seem to get a bogus return value */ + printk(BIOS_DEBUG, "%s: mem: 0x%p\n", __func__, mem); + if ((unsigned long)mem < CONFIG_RAMBASE) { + printk(BIOS_DEBUG, "%s: mem < CONFIG_RAMBASE\n" , __func__); + while (1); + } /* Record the mptable and the the lb_table (This will be adjusted later) */ lb_add_memory_range(mem, LB_MEM_TABLE, - low_table_start, low_table_end - low_table_start); + table_start, table_end - table_start); /* Record the pirq table, acpi tables, and maybe the mptable */ lb_add_memory_range(mem, LB_MEM_TABLE, - rom_table_start, rom_table_end-rom_table_start); + table_start, table_end - table_start); #if CONFIG_WRITE_HIGH_TABLES printk(BIOS_DEBUG, "Adding high table area\n"); // should this be LB_MEM_ACPI? lb_add_memory_range(mem, LB_MEM_TABLE, - high_tables_base, high_tables_size); + table_start, table_end - table_start); #endif /* Add reserved regions */ @@ -679,11 +673,12 @@ unsigned long write_coreboot_table( /* Note: * I assume that there is always memory at immediately after - * the low_table_end. This means that after I setup the coreboot table. + * the table_end. This means that after I setup the coreboot table. * I can trivially fixup the reserved memory ranges to hold the correct * size of the coreboot table. */ + /* FIXME(dhendrix): Most of these do nothing at the moment */ /* Record our motherboard */ lb_mainboard(head); /* Record the serial port, if present */ @@ -695,6 +690,7 @@ unsigned long write_coreboot_table( /* Record our framebuffer */ lb_framebuffer(head); +#if 0 #if CONFIG_CHROMEOS /* Record our GPIO settings (ChromeOS specific) */ lb_gpios(head); @@ -705,9 +701,12 @@ unsigned long write_coreboot_table( /* pass along VBNV offsets in CMOS */ lb_vbnv(head); #endif +#endif add_cbmem_pointers(head); /* Remember where my valid memory ranges are */ - return lb_table_fini(head, 1); + fini = lb_table_fini(head, 1); + printk(BIOS_DEBUG, "%s: DONE: fini is 0x%lx\n", __func__, fini); + return fini; } diff --git a/src/arch/armv7/boot/tables.c b/src/arch/armv7/boot/tables.c index 07c5635..813eaea 100644 --- a/src/arch/armv7/boot/tables.c +++ b/src/arch/armv7/boot/tables.c @@ -28,6 +28,10 @@ #include <cbmem.h> #include <lib.h> +/* + * TODO: "High" tables are a convention used on x86. Maybe we can + * clean up that naming at some point. + */ uint64_t high_tables_base = 0; uint64_t high_tables_size; @@ -37,58 +41,30 @@ void cbmem_arch_init(void) struct lb_memory *write_tables(void) { - unsigned long low_table_start, low_table_end; - unsigned long rom_table_start, rom_table_end; - - /* Even if high tables are configured, some tables are copied both to - * the low and the high area, so payloads and OSes don't need to know - * about the high tables. - */ - unsigned long high_table_pointer; + unsigned long table_pointer; if (!high_tables_base) { - printk(BIOS_ERR, "ERROR: High Tables Base is not set.\n"); + printk(BIOS_ERR, "ERROR: coreboot_tables_base is not set.\n"); // Are there any boards without? // Stepan thinks we should die() here! } - printk(BIOS_DEBUG, "High Tables Base is %llx.\n", high_tables_base); - - rom_table_start = 0xf0000; - rom_table_end = 0xf0000; - - /* Start low addr at 0x500, so we don't run into conflicts with the BDA - * in case our data structures grow beyound 0x400. Only multiboot, GDT - * and the coreboot table use low_tables. - */ - low_table_start = 0; - low_table_end = 0x500; + printk(BIOS_DEBUG, "high_tables_base: %llx.\n", high_tables_base); -#define MAX_COREBOOT_TABLE_SIZE (8 * 1024) post_code(0x9d); - high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, MAX_COREBOOT_TABLE_SIZE); - - if (high_table_pointer) { - unsigned long new_high_table_pointer; - - /* Also put a forwarder entry into 0-4K */ - new_high_table_pointer = write_coreboot_table(low_table_start, low_table_end, - high_tables_base, high_table_pointer); - - if (new_high_table_pointer > (high_table_pointer + - MAX_COREBOOT_TABLE_SIZE)) + table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, + MAX_COREBOOT_TABLE_SIZE); + if (table_pointer) { + unsigned long new_table_pointer; + new_table_pointer = write_coreboot_table(table_pointer, + high_tables_size); + if (table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) { printk(BIOS_ERR, "%s: coreboot table didn't fit (%lx)\n", - __func__, new_high_table_pointer - - high_table_pointer); - - printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", - new_high_table_pointer - high_table_pointer); - } else { - /* The coreboot table must be in 0-4K or 960K-1M */ - rom_table_end = write_coreboot_table( - low_table_start, low_table_end, - rom_table_start, rom_table_end); + __func__, new_table_pointer - table_pointer); + } + printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", + new_table_pointer - table_pointer); } post_code(0x9e); diff --git a/src/arch/armv7/include/arch/coreboot_tables.h b/src/arch/armv7/include/arch/coreboot_tables.h index 3c9bf98..ab20866 100644 --- a/src/arch/armv7/include/arch/coreboot_tables.h +++ b/src/arch/armv7/include/arch/coreboot_tables.h @@ -3,10 +3,11 @@ #include <boot/coreboot_tables.h> +#define MAX_COREBOOT_TABLE_SIZE (8 * 1024) + /* This file holds function prototypes for building the coreboot table. */ unsigned long write_coreboot_table( - unsigned long low_table_start, unsigned long low_table_end, - unsigned long rom_table_start, unsigned long rom_table_end); + unsigned long table_start, unsigned long table_end); void lb_memory_range(struct lb_memory *mem, uint32_t type, uint64_t start, uint64_t size);

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New patch to review for coreboot: f834070 snow: do something useful in ramstage()
by David Hendricks 09 Feb '13

09 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2328 -gerrit commit f834070d554e3558292183874aca559fd4b3a6e5 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 8 18:04:59 2013 -0800 snow: do something useful in ramstage() This cleans up Snow's trivial ramstage, gives it a coreboot table address and calls hardwaremain(). Change-Id: I84c904bcfd57a5f9eb3969de8a496f01e43bc2f6 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/snow/ramstage.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index f9d9c96..d280dbe 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -19,12 +19,21 @@ #include <console/console.h> +#if CONFIG_WRITE_HIGH_TABLES +#include <cbmem.h> +#endif + +void hardwaremain(int boot_complete); void main(void) { -// volatile unsigned long *pshold = (unsigned long *)0x1004330c; -// *pshold &= ~0x100; /* shut down */ - console_init(); printk(BIOS_INFO, "hello from ramstage\n"); - while (1); + +#if CONFIG_WRITE_HIGH_TABLES + /* Leave some space for ACPI tables */ + high_tables_base = CONFIG_RAMBASE; + high_tables_size = CONFIG_RAMBASE + 0x100000; +#endif + + hardwaremain(0); }

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Patch set updated for coreboot: 40bcc8f snow: cleanup ramstage and call hardwaremain()
by David Hendricks 09 Feb '13

09 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2302 -gerrit commit 40bcc8f0e13d8ce26edb90095c663026f77d12d7 Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Feb 6 16:29:42 2013 -0800 snow: cleanup ramstage and call hardwaremain() ** do not submit (work-in-progress) ** It *no longer* dies in write_coreboot_tables(). The trick is that lb_table_fini is more than informational, it writes a record and hence can not be called before any other record has been written, or it writes garbage. Oops. That's a problem with the original too: it assumes at least one record written, which is safe, because there's always one record written. Hence one can not call lb_table_fini just to ask a question. It can only be called once. Note 1: For ARM we can get away with only using one table, the high table and low table distinction is an x86-ism. Note 2: We'll eventually need to fill in the device structure so that search_global_resources() can mark regions appropriately. Fortunately we can get by with the assumption that 0x4000_0000- 0xffff_ffff is plain memory without any IO holes (We'll probably want to specify which regions are IO later on). Change-Id: I30200432535244de971a7cea9f7902f5e9b46403 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/boot/coreboot_table.c | 81 +++++++++++++-------------- src/arch/armv7/boot/tables.c | 59 ++++++++----------- src/arch/armv7/include/arch/coreboot_tables.h | 3 +- src/lib/compute_ip_checksum.c | 2 + src/lib/hardwaremain.c | 4 +- src/mainboard/google/snow/ramstage.c | 17 ++++-- 6 files changed, 81 insertions(+), 85 deletions(-) diff --git a/src/arch/armv7/boot/coreboot_table.c b/src/arch/armv7/boot/coreboot_table.c index b2d88aa..ed105a4 100644 --- a/src/arch/armv7/boot/coreboot_table.c +++ b/src/arch/armv7/boot/coreboot_table.c @@ -559,11 +559,13 @@ struct lb_memory *get_lb_mem(void) return mem_ranges; } +#if 0 static void build_lb_mem_range(void *gp, struct device *dev, struct resource *res) { struct lb_memory *mem = gp; new_lb_memory_range(mem, LB_MEM_RAM, res->base, res->size); } +#endif static struct lb_memory *build_lb_mem(struct lb_header *head) { @@ -573,11 +575,15 @@ static struct lb_memory *build_lb_mem(struct lb_header *head) mem = lb_memory(head); mem_ranges = mem; + /* FIXME: implement this */ +#if 0 /* Build the raw table of memory */ search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, build_lb_mem_range, mem); - lb_cleanup_memory_ranges(mem); +#endif + /* FIXME: things die in cleanup_memory_ranges(), skip for now */ +// lb_cleanup_memory_ranges(mem); return mem; } @@ -596,47 +602,27 @@ static void add_lb_reserved(struct lb_memory *mem) } unsigned long write_coreboot_table( - unsigned long low_table_start, unsigned long low_table_end, - unsigned long rom_table_start, unsigned long rom_table_end) + unsigned long table_start, unsigned long table_end) { struct lb_header *head; struct lb_memory *mem; + unsigned long fini; -#if CONFIG_WRITE_HIGH_TABLES - printk(BIOS_DEBUG, "Writing high table forward entry at 0x%08lx\n", - low_table_end); - head = lb_table_init(low_table_end); - lb_forward(head, (struct lb_header*)rom_table_end); - - low_table_end = (unsigned long) lb_table_fini(head, 0); - printk(BIOS_DEBUG, "New low_table_end: 0x%08lx\n", low_table_end); - printk(BIOS_DEBUG, "Now going to write high coreboot table at 0x%08lx\n", - rom_table_end); - - head = lb_table_init(rom_table_end); - rom_table_end = (unsigned long)head; - printk(BIOS_DEBUG, "rom_table_end = 0x%08lx\n", rom_table_end); -#else - if(low_table_end > (0x1000 - sizeof(struct lb_header))) { /* after 4K */ - /* We need to put lbtable on to [0xf0000,0x100000) */ - head = lb_table_init(rom_table_end); - rom_table_end = (unsigned long)head; - } else { - head = lb_table_init(low_table_end); - low_table_end = (unsigned long)head; - } -#endif + printk(BIOS_DEBUG, "table_start: 0x%lx, table_end: 0x%lx\n", + table_start, table_end); + head = lb_table_init(table_start); + + printk(BIOS_DEBUG, "Writing table forward entry at 0x%08lx\n", + table_end); + lb_forward(head, (struct lb_header*)table_end); - printk(BIOS_DEBUG, "Adjust low_table_end from 0x%08lx to ", low_table_end); - low_table_end += 0xfff; // 4K aligned - low_table_end &= ~0xfff; - printk(BIOS_DEBUG, "0x%08lx \n", low_table_end); + table_end = (unsigned long) head + head->table_bytes; - /* The Linux kernel assumes this region is reserved */ - printk(BIOS_DEBUG, "Adjust rom_table_end from 0x%08lx to ", rom_table_end); - rom_table_end += 0xffff; // 64K align - rom_table_end &= ~0xffff; - printk(BIOS_DEBUG, "0x%08lx \n", rom_table_end); + /* FIXME(dhendrix): do we need this? */ + printk(BIOS_DEBUG, "Adjust table_end from 0x%08lx to ", table_end); + table_end += 0xfff; // 4K aligned + table_end &= ~0xfff; + printk(BIOS_DEBUG, "0x%08lx \n", table_end); #if CONFIG_USE_OPTION_TABLE { @@ -655,21 +641,29 @@ unsigned long write_coreboot_table( } #endif /* Record where RAM is located */ + /* FIXME(dhendrix): add global resources */ + printk(BIOS_DEBUG, "%s: head: 0x%p\n", __func__, head); mem = build_lb_mem(head); + /* FIXME: we seem to get a bogus return value */ + printk(BIOS_DEBUG, "%s: mem: 0x%p\n", __func__, mem); + if ((unsigned long)mem < CONFIG_RAMBASE) { + printk(BIOS_DEBUG, "%s: mem < CONFIG_RAMBASE\n" , __func__); + while (1); + } /* Record the mptable and the the lb_table (This will be adjusted later) */ lb_add_memory_range(mem, LB_MEM_TABLE, - low_table_start, low_table_end - low_table_start); + table_start, table_end - table_start); /* Record the pirq table, acpi tables, and maybe the mptable */ lb_add_memory_range(mem, LB_MEM_TABLE, - rom_table_start, rom_table_end-rom_table_start); + table_start, table_end - table_start); #if CONFIG_WRITE_HIGH_TABLES printk(BIOS_DEBUG, "Adding high table area\n"); // should this be LB_MEM_ACPI? lb_add_memory_range(mem, LB_MEM_TABLE, - high_tables_base, high_tables_size); + table_start, table_end - table_start); #endif /* Add reserved regions */ @@ -679,11 +673,12 @@ unsigned long write_coreboot_table( /* Note: * I assume that there is always memory at immediately after - * the low_table_end. This means that after I setup the coreboot table. + * the table_end. This means that after I setup the coreboot table. * I can trivially fixup the reserved memory ranges to hold the correct * size of the coreboot table. */ + /* FIXME(dhendrix): Most of these do nothing at the moment */ /* Record our motherboard */ lb_mainboard(head); /* Record the serial port, if present */ @@ -695,6 +690,7 @@ unsigned long write_coreboot_table( /* Record our framebuffer */ lb_framebuffer(head); +#if 0 #if CONFIG_CHROMEOS /* Record our GPIO settings (ChromeOS specific) */ lb_gpios(head); @@ -705,9 +701,12 @@ unsigned long write_coreboot_table( /* pass along VBNV offsets in CMOS */ lb_vbnv(head); #endif +#endif add_cbmem_pointers(head); /* Remember where my valid memory ranges are */ - return lb_table_fini(head, 1); + fini = lb_table_fini(head, 1); + printk(BIOS_DEBUG, "%s: DONE: fini is 0x%lx\n", __func__, fini); + return fini; } diff --git a/src/arch/armv7/boot/tables.c b/src/arch/armv7/boot/tables.c index 07c5635..a60ebca 100644 --- a/src/arch/armv7/boot/tables.c +++ b/src/arch/armv7/boot/tables.c @@ -28,6 +28,10 @@ #include <cbmem.h> #include <lib.h> +/* + * TODO: "High" tables are a convention used on x86. Maybe we can + * clean up that naming at some point. + */ uint64_t high_tables_base = 0; uint64_t high_tables_size; @@ -37,59 +41,40 @@ void cbmem_arch_init(void) struct lb_memory *write_tables(void) { - unsigned long low_table_start, low_table_end; - unsigned long rom_table_start, rom_table_end; - - /* Even if high tables are configured, some tables are copied both to - * the low and the high area, so payloads and OSes don't need to know - * about the high tables. - */ - unsigned long high_table_pointer; + unsigned long table_pointer; if (!high_tables_base) { - printk(BIOS_ERR, "ERROR: High Tables Base is not set.\n"); + printk(BIOS_ERR, "ERROR: coreboot_tables_base is not set.\n"); // Are there any boards without? // Stepan thinks we should die() here! } - printk(BIOS_DEBUG, "High Tables Base is %llx.\n", high_tables_base); - - rom_table_start = 0xf0000; - rom_table_end = 0xf0000; - - /* Start low addr at 0x500, so we don't run into conflicts with the BDA - * in case our data structures grow beyound 0x400. Only multiboot, GDT - * and the coreboot table use low_tables. - */ - low_table_start = 0; - low_table_end = 0x500; + printk(BIOS_DEBUG, "high_tables_base: %llx.\n", high_tables_base); #define MAX_COREBOOT_TABLE_SIZE (8 * 1024) post_code(0x9d); - high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, MAX_COREBOOT_TABLE_SIZE); - - if (high_table_pointer) { - unsigned long new_high_table_pointer; - - /* Also put a forwarder entry into 0-4K */ - new_high_table_pointer = write_coreboot_table(low_table_start, low_table_end, - high_tables_base, high_table_pointer); - - if (new_high_table_pointer > (high_table_pointer + - MAX_COREBOOT_TABLE_SIZE)) + table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, + MAX_COREBOOT_TABLE_SIZE); + if (table_pointer) { + unsigned long new_table_pointer; + new_table_pointer = write_coreboot_table(table_pointer, + high_tables_size); + if (table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) { printk(BIOS_ERR, "%s: coreboot table didn't fit (%lx)\n", - __func__, new_high_table_pointer - - high_table_pointer); - - printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", - new_high_table_pointer - high_table_pointer); - } else { + __func__, new_table_pointer - table_pointer); + } + printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", + new_table_pointer - table_pointer); + } +#if 0 + else { /* The coreboot table must be in 0-4K or 960K-1M */ rom_table_end = write_coreboot_table( low_table_start, low_table_end, rom_table_start, rom_table_end); } +#endif post_code(0x9e); diff --git a/src/arch/armv7/include/arch/coreboot_tables.h b/src/arch/armv7/include/arch/coreboot_tables.h index 3c9bf98..e8bb7be 100644 --- a/src/arch/armv7/include/arch/coreboot_tables.h +++ b/src/arch/armv7/include/arch/coreboot_tables.h @@ -5,8 +5,7 @@ /* This file holds function prototypes for building the coreboot table. */ unsigned long write_coreboot_table( - unsigned long low_table_start, unsigned long low_table_end, - unsigned long rom_table_start, unsigned long rom_table_end); + unsigned long table_start, unsigned long table_end); void lb_memory_range(struct lb_memory *mem, uint32_t type, uint64_t start, uint64_t size); diff --git a/src/lib/compute_ip_checksum.c b/src/lib/compute_ip_checksum.c index 48f93d4..8526f6d 100644 --- a/src/lib/compute_ip_checksum.c +++ b/src/lib/compute_ip_checksum.c @@ -1,6 +1,8 @@ #include <stdint.h> #include <ip_checksum.h> +#include <console/console.h> + unsigned long compute_ip_checksum(void *addr, unsigned long length) { uint8_t *ptr; diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 85c05f5..c0822d6 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -114,7 +114,7 @@ void hardwaremain(int boot_complete) timestamp_stash(TS_DEVICE_DONE); #if CONFIG_WRITE_HIGH_TABLES - cbmem_initialize(); + int rc = cbmem_initialize(); #if CONFIG_CONSOLE_CBMEM cbmemc_reinit(); #endif @@ -142,11 +142,13 @@ void hardwaremain(int boot_complete) timestamp_add_now(TS_LOAD_PAYLOAD); + printk(BIOS_DEBUG, "%s: finding payload\n", __func__); payload = cbfs_load_payload(CBFS_DEFAULT_MEDIA, CONFIG_CBFS_PREFIX "/payload"); if (! payload) die("Could not find a payload\n"); + printk(BIOS_DEBUG, "%s: found payload, running selfboot\n", __func__); selfboot(lb_mem, payload); printk(BIOS_EMERG, "Boot failed"); } diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index f9d9c96..d280dbe 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -19,12 +19,21 @@ #include <console/console.h> +#if CONFIG_WRITE_HIGH_TABLES +#include <cbmem.h> +#endif + +void hardwaremain(int boot_complete); void main(void) { -// volatile unsigned long *pshold = (unsigned long *)0x1004330c; -// *pshold &= ~0x100; /* shut down */ - console_init(); printk(BIOS_INFO, "hello from ramstage\n"); - while (1); + +#if CONFIG_WRITE_HIGH_TABLES + /* Leave some space for ACPI tables */ + high_tables_base = CONFIG_RAMBASE; + high_tables_size = CONFIG_RAMBASE + 0x100000; +#endif + + hardwaremain(0); }

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coreboot February 2013