coreboot February 2013

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Patch set updated for coreboot: b47e003 speedstep: Deduplicate some MSR identifiers
by Patrick Georgi 09 Feb '13

09 Feb '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2337 -gerrit commit b47e003fa2b64ed027452e2722fc1390ecf4bfba Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Feb 9 15:35:30 2013 +0100 speedstep: Deduplicate some MSR identifiers In particular: MSR_PMG_CST_CONFIG_CONTROL MSR_PMG_IO_BASE_ADDR MSR_PMG_IO_CAPTURE_ADDR Change-Id: Ief2697312f0edf8c45f7d3550a7bedaff1b69dc6 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/cpu/intel/model_1067x/model_1067x_init.c | 15 ++++++--------- src/cpu/intel/model_106cx/model_106cx_init.c | 12 ++++-------- src/cpu/intel/model_206ax/finalize.c | 1 + src/cpu/intel/model_206ax/model_206ax.h | 2 -- src/cpu/intel/model_206ax/model_206ax_init.c | 4 ++-- src/cpu/intel/model_6ex/model_6ex_init.c | 12 ++++-------- src/cpu/intel/model_6fx/model_6fx_init.c | 12 ++++-------- src/include/cpu/intel/speedstep.h | 3 +++ 8 files changed, 24 insertions(+), 37 deletions(-) diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 2b7839b..e81a6a7 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -98,9 +98,6 @@ static void enable_vmx(void) wrmsr(IA32_FEATURE_CONTROL, msr); } -#define PMG_CST_CONFIG_CONTROL 0xe2 -#define PMG_IO_BASE_ADDR 0xe3 -#define PMG_IO_CAPTURE_ADDR 0xe4 #define MSR_BBL_CR_CTL3 0x11e #define MSR_FSB_FREQ 0xcd @@ -123,7 +120,7 @@ static void configure_c_states(const int quad) const int cst_range = (c6 ? 6 : (c5 ? 5 : 4)) - 2; /* zero means lvl2 */ - msr = rdmsr(PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk msr.lo |= (1 << 8); if (quad) { @@ -140,17 +137,17 @@ static void configure_c_states(const int quad) msr.lo |= (1 << 10); /* Enable IO MWAIT redirection. */ if (c6) msr.lo |= (1 << 25); - wrmsr(PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE */ msr.hi = 0; msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); - wrmsr(PMG_IO_BASE_ADDR, msr); + wrmsr(MSR_PMG_IO_BASE_ADDR, msr); /* Set IO Capture Address */ msr.hi = 0; msr.lo = ((PMB0_BASE + 4) & 0xffff) | ((cst_range & 0xffff) << 16); - wrmsr(PMG_IO_CAPTURE_ADDR, msr); + wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); if (c5) { msr = rdmsr(MSR_BBL_CR_CTL3); @@ -188,10 +185,10 @@ static void configure_p_states(const char stepping, const char cores) wrmsr(IA32_PERF_CTL, msr); } - msr = rdmsr(PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); msr.lo &= ~(1 << 11); /* Enable hw coordination. */ msr.lo |= (1 << 15); /* Lock config until next reset. */ - wrmsr(PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); } #define MSR_EMTTM_CR_TABLE(x) (0xa8 + (x)) diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 4bf2924..803875d 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -80,34 +80,30 @@ static void enable_vmx(void) wrmsr(IA32_FEATURE_CONTROL, msr); } -#define PMG_CST_CONFIG_CONTROL 0xe2 -#define PMG_IO_BASE_ADDR 0xe3 -#define PMG_IO_CAPTURE_ADDR 0xe4 - #define HIGHEST_CLEVEL 3 static void configure_c_states(void) { msr_t msr; - msr = rdmsr(PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); msr.lo |= (1 << 15); // Lock configuration msr.lo |= (1 << 10); // redirect IO-based CState transition requests to MWAIT msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3 // TODO Do we want Deep C4 and Dynamic L2 shrinking? - wrmsr(PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE (P_BLK) */ msr.hi = 0; // TODO Do we want PM1_BASE? Needs SMM? //msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); msr.lo = ((PMB0_BASE + 4) & 0xffff); - wrmsr(PMG_IO_BASE_ADDR, msr); + wrmsr(MSR_PMG_IO_BASE_ADDR, msr); /* set C_LVL controls */ msr.hi = 0; msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted - wrmsr(PMG_IO_CAPTURE_ADDR, msr); + wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); } #define IA32_MISC_ENABLE 0x1a0 diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 4ed5d1e..9e7c3fa 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -22,6 +22,7 @@ #include <stdlib.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> +#include <cpu/intel/speedstep.h> #include "model_206ax.h" static void msr_set_bit(unsigned reg, unsigned bit) diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index a7ca04a..d440c70 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -48,8 +48,6 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 -#define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 71879e2..d1f9277 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -316,11 +316,11 @@ static void configure_c_states(void) msr.lo |= 7; // No package C-state limit wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); - msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE); + msr = rdmsr(MSR_PMG_IO_CAPTURE_ADDR); msr.lo &= ~0x7ffff; msr.lo |= (PMB0_BASE + 4); // LVL_2 base address msr.lo |= (2 << 16); // CST Range: C7 is max C-state - wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr); + wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); msr = rdmsr(MSR_MISC_PWR_MGMT); msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 9dbb137..2e25553 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -77,16 +77,12 @@ static void enable_vmx(void) wrmsr(IA32_FEATURE_CONTROL, msr); } -#define PMG_CST_CONFIG_CONTROL 0xe2 -#define PMG_IO_BASE_ADDR 0xe3 -#define PMG_IO_CAPTURE_ADDR 0xe4 - #define HIGHEST_CLEVEL 3 static void configure_c_states(void) { msr_t msr; - msr = rdmsr(PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); msr.lo |= (1 << 15); // config lock until next reset. msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk @@ -96,17 +92,17 @@ static void configure_c_states(void) msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3 - wrmsr(PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE (P_BLK) */ msr.hi = 0; msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); - wrmsr(PMG_IO_BASE_ADDR, msr); + wrmsr(MSR_PMG_IO_BASE_ADDR, msr); /* set C_LVL controls */ msr.hi = 0; msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted - wrmsr(PMG_IO_CAPTURE_ADDR, msr); + wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); } #define IA32_MISC_ENABLE 0x1a0 diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 3cdfdc4..d7c8d51 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -91,16 +91,12 @@ static void enable_vmx(void) wrmsr(IA32_FEATURE_CONTROL, msr); } -#define PMG_CST_CONFIG_CONTROL 0xe2 -#define PMG_IO_BASE_ADDR 0xe3 -#define PMG_IO_CAPTURE_ADDR 0xe4 - #define HIGHEST_CLEVEL 3 static void configure_c_states(void) { msr_t msr; - msr = rdmsr(PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); msr.lo |= (1 << 15); // config lock until next reset msr.lo |= (1 << 14); // Deeper Sleep @@ -112,17 +108,17 @@ static void configure_c_states(void) msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3 - wrmsr(PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE */ msr.hi = 0; msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); - wrmsr(PMG_IO_BASE_ADDR, msr); + wrmsr(MSR_PMG_IO_BASE_ADDR, msr); /* Set C_LVL controls and IO Capture Address */ msr.hi = 0; msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted - wrmsr(PMG_IO_CAPTURE_ADDR, msr); + wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); } #define IA32_MISC_ENABLE 0x1a0 diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index b5d1d68..86778b1 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -46,6 +46,9 @@ #define MSR_THERM2_CTL 0x19D #define IA32_MISC_ENABLES 0x1A0 #define MSR_FSB_CLOCK_VCC 0xce +#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PMG_IO_BASE_ADDR 0xe3 +#define MSR_PMG_IO_CAPTURE_ADDR 0xe4 #define MSR_EXTENDED_CONFIG 0xee

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New patch to review for coreboot: a8107ab Intel: Replace MSR 0xcd with MSR_FSB_FREQ
by Patrick Georgi 09 Feb '13

09 Feb '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2339 -gerrit commit a8107aba0ab2d7f99ed1b2d631ae5509933caec8 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Feb 9 15:56:04 2013 +0100 Intel: Replace MSR 0xcd with MSR_FSB_FREQ And move the corresponding #define to speedstep.h Change-Id: I8c884b8ab9ba54e01cfed7647a59deafeac94f2d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/cpu/intel/model_1067x/model_1067x_init.c | 1 - src/cpu/intel/speedstep/acpi.c | 2 +- src/cpu/x86/lapic/apic_timer.c | 5 +++-- src/include/cpu/intel/speedstep.h | 1 + src/northbridge/intel/gm45/delay.c | 3 ++- src/northbridge/intel/i3100/raminit.c | 3 ++- src/northbridge/intel/i3100/raminit_ep80579.c | 5 +++-- src/northbridge/intel/i5000/raminit.c | 3 ++- src/northbridge/intel/i5000/udelay.c | 3 ++- src/northbridge/intel/i945/udelay.c | 3 ++- 10 files changed, 18 insertions(+), 11 deletions(-) diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 2b7839b..e51c993 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -102,7 +102,6 @@ static void enable_vmx(void) #define PMG_IO_BASE_ADDR 0xe3 #define PMG_IO_CAPTURE_ADDR 0xe4 #define MSR_BBL_CR_CTL3 0x11e -#define MSR_FSB_FREQ 0xcd static void configure_c_states(const int quad) { diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 910055d..dfcc82e 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -67,7 +67,7 @@ static int determine_total_number_of_cores(void) */ static int get_fsb(void) { - const u32 fsbcode = rdmsr(0xcd).lo & 7; + const u32 fsbcode = rdmsr(MSR_FSB_FREQ).lo & 7; switch (fsbcode) { case 0: return 800; /* / 3 == 266 */ case 1: return 400; /* / 3 == 133 */ diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 53209fb..93e948f 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -25,6 +25,7 @@ #include <cpu/x86/car.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> +#include <cpu/intel/speedstep.h> /* NOTE: This code uses global variables, so it can not be used during * memory init. @@ -53,11 +54,11 @@ static int set_timer_fsb(void) switch (c.x86_model) { case 0xe: /* Core Solo/Duo */ case 0x1c: /* Atom */ - timer_fsb = core_fsb[rdmsr(0xcd).lo & 7]; + timer_fsb = core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; break; case 0xf: /* Core 2 or Xeon */ case 0x17: /* Enhanced Core */ - timer_fsb = core2_fsb[rdmsr(0xcd).lo & 7]; + timer_fsb = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; break; case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/ case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/ diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index b5d1d68..b6d7b34 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -45,6 +45,7 @@ #define IA32_PERF_CTL 0x199 #define MSR_THERM2_CTL 0x19D #define IA32_MISC_ENABLES 0x1A0 +#define MSR_FSB_FREQ 0xcd #define MSR_FSB_CLOCK_VCC 0xce #define MSR_EXTENDED_CONFIG 0xee diff --git a/src/northbridge/intel/gm45/delay.c b/src/northbridge/intel/gm45/delay.c index 50bea2c..c33bbe2 100644 --- a/src/northbridge/intel/gm45/delay.c +++ b/src/northbridge/intel/gm45/delay.c @@ -21,6 +21,7 @@ #include <stdint.h> #include <cpu/x86/tsc.h> #include <cpu/x86/msr.h> +#include <cpu/intel/speedstep.h> #include "delay.h" /* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ @@ -45,7 +46,7 @@ static void _udelay(const u32 us, const u32 numerator, const int total) u32 fsb = 0, divisor; u32 d; /* ticks per us */ - msr = rdmsr(0xcd); + msr = rdmsr(MSR_FSB_FREQ); switch (msr.lo & 0x07) { case 5: fsb = 400; diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c index b453e8b..fa42efc 100644 --- a/src/northbridge/intel/i3100/raminit.c +++ b/src/northbridge/intel/i3100/raminit.c @@ -21,6 +21,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> +#include <cpu/intel/speedstep.h> #include <stdlib.h> #include "raminit.h" #include "i3100.h" @@ -583,7 +584,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, drc |= (1 << 4); /* independent clocks */ /* set front side bus speed */ - msr = rdmsr(0xcd); /* returns 0 on Pentium M 90nm */ + msr = rdmsr(MSR_FSB_FREQ); /* returns 0 on Pentium M 90nm */ value = msr.lo & 0x07; drc &= ~(3 << 2); drc |= (fsb_conversion[value] << 2); diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 5fe206f..4c688d5 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -20,6 +20,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> +#include <cpu/intel/speedstep.h> #include "raminit_ep80579.h" #include "ep80579.h" @@ -441,8 +442,8 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, /* TODO check: */ /* set front side bus speed */ - msr = rdmsr(0xcd); /* returns 0 on Pentium M 90nm */ - print_debug("msr 0xcd = "); + msr = rdmsr(MSR_FSB_FREQ); /* returns 0 on Pentium M 90nm */ + print_debug("MSR FSB_FREQ(0xcd) = "); print_debug_hex32(msr.hi); print_debug_hex32(msr.lo); print_debug("\n"); diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c index ffc579a..3c913cf 100644 --- a/src/northbridge/intel/i5000/raminit.c +++ b/src/northbridge/intel/i5000/raminit.c @@ -25,6 +25,7 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> +#include <cpu/intel/speedstep.h> #include <console/console.h> #include <spd.h> #include <types.h> @@ -1560,7 +1561,7 @@ static int i5000_setup_clocking(struct i5000_fbd_setup *setup) return 1; } - msr = rdmsr(0xcd); + msr = rdmsr(MSR_FSB_FREQ); switch(msr.lo & 7) { case 1: diff --git a/src/northbridge/intel/i5000/udelay.c b/src/northbridge/intel/i5000/udelay.c index 6462fe0..ff2da6f 100644 --- a/src/northbridge/intel/i5000/udelay.c +++ b/src/northbridge/intel/i5000/udelay.c @@ -21,6 +21,7 @@ #include <stdint.h> #include <cpu/x86/tsc.h> #include <cpu/x86/msr.h> +#include <cpu/intel/speedstep.h> #include <console/console.h> /** * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock @@ -35,7 +36,7 @@ void udelay(u32 us) u32 d; /* ticks per us */ u32 dn = 0x1000000 / 2; /* how many us before we need to use hi */ - msr = rdmsr(0xcd); + msr = rdmsr(MSR_FSB_FREQ); switch (msr.lo & 0x07) { case 5: fsb = 400; diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c index ce5e9d8..be56008 100644 --- a/src/northbridge/intel/i945/udelay.c +++ b/src/northbridge/intel/i945/udelay.c @@ -22,6 +22,7 @@ #include <stdint.h> #include <cpu/x86/tsc.h> #include <cpu/x86/msr.h> +#include <cpu/intel/speedstep.h> /* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) @@ -46,7 +47,7 @@ void udelay(u32 us) u32 fsb = 0, divisor; u32 d; /* ticks per us */ - msr = rdmsr(0xcd); + msr = rdmsr(MSR_FSB_FREQ); switch (msr.lo & 0x07) { case 5: fsb = 400;

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New patch to review for coreboot: 0739b12 build system: Don't run the full build system on "make clean"
by Patrick Georgi 09 Feb '13

09 Feb '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2338 -gerrit commit 0739b12ca1619dbd4c193d2e2878c6cc64295cef Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Feb 9 15:45:02 2013 +0100 build system: Don't run the full build system on "make clean" When running "make clean" the build system used to parse the entire build system. Besides costing time, it prevents cleaning the tree if a blobs-board is selected but blobs are not enabled. Change-Id: Ief6362460d4eb7edcb4b0a47ec76cb9a61bf3b86 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 527fbcc..eb22b18 100644 --- a/Makefile +++ b/Makefile @@ -97,10 +97,10 @@ ifeq ($(strip $(HAVE_DOTCONFIG)),) NOCOMPILE:=1 endif ifneq ($(MAKECMDGOALS),) -ifneq ($(filter %config distclean,$(MAKECMDGOALS)),) +ifneq ($(filter %config %clean,$(MAKECMDGOALS)),) NOCOMPILE:=1 endif -ifeq ($(MAKECMDGOALS), distclean) +ifeq ($(MAKECMDGOALS), %clean) NOMKDIR:=1 endif endif

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New patch to review for coreboot: ff95c8a speedstep: Deduplicate some MSR identifiers
by Patrick Georgi 09 Feb '13

09 Feb '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2337 -gerrit commit ff95c8ab670f793d1e00490d8f1dfeefc6166184 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Feb 9 15:35:30 2013 +0100 speedstep: Deduplicate some MSR identifiers In particular: MSR_PMG_CST_CONFIG_CONTROL MSR_PMG_IO_BASE_ADDR MSR_PMG_IO_CAPTURE_ADDR Change-Id: Ief2697312f0edf8c45f7d3550a7bedaff1b69dc6 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/cpu/intel/model_1067x/model_1067x_init.c | 15 ++++++--------- src/cpu/intel/model_106cx/model_106cx_init.c | 12 ++++-------- src/cpu/intel/model_206ax/finalize.c | 1 + src/cpu/intel/model_206ax/model_206ax.h | 2 -- src/cpu/intel/model_6ex/model_6ex_init.c | 12 ++++-------- src/cpu/intel/model_6fx/model_6fx_init.c | 12 ++++-------- src/include/cpu/intel/speedstep.h | 3 +++ 7 files changed, 22 insertions(+), 35 deletions(-) diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 2b7839b..e81a6a7 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -98,9 +98,6 @@ static void enable_vmx(void) wrmsr(IA32_FEATURE_CONTROL, msr); } -#define PMG_CST_CONFIG_CONTROL 0xe2 -#define PMG_IO_BASE_ADDR 0xe3 -#define PMG_IO_CAPTURE_ADDR 0xe4 #define MSR_BBL_CR_CTL3 0x11e #define MSR_FSB_FREQ 0xcd @@ -123,7 +120,7 @@ static void configure_c_states(const int quad) const int cst_range = (c6 ? 6 : (c5 ? 5 : 4)) - 2; /* zero means lvl2 */ - msr = rdmsr(PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk msr.lo |= (1 << 8); if (quad) { @@ -140,17 +137,17 @@ static void configure_c_states(const int quad) msr.lo |= (1 << 10); /* Enable IO MWAIT redirection. */ if (c6) msr.lo |= (1 << 25); - wrmsr(PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE */ msr.hi = 0; msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); - wrmsr(PMG_IO_BASE_ADDR, msr); + wrmsr(MSR_PMG_IO_BASE_ADDR, msr); /* Set IO Capture Address */ msr.hi = 0; msr.lo = ((PMB0_BASE + 4) & 0xffff) | ((cst_range & 0xffff) << 16); - wrmsr(PMG_IO_CAPTURE_ADDR, msr); + wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); if (c5) { msr = rdmsr(MSR_BBL_CR_CTL3); @@ -188,10 +185,10 @@ static void configure_p_states(const char stepping, const char cores) wrmsr(IA32_PERF_CTL, msr); } - msr = rdmsr(PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); msr.lo &= ~(1 << 11); /* Enable hw coordination. */ msr.lo |= (1 << 15); /* Lock config until next reset. */ - wrmsr(PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); } #define MSR_EMTTM_CR_TABLE(x) (0xa8 + (x)) diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 4bf2924..803875d 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -80,34 +80,30 @@ static void enable_vmx(void) wrmsr(IA32_FEATURE_CONTROL, msr); } -#define PMG_CST_CONFIG_CONTROL 0xe2 -#define PMG_IO_BASE_ADDR 0xe3 -#define PMG_IO_CAPTURE_ADDR 0xe4 - #define HIGHEST_CLEVEL 3 static void configure_c_states(void) { msr_t msr; - msr = rdmsr(PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); msr.lo |= (1 << 15); // Lock configuration msr.lo |= (1 << 10); // redirect IO-based CState transition requests to MWAIT msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3 // TODO Do we want Deep C4 and Dynamic L2 shrinking? - wrmsr(PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE (P_BLK) */ msr.hi = 0; // TODO Do we want PM1_BASE? Needs SMM? //msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); msr.lo = ((PMB0_BASE + 4) & 0xffff); - wrmsr(PMG_IO_BASE_ADDR, msr); + wrmsr(MSR_PMG_IO_BASE_ADDR, msr); /* set C_LVL controls */ msr.hi = 0; msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted - wrmsr(PMG_IO_CAPTURE_ADDR, msr); + wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); } #define IA32_MISC_ENABLE 0x1a0 diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 4ed5d1e..9e7c3fa 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -22,6 +22,7 @@ #include <stdlib.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> +#include <cpu/intel/speedstep.h> #include "model_206ax.h" static void msr_set_bit(unsigned reg, unsigned bit) diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index a7ca04a..d440c70 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -48,8 +48,6 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 -#define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 9dbb137..2e25553 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -77,16 +77,12 @@ static void enable_vmx(void) wrmsr(IA32_FEATURE_CONTROL, msr); } -#define PMG_CST_CONFIG_CONTROL 0xe2 -#define PMG_IO_BASE_ADDR 0xe3 -#define PMG_IO_CAPTURE_ADDR 0xe4 - #define HIGHEST_CLEVEL 3 static void configure_c_states(void) { msr_t msr; - msr = rdmsr(PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); msr.lo |= (1 << 15); // config lock until next reset. msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk @@ -96,17 +92,17 @@ static void configure_c_states(void) msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3 - wrmsr(PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE (P_BLK) */ msr.hi = 0; msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); - wrmsr(PMG_IO_BASE_ADDR, msr); + wrmsr(MSR_PMG_IO_BASE_ADDR, msr); /* set C_LVL controls */ msr.hi = 0; msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted - wrmsr(PMG_IO_CAPTURE_ADDR, msr); + wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); } #define IA32_MISC_ENABLE 0x1a0 diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 3cdfdc4..d7c8d51 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -91,16 +91,12 @@ static void enable_vmx(void) wrmsr(IA32_FEATURE_CONTROL, msr); } -#define PMG_CST_CONFIG_CONTROL 0xe2 -#define PMG_IO_BASE_ADDR 0xe3 -#define PMG_IO_CAPTURE_ADDR 0xe4 - #define HIGHEST_CLEVEL 3 static void configure_c_states(void) { msr_t msr; - msr = rdmsr(PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); msr.lo |= (1 << 15); // config lock until next reset msr.lo |= (1 << 14); // Deeper Sleep @@ -112,17 +108,17 @@ static void configure_c_states(void) msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3 - wrmsr(PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE */ msr.hi = 0; msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); - wrmsr(PMG_IO_BASE_ADDR, msr); + wrmsr(MSR_PMG_IO_BASE_ADDR, msr); /* Set C_LVL controls and IO Capture Address */ msr.hi = 0; msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted - wrmsr(PMG_IO_CAPTURE_ADDR, msr); + wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); } #define IA32_MISC_ENABLE 0x1a0 diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index b5d1d68..86778b1 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -46,6 +46,9 @@ #define MSR_THERM2_CTL 0x19D #define IA32_MISC_ENABLES 0x1A0 #define MSR_FSB_CLOCK_VCC 0xce +#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PMG_IO_BASE_ADDR 0xe3 +#define MSR_PMG_IO_CAPTURE_ADDR 0xe4 #define MSR_EXTENDED_CONFIG 0xee

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New patch to review for coreboot: a8aa579 romcc: Use default romcc flags for most boards
by Patrick Georgi 09 Feb '13

09 Feb '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2336 -gerrit commit a8aa579af6461b4d96bbfe068b46066e6fd49112 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Feb 9 15:26:47 2013 +0100 romcc: Use default romcc flags for most boards Except for one board, the flags can be derived from CONFIG_MMX and CONFIG_SSE. Change-Id: I64a11135ee7ce8676f3422b2377069a3fa78e24d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/arch/x86/Makefile.inc | 10 +++++++++- src/mainboard/advantech/pcm-5820/Makefile.inc | 21 --------------------- src/mainboard/aopen/dxplplusu/Makefile.inc | 1 - src/mainboard/asi/mb_5blgp/Makefile.inc | 21 --------------------- src/mainboard/asi/mb_5blmp/Makefile.inc | 21 --------------------- src/mainboard/axus/tc320/Makefile.inc | 21 --------------------- src/mainboard/bcom/winnet100/Makefile.inc | 21 --------------------- src/mainboard/bifferos/bifferboard/Makefile.inc | 1 - src/mainboard/digitallogic/adl855pc/Makefile.inc | 1 - src/mainboard/digitallogic/msm586seg/Makefile.inc | 1 - src/mainboard/eaglelion/5bcm/Makefile.inc | 21 --------------------- src/mainboard/emulation/qemu-x86/Makefile.inc | 2 -- src/mainboard/iei/juki-511p/Makefile.inc | 21 --------------------- src/mainboard/iei/nova4899r/Makefile.inc | 21 --------------------- src/mainboard/intel/jarrell/Makefile.inc | 1 - src/mainboard/intel/mtarvon/Makefile.inc | 1 - src/mainboard/intel/xe7501devkit/Makefile.inc | 1 - src/mainboard/lanner/em8510/Makefile.inc | 21 --------------------- src/mainboard/lippert/frontrunner/Makefile.inc | 1 - src/mainboard/supermicro/x6dai_g/Makefile.inc | 21 --------------------- src/mainboard/supermicro/x6dhe_g/Makefile.inc | 21 --------------------- src/mainboard/supermicro/x6dhe_g2/Makefile.inc | 21 --------------------- src/mainboard/supermicro/x6dhr_ig/Makefile.inc | 21 --------------------- src/mainboard/supermicro/x6dhr_ig2/Makefile.inc | 21 --------------------- src/mainboard/technologic/ts5300/Makefile.inc | 1 - src/mainboard/televideo/tc7020/Makefile.inc | 21 --------------------- src/mainboard/via/epia-cn/Makefile.inc | 1 - src/mainboard/via/pc2500e/Makefile.inc | 21 --------------------- 28 files changed, 9 insertions(+), 349 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index da03693..795a245 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -212,7 +212,15 @@ crt0s += $(src)/arch/x86/init/crt0_romcc_epilogue.inc endif ifeq ($(CONFIG_ROMCC),y) -ROMCCFLAGS ?= -mcpu=p2 -O2 +ifeq ($(CONFIG_MMX),y) + ifeq ($(CONFIG_SSE),y) + ROMCCFLAGS := -mcpu=p4 -O2 # MMX, SSE + else + ROMCCFLAGS := -mcpu=p2 -O2 # MMX, !SSE + endif +else + ROMCCFLAGS := -mcpu=i386 -O2 # !MMX, !SSE +endif $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h printf " ROMCC romstage.inc\n" diff --git a/src/mainboard/advantech/pcm-5820/Makefile.inc b/src/mainboard/advantech/pcm-5820/Makefile.inc deleted file mode 100644 index 21ae28e..0000000 --- a/src/mainboard/advantech/pcm-5820/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -ROMCCFLAGS := -mcpu=i386 -O2 diff --git a/src/mainboard/aopen/dxplplusu/Makefile.inc b/src/mainboard/aopen/dxplplusu/Makefile.inc deleted file mode 100644 index 0f285cd..0000000 --- a/src/mainboard/aopen/dxplplusu/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ROMCCFLAGS := -mcpu=p4 -O2 diff --git a/src/mainboard/asi/mb_5blgp/Makefile.inc b/src/mainboard/asi/mb_5blgp/Makefile.inc deleted file mode 100644 index 21ae28e..0000000 --- a/src/mainboard/asi/mb_5blgp/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -ROMCCFLAGS := -mcpu=i386 -O2 diff --git a/src/mainboard/asi/mb_5blmp/Makefile.inc b/src/mainboard/asi/mb_5blmp/Makefile.inc deleted file mode 100644 index 21ae28e..0000000 --- a/src/mainboard/asi/mb_5blmp/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -ROMCCFLAGS := -mcpu=i386 -O2 diff --git a/src/mainboard/axus/tc320/Makefile.inc b/src/mainboard/axus/tc320/Makefile.inc deleted file mode 100644 index 21ae28e..0000000 --- a/src/mainboard/axus/tc320/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -ROMCCFLAGS := -mcpu=i386 -O2 diff --git a/src/mainboard/bcom/winnet100/Makefile.inc b/src/mainboard/bcom/winnet100/Makefile.inc deleted file mode 100644 index 21ae28e..0000000 --- a/src/mainboard/bcom/winnet100/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -ROMCCFLAGS := -mcpu=i386 -O2 diff --git a/src/mainboard/bifferos/bifferboard/Makefile.inc b/src/mainboard/bifferos/bifferboard/Makefile.inc deleted file mode 100644 index 7678401..0000000 --- a/src/mainboard/bifferos/bifferboard/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ROMCCFLAGS := -mcpu=i386 -O diff --git a/src/mainboard/digitallogic/adl855pc/Makefile.inc b/src/mainboard/digitallogic/adl855pc/Makefile.inc deleted file mode 100644 index accacee..0000000 --- a/src/mainboard/digitallogic/adl855pc/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ROMCCFLAGS := -mcpu=p3 -O diff --git a/src/mainboard/digitallogic/msm586seg/Makefile.inc b/src/mainboard/digitallogic/msm586seg/Makefile.inc deleted file mode 100644 index 7678401..0000000 --- a/src/mainboard/digitallogic/msm586seg/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ROMCCFLAGS := -mcpu=i386 -O diff --git a/src/mainboard/eaglelion/5bcm/Makefile.inc b/src/mainboard/eaglelion/5bcm/Makefile.inc deleted file mode 100644 index 21ae28e..0000000 --- a/src/mainboard/eaglelion/5bcm/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -ROMCCFLAGS := -mcpu=i386 -O2 diff --git a/src/mainboard/emulation/qemu-x86/Makefile.inc b/src/mainboard/emulation/qemu-x86/Makefile.inc index 93f9cc2..22fdfe1 100644 --- a/src/mainboard/emulation/qemu-x86/Makefile.inc +++ b/src/mainboard/emulation/qemu-x86/Makefile.inc @@ -1,4 +1,2 @@ -ROMCCFLAGS := -mcpu=i386 -O - cpu_incs += $(src)/mainboard/emulation/qemu-x86/cache_as_ram.inc ramstage-y += northbridge.c diff --git a/src/mainboard/iei/juki-511p/Makefile.inc b/src/mainboard/iei/juki-511p/Makefile.inc deleted file mode 100644 index 21ae28e..0000000 --- a/src/mainboard/iei/juki-511p/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -ROMCCFLAGS := -mcpu=i386 -O2 diff --git a/src/mainboard/iei/nova4899r/Makefile.inc b/src/mainboard/iei/nova4899r/Makefile.inc deleted file mode 100644 index 21ae28e..0000000 --- a/src/mainboard/iei/nova4899r/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -ROMCCFLAGS := -mcpu=i386 -O2 diff --git a/src/mainboard/intel/jarrell/Makefile.inc b/src/mainboard/intel/jarrell/Makefile.inc deleted file mode 100644 index 0f285cd..0000000 --- a/src/mainboard/intel/jarrell/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ROMCCFLAGS := -mcpu=p4 -O2 diff --git a/src/mainboard/intel/mtarvon/Makefile.inc b/src/mainboard/intel/mtarvon/Makefile.inc deleted file mode 100644 index 0f285cd..0000000 --- a/src/mainboard/intel/mtarvon/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ROMCCFLAGS := -mcpu=p4 -O2 diff --git a/src/mainboard/intel/xe7501devkit/Makefile.inc b/src/mainboard/intel/xe7501devkit/Makefile.inc deleted file mode 100644 index 0f285cd..0000000 --- a/src/mainboard/intel/xe7501devkit/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ROMCCFLAGS := -mcpu=p4 -O2 diff --git a/src/mainboard/lanner/em8510/Makefile.inc b/src/mainboard/lanner/em8510/Makefile.inc deleted file mode 100644 index 6b93f64..0000000 --- a/src/mainboard/lanner/em8510/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Travelping GmbH <info(a)travelping.com> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -ROMCCFLAGS := -mcpu=p3 -O diff --git a/src/mainboard/lippert/frontrunner/Makefile.inc b/src/mainboard/lippert/frontrunner/Makefile.inc deleted file mode 100644 index 1286e63..0000000 --- a/src/mainboard/lippert/frontrunner/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ROMCCFLAGS=-mcpu=i386 -O diff --git a/src/mainboard/supermicro/x6dai_g/Makefile.inc b/src/mainboard/supermicro/x6dai_g/Makefile.inc deleted file mode 100644 index 495602d..0000000 --- a/src/mainboard/supermicro/x6dai_g/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -ROMCCFLAGS=-mcpu=p4 -O2 diff --git a/src/mainboard/supermicro/x6dhe_g/Makefile.inc b/src/mainboard/supermicro/x6dhe_g/Makefile.inc deleted file mode 100644 index 495602d..0000000 --- a/src/mainboard/supermicro/x6dhe_g/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -ROMCCFLAGS=-mcpu=p4 -O2 diff --git a/src/mainboard/supermicro/x6dhe_g2/Makefile.inc b/src/mainboard/supermicro/x6dhe_g2/Makefile.inc deleted file mode 100644 index 495602d..0000000 --- a/src/mainboard/supermicro/x6dhe_g2/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -ROMCCFLAGS=-mcpu=p4 -O2 diff --git a/src/mainboard/supermicro/x6dhr_ig/Makefile.inc b/src/mainboard/supermicro/x6dhr_ig/Makefile.inc deleted file mode 100644 index 495602d..0000000 --- a/src/mainboard/supermicro/x6dhr_ig/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -ROMCCFLAGS=-mcpu=p4 -O2 diff --git a/src/mainboard/supermicro/x6dhr_ig2/Makefile.inc b/src/mainboard/supermicro/x6dhr_ig2/Makefile.inc deleted file mode 100644 index 495602d..0000000 --- a/src/mainboard/supermicro/x6dhr_ig2/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -ROMCCFLAGS=-mcpu=p4 -O2 diff --git a/src/mainboard/technologic/ts5300/Makefile.inc b/src/mainboard/technologic/ts5300/Makefile.inc deleted file mode 100644 index 7678401..0000000 --- a/src/mainboard/technologic/ts5300/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ROMCCFLAGS := -mcpu=i386 -O diff --git a/src/mainboard/televideo/tc7020/Makefile.inc b/src/mainboard/televideo/tc7020/Makefile.inc deleted file mode 100644 index 21ae28e..0000000 --- a/src/mainboard/televideo/tc7020/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -ROMCCFLAGS := -mcpu=i386 -O2 diff --git a/src/mainboard/via/epia-cn/Makefile.inc b/src/mainboard/via/epia-cn/Makefile.inc deleted file mode 100644 index 691b3d5..0000000 --- a/src/mainboard/via/epia-cn/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ROMCCFLAGS := -mcpu=c3 -O diff --git a/src/mainboard/via/pc2500e/Makefile.inc b/src/mainboard/via/pc2500e/Makefile.inc deleted file mode 100644 index 8d32f87..0000000 --- a/src/mainboard/via/pc2500e/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -ROMCCFLAGS ?= -mcpu=c3

1 0

New patch to review for coreboot: 1f4e9a4 romcc: Don't use user overridable romcc flags for bootblock
by Patrick Georgi 09 Feb '13

09 Feb '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2335 -gerrit commit 1f4e9a4fb86e0672ae0121582d93eb9495a04a58 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Feb 9 14:35:55 2013 +0100 romcc: Don't use user overridable romcc flags for bootblock The bootblock is typically run before fpu/mmx/sse setup, so we can't rely on -mcpu=p4 and the like to increase the register space. bootblock_romccflags does that for SSE, but they're controlled separately. Change-Id: I2b0609ac18b2394a319bf9bbbee1f77d2e758127 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/arch/x86/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 419507b..da03693 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -330,7 +330,7 @@ $(objgenerated)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOC @printf " ROMCC $(subst $(obj)/,,$(@))\n" $(CC) $(INCLUDES) -MM -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d - $(ROMCC) -c -S $(bootblock_romccflags) $(ROMCCFLAGS) -I. $(INCLUDES) $< -o $@ + $(ROMCC) -c -S $(bootblock_romccflags) -I. $(INCLUDES) $< -o $@ $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld @printf " LINK $(subst $(obj)/,,$(@))\n"

1 0

New patch to review for coreboot: 161fd62 cbfstool: Handle alignment in UEFI payloads
by Patrick Georgi 09 Feb '13

09 Feb '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2334 -gerrit commit 161fd6250c7ebe90cfc19d32ea43d852ad581cde Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Feb 9 13:26:19 2013 +0100 cbfstool: Handle alignment in UEFI payloads Tiano for X64 is much cleaner to start up when using higher alignments in firmware volumes. These are implemented using padding files and sections that cbfstool knew nothing about. Skip these. Change-Id: Ibc433070ae6f822d00af2f187018ed8b358e2018 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/cbfstool/cbfs-mkpayload.c | 10 ++++++++++ util/cbfstool/fv.h | 2 ++ 2 files changed, 12 insertions(+) diff --git a/util/cbfstool/cbfs-mkpayload.c b/util/cbfstool/cbfs-mkpayload.c index e207b3e..6115e49 100644 --- a/util/cbfstool/cbfs-mkpayload.c +++ b/util/cbfstool/cbfs-mkpayload.c @@ -279,6 +279,11 @@ int parse_fv_to_payload(const struct buffer *input, } fh = (ffs_file_header_t *)(input->data + fv->header_length); + while (fh->file_type == FILETYPE_PAD) { + unsigned long offset = (fh->size[2] << 16) | (fh->size[1] << 8) | fh->size[0]; + ERROR("skipping %d bytes of FV padding\n", offset); + fh = (ffs_file_header_t *)(((void*)fh) + offset); + } if (fh->file_type != FILETYPE_SEC) { ERROR("Not a usable UEFI firmware volume.\n"); INFO("First file in first FV not a SEC core.\n"); @@ -286,6 +291,11 @@ int parse_fv_to_payload(const struct buffer *input, } cs = (common_section_header_t *)&fh[1]; + while (cs->section_type == SECTION_RAW) { + unsigned long offset = (cs->size[2] << 16) | (cs->size[1] << 8) | cs->size[0]; + ERROR("skipping %d bytes of section padding\n", offset); + cs = (common_section_header_t *)(((void*)cs) + offset); + } if (cs->section_type != SECTION_PE32) { ERROR("Not a usable UEFI firmware volume.\n"); INFO("Section type not PE32.\n"); diff --git a/util/cbfstool/fv.h b/util/cbfstool/fv.h index 1ea50e0..88457bf 100644 --- a/util/cbfstool/fv.h +++ b/util/cbfstool/fv.h @@ -33,6 +33,7 @@ typedef struct { } firmware_volume_header_t; #define FILETYPE_SEC 0x03 +#define FILETYPE_PAD 0xf0 typedef struct { uint8_t name[16]; uint16_t integrity; @@ -43,6 +44,7 @@ typedef struct { } ffs_file_header_t; #define SECTION_PE32 0x10 +#define SECTION_RAW 0x19 typedef struct { uint8_t size[3]; uint8_t section_type;

1 0

Patch merged into filo/master: 4e8ce15 Show coreboot version in FILO header
by gerrit＠coreboot.org 09 Feb '13

09 Feb '13

the following patch was just integrated into master: commit 4e8ce1517723797a5b82eb71e52c42ce37cac6f0 Author: Mathias Krause <mathias.krause(a)secunet.com> Date: Thu Oct 20 14:07:31 2011 +0200 Show coreboot version in FILO header Add get_cb_version(). Print coreboot version in the FILO header. Change-Id: I9a8831e574f71a22a10f10e7946062019ebb0e9f Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Reviewed-on: http://review.coreboot.org/2324 Tested-by: build bot (Jenkins) Reviewed-by: Mathias Krause <minipli(a)googlemail.com> See http://review.coreboot.org/2324 for details. -gerrit

1 0

Patch merged into coreboot/master: 408aefd cbfstool: Fix crash on image without bootblock in end of ROM.
by gerrit＠coreboot.org 09 Feb '13

09 Feb '13

the following patch was just integrated into master: commit 408aefd17645a95a0b1cac23b0ca7ad9c9df6925 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Sat Feb 9 10:38:55 2013 +0800 cbfstool: Fix crash on image without bootblock in end of ROM. On platforms with CBFS data filling end of ROM image without bootblock in the end (ex, ARM), calculation of "next valid entry" may exceed ROM image buffer in memory and raise segmentation fault when we try to compare its magic value. To fix this, always check if the entry address is inside ROM image buffer. Verified to build and boot successfully on qemu/x86 and armv7/snow. Change-Id: I117d6767a5403be636eea2b23be1dcf2e1c88839 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: http://review.coreboot.org/2330 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Build-Tested: build bot (Jenkins) at Sat Feb 9 04:11:31 2013, giving +1 Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Sat Feb 9 04:14:34 2013, giving +2 See http://review.coreboot.org/2330 for details. -gerrit

1 0

New patch to review for coreboot: b3addbf crossgcc: Support hosts using non-GNU make as default make.
by Hung-Te Lin 09 Feb '13

09 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2333 -gerrit commit b3addbfb9b12fa19351466d062fe7369f76df25d Author: Hung-Te Lin <hungte(a)chromium.org> Date: Sat Feb 9 13:08:03 2013 +0800 crossgcc: Support hosts using non-GNU make as default make. On hosts using non-GNU make as default make program (ex, FreeBSD's default is bsd make and GNU make as "gmake"), buliding acpica will fail. We should pass the correct name of make from bulidgcc. Verified to build on FreeBSD with gcc 4.7. Change-Id: Iacbf5a05e84a8a53d9d3e783a10131de603282c9 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- util/crossgcc/buildgcc | 2 +- .../acpica-unix-20121114_override_make.patch | 80 ++++++++++++++++++++++ 2 files changed, 81 insertions(+), 1 deletion(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index eaff24d..ad2bb65 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -584,7 +584,7 @@ printf "Building IASL ${IASL_VERSION} ... " cd $IASL_DIR/generate/unix rm -f .failed CFLAGS="$HOSTCFLAGS" - $MAKE CC="$CC" iasl || touch .failed + $MAKE MAKE="$MAKE" CC="$CC" iasl || touch .failed rm -f $DESTDIR$TARGETDIR/bin/iasl || touch .failed if [ -d bin32 ]; then cp bin32/iasl $DESTDIR$TARGETDIR/bin || touch .failed ; fi if [ -d bin64 ]; then cp bin64/iasl $DESTDIR$TARGETDIR/bin || touch .failed ; fi diff --git a/util/crossgcc/patches/acpica-unix-20121114_override_make.patch b/util/crossgcc/patches/acpica-unix-20121114_override_make.patch new file mode 100644 index 0000000..c4ce67f --- /dev/null +++ b/util/crossgcc/patches/acpica-unix-20121114_override_make.patch @@ -0,0 +1,80 @@ +diff -Nurbs acpica-unix-20121114.orig/generate/unix/Makefile.common acpica-unix-20121114/generate/unix/Makefile.common +--- acpica-unix-20121114.orig/generate/unix/Makefile.common 2012-11-15 00:22:38.000000000 +0800 ++++ acpica-unix-20121114/generate/unix/Makefile.common 2013-02-09 12:11:55.994133871 +0800 +@@ -19,17 +19,17 @@ + if [ $(BITS) -eq 32 ]; then \ + echo "Forced 32-bit generation of $@"; \ + mkdir -p obj32; \ +- make BITS=32; \ ++ $(MAKE) BITS=32; \ + echo "32-bit version of $@:"; \ + ls -al ../bin32/$@; \ + elif [ $(findstring 64,$(HARDWARE_NAME)) ]; then \ + mkdir -p obj64; \ +- make BITS=64; \ ++ $(MAKE) BITS=64; \ + echo "64-bit version of $@:"; \ + ls -al ../bin64/$@; \ + else \ + mkdir -p obj32; \ +- make BITS=32; \ ++ $(MAKE) BITS=32; \ + echo "32-bit version of $@:"; \ + ls -al ../bin32/$@; \ + fi; +@@ -47,7 +47,7 @@ + (cd $(BUILD_DIRECTORY_PATH)/$$toolname; \ + pwd; \ + mkdir -p obj32; \ +- make BITS=32; \ ++ $(MAKE) BITS=32; \ + echo "32-bit version of $$toolname:"; \ + ls -al obj32/$$toolname \ + ); \ +@@ -61,7 +61,7 @@ + (cd $(BUILD_DIRECTORY_PATH)/$$toolname; \ + pwd; \ + mkdir -p obj64; \ +- make BITS=64; \ ++ $(MAKE) BITS=64; \ + echo "64-bit version of $$toolname:"; \ + ls -al obj64/$$toolname \ + ); \ +@@ -73,11 +73,11 @@ + echo "Removing $$toolname"; \ + pwd; \ + if [ -d "obj32" ] ; then \ +- make BITS=32 clean; \ ++ $(MAKE) BITS=32 clean; \ + rmdir obj32; \ + fi; \ + if [ -d "obj64" ] ; then \ +- make BITS=64 clean; \ ++ $(MAKE) BITS=64 clean; \ + rmdir obj64; \ + fi; \ + echo ""; \ +@@ -92,10 +92,10 @@ + (cd $(BUILD_DIRECTORY_PATH)/$$toolname; \ + pwd; \ + if [ $(findstring 64,$(HARDWARE_NAME)) ]; then \ +- make BITS=64 PROG=$$toolname install; \ ++ $(MAKE) BITS=64 PROG=$$toolname install; \ + echo "Installed 64-bit version of $$toolname"; \ + else \ +- make BITS=32 PROG=$$toolname install; \ ++ $(MAKE) BITS=32 PROG=$$toolname install; \ + echo "Installed 32-bit version of $$toolname"; \ + fi; \ + echo ""; \ +diff -Nurbs acpica-unix-20121114.orig/generate/unix/Makefile.config acpica-unix-20121114/generate/unix/Makefile.config +--- acpica-unix-20121114.orig/generate/unix/Makefile.config 2012-11-15 00:22:38.000000000 +0800 ++++ acpica-unix-20121114/generate/unix/Makefile.config 2013-02-09 12:11:12.978134325 +0800 +@@ -31,6 +31,7 @@ + PROGS = acpibin acpiexec acpihelp acpinames acpisrc acpixtract iasl + HOST = _CYGWIN + CC = gcc ++MAKE = make + + # + # Common defines

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coreboot February 2013