coreboot February 2013

coreboot@coreboot.org

27 participants
790 discussions

building a coreboot (and 100% free software) compatible box
by "Kristóf, Csillag" 09 Feb '13

09 Feb '13

Hi, I am looking to build a new computer very soon, and I would like to ask for your advice about it, especially about software supports. My requirements are the following: 1. Absolutely necessary: 1.1. It must be able to run 100% free software. No closed BIOS. No binary firmware loaded to any part of the system with meaningful access to my data. (CPU, GPU, network card, etc.) Open display drivers. (Don't care about 3D.) I don't need UEFI, thank you very much. 1.2. It must have hardware support for AES. (For hw crypto acceleration.) 1.4. It must have hardware support for virtualization. 1.5. It must be able to drive 3 independent display outputs, at least in 1920x1200 resolution. (Preferably all digital, but that's not necessary.) 1.6. I must _use_ this, in a production environment, therefore it must work. Reliably. Now. I have ~15 yrs Linux programming experience, have modified stuff inside the kernel and X drivers, and I am not afraid to have my hands dirty, but now I am not here to run a hobby project, I want to to buy something that works, so that I can do my job using it. 2. Would be nice: 2.1. It should only use integrated graphics. (Both Intel and AMD can do 3 displays from integrated graphics now.) If I must, I could add discrete card[s], but that increases power consumption and system size... 2.2. Size small enough to be portable. Not planning to use in on the move; I mean portable in a (potentially huge) backpack, between several sites, where I intend to use them. - size of Intel NUC or Thin Mini-ITX mainboard are very cool, - Mini ITX is great, too, - MicroATX is acceptable - ATX seems to be too big, unless you can recommend me a really, really small case (with acceptable cooling) 2.3. Modern tech and High CPU performance. Of course :) Whatever is available... 2.4. Low TDP, for the possibility of quite/silent cooling. - definitely under 100W, - probably at most 65W, - ideally only 45W. 2.5. It should be built from standard components, with standard interfaces. (So that I can replace anything later.) Notebook/Laptop stuff is hard, there is too much diversity, not enough standards. Desktop technology seems to be easiest. x86 is not a must (as long as the given arch is supported by Debian), but would be nice, since it has the most support. * * * Obviously, given the requirements, I am aware that I will need to forgo some of the "would be nice" bits. If it was not for the software situation, I would go with a MoBo like Gigabyte GA-Z77MX-D3H TH (MicroATX, has 2x thunderbolt + DVI + HDMI), and with a CPU like Intel Xeon E3-1265L V2 (Quad-core with HT, 45W TDP, scores ~8800 on cpubenchmark I would not need to add a discrete video card. If I went the AMD way, I would go with ASUS F2A85-M PRO motherboard (eyefinity enabled, with DP + DVI + HDMI + D-SUB), and AMD A10-5700 APU. (65W TDP, scores ~4500 on cpubenchmark.) * * * Now, if I understand correctly, the both GPU's (intel HD 4000 and Radeon HD 7660D) runs on binary firmware blobs. I have read about attempts to replace the Intel firmware with an open version, but I am not sure where it stands now. What are my options here? Thank you for your help: Csillag

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Patch merged into coreboot/master: c146d66 DEBUG_CBFS should not depend on TPM
by gerrit＠coreboot.org 09 Feb '13

09 Feb '13

the following patch was just integrated into master: commit c146d668ef56c3cc21a1e2afd7df7776a3aed9e3 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 8 16:33:52 2013 -0800 DEBUG_CBFS should not depend on TPM This seemed to have been introduced in fe422184. Change-Id: I4f9ecfbec42aa8c0bb8887675a3add8951645b98 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2327 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Feb 9 01:44:48 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sat Feb 9 01:46:25 2013, giving +2 See http://review.coreboot.org/2327 for details. -gerrit

1 0

New patch to review for coreboot: 4ede33c DEBUG_CBFS should not depend on TPM
by David Hendricks 09 Feb '13

09 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2327 -gerrit commit 4ede33ccba0a4ed5b5f9cd6f82b3f7fb3e16941a Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Feb 8 16:33:52 2013 -0800 DEBUG_CBFS should not depend on TPM This seemed to have been introduced in fe422184. Change-Id: I4f9ecfbec42aa8c0bb8887675a3add8951645b98 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index 32a63d8..726fa39 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -597,7 +597,6 @@ config GDB_WAIT config DEBUG_CBFS bool "Output verbose CBFS debug messages" default n - depends on TPM help This option enables additional CBFS related debug messages.

1 0

Patch merged into coreboot/master: 223af0d document Intel VMX locking behavior
by gerrit＠coreboot.org 09 Feb '13

09 Feb '13

the following patch was just integrated into master: commit 223af0dc4480dbcf55802e879c723003909bf1e1 Author: Mike Frysinger <vapier(a)chromium.org> Date: Fri Feb 8 17:45:27 2013 -0500 document Intel VMX locking behavior Add a comment explaining that the existing lock bit logic is correct and "as designed" even though the manual states otherwise. This way people don't have to "just know" what is going on. Change-Id: I14e6763abfe339e034037b73db01d4ee634bb34d Signed-off-by: Mike Frysinger <vapier(a)chromium.org> Reviewed-on: http://review.coreboot.org/2326 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter(a)stuge.se> Build-Tested: build bot (Jenkins) at Sat Feb 9 00:23:44 2013, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Sat Feb 9 00:42:46 2013, giving +2 See http://review.coreboot.org/2326 for details. -gerrit

1 0

New patch to review for coreboot: 80b383f document Intel VMX locking behavior
by Mike Frysinger 09 Feb '13

09 Feb '13

Mike Frysinger (vapier(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2326 -gerrit commit 80b383f2acbf8130b8c0138318598854038da4ab Author: Mike Frysinger <vapier(a)chromium.org> Date: Fri Feb 8 17:45:27 2013 -0500 document Intel VMX locking behavior Add a comment explaining that the existing lock bit logic is correct and "as designed" even though the manual states otherwise. This way people don't have to "just know" what is going on. Change-Id: I14e6763abfe339e034037b73db01d4ee634bb34d Signed-off-by: Mike Frysinger <vapier(a)chromium.org> --- src/cpu/intel/model_206ax/model_206ax_init.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 64c32a0..71879e2 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -144,10 +144,23 @@ static void enable_vmx(void) printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); + /* Even though the Intel manual says you must set the lock bit in addition + * to the VMX bit in order for VMX to work, it is incorrect. Thus we leave + * it unlocked for the OS to manage things itself. This is good for a few + * reasons: + * - No need to reflash the bios just to toggle the lock bit. + * - The VMX bits really really should match each other across cores, so + * hard locking it on one while another has the opposite setting can + * easily lead to crashes as code using VMX migrates between them. + * - Vendors that want to "upsell" from a bios that disables+locks to + * one that doesn't is sleazy. + * By leaving this to the OS (e.g. Linux), people can do exactly what they + * want on the fly, and do it correctly (e.g. across multiple cores). + */ if (enable) { - msr.lo |= (1 << 2); - if (regs.ecx & CPUID_SMX) - msr.lo |= (1 << 1); + msr.lo |= (1 << 2); + if (regs.ecx & CPUID_SMX) + msr.lo |= (1 << 1); } wrmsr(IA32_FEATURE_CONTROL, msr);

1 0

Patch set updated for coreboot: 07c6777 snow: cleanup ramstage and call hardwaremain()
by Ronald G. Minnich 09 Feb '13

09 Feb '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2302 -gerrit commit 07c6777c37a976a328cdc5dfa02263f0fa8f25df Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Feb 6 16:29:42 2013 -0800 snow: cleanup ramstage and call hardwaremain() ** do not submit (work-in-progress) ** It *no longer* dies in write_coreboot_tables(). The trick is that lb_table_fini is more than informational, it writes a record and hence can not be called before any other record has been written, or it writes garbage. Oops. That's a problem with the original too: it assumes at least one record written, which is safe, because there's always one record written. Hence one can not call lb_table_fini just to ask a question. It can only be called once. Let's not have cbfs debug prints depend on TPM :-) Note 1: For ARM we can get away with only using one table, the high table and low table distinction is an x86-ism. Note 2: We'll eventually need to fill in the device structure so that search_global_resources() can mark regions appropriately. Fortunately we can get by with the assumption that 0x4000_0000- 0xffff_ffff is plain memory without any IO holes (We'll probably want to specify which regions are IO later on). Change-Id: I30200432535244de971a7cea9f7902f5e9b46403 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/Kconfig | 1 - src/arch/armv7/boot/coreboot_table.c | 90 +++++++++++++++------------ src/arch/armv7/boot/tables.c | 59 +++++++----------- src/arch/armv7/include/arch/coreboot_tables.h | 3 +- src/lib/compute_ip_checksum.c | 2 + src/lib/hardwaremain.c | 3 +- src/mainboard/google/snow/ramstage.c | 17 +++-- 7 files changed, 89 insertions(+), 86 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 32a63d8..726fa39 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -597,7 +597,6 @@ config GDB_WAIT config DEBUG_CBFS bool "Output verbose CBFS debug messages" default n - depends on TPM help This option enables additional CBFS related debug messages. diff --git a/src/arch/armv7/boot/coreboot_table.c b/src/arch/armv7/boot/coreboot_table.c index b2d88aa..3acfe16 100644 --- a/src/arch/armv7/boot/coreboot_table.c +++ b/src/arch/armv7/boot/coreboot_table.c @@ -559,11 +559,13 @@ struct lb_memory *get_lb_mem(void) return mem_ranges; } +#if 0 static void build_lb_mem_range(void *gp, struct device *dev, struct resource *res) { struct lb_memory *mem = gp; new_lb_memory_range(mem, LB_MEM_RAM, res->base, res->size); } +#endif static struct lb_memory *build_lb_mem(struct lb_header *head) { @@ -573,11 +575,15 @@ static struct lb_memory *build_lb_mem(struct lb_header *head) mem = lb_memory(head); mem_ranges = mem; + /* FIXME: implement this */ +#if 0 /* Build the raw table of memory */ search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, build_lb_mem_range, mem); - lb_cleanup_memory_ranges(mem); +#endif + /* FIXME: things die in cleanup_memory_ranges(), skip for now */ +// lb_cleanup_memory_ranges(mem); return mem; } @@ -596,47 +602,30 @@ static void add_lb_reserved(struct lb_memory *mem) } unsigned long write_coreboot_table( - unsigned long low_table_start, unsigned long low_table_end, - unsigned long rom_table_start, unsigned long rom_table_end) + unsigned long table_start, unsigned long table_end) { struct lb_header *head; struct lb_memory *mem; + unsigned long fini; -#if CONFIG_WRITE_HIGH_TABLES - printk(BIOS_DEBUG, "Writing high table forward entry at 0x%08lx\n", - low_table_end); - head = lb_table_init(low_table_end); - lb_forward(head, (struct lb_header*)rom_table_end); - - low_table_end = (unsigned long) lb_table_fini(head, 0); - printk(BIOS_DEBUG, "New low_table_end: 0x%08lx\n", low_table_end); - printk(BIOS_DEBUG, "Now going to write high coreboot table at 0x%08lx\n", - rom_table_end); - - head = lb_table_init(rom_table_end); - rom_table_end = (unsigned long)head; - printk(BIOS_DEBUG, "rom_table_end = 0x%08lx\n", rom_table_end); -#else - if(low_table_end > (0x1000 - sizeof(struct lb_header))) { /* after 4K */ - /* We need to put lbtable on to [0xf0000,0x100000) */ - head = lb_table_init(rom_table_end); - rom_table_end = (unsigned long)head; - } else { - head = lb_table_init(low_table_end); - low_table_end = (unsigned long)head; - } -#endif + printk(BIOS_DEBUG, "table_start: 0x%lx, table_end: 0x%lx, ", + table_start, table_end); + head = lb_table_init(table_start); + + printk(BIOS_DEBUG, "writing head (0x%p)... ", head); + printk(BIOS_DEBUG, "Writing table forward entry at 0x%08lx\n", + table_end); + lb_forward(head, (struct lb_header*)table_end); + printk(BIOS_DEBUG, "done\n"); - printk(BIOS_DEBUG, "Adjust low_table_end from 0x%08lx to ", low_table_end); - low_table_end += 0xfff; // 4K aligned - low_table_end &= ~0xfff; - printk(BIOS_DEBUG, "0x%08lx \n", low_table_end); + table_end = (unsigned long) head + head->table_bytes; + printk(BIOS_DEBUG, "New table_end: 0x%08lx\n", table_end); - /* The Linux kernel assumes this region is reserved */ - printk(BIOS_DEBUG, "Adjust rom_table_end from 0x%08lx to ", rom_table_end); - rom_table_end += 0xffff; // 64K align - rom_table_end &= ~0xffff; - printk(BIOS_DEBUG, "0x%08lx \n", rom_table_end); + /* FIXME(dhendrix): do we need this? */ + printk(BIOS_DEBUG, "Adjust table_end from 0x%08lx to ", table_end); + table_end += 0xfff; // 4K aligned + table_end &= ~0xfff; + printk(BIOS_DEBUG, "0x%08lx \n", table_end); #if CONFIG_USE_OPTION_TABLE { @@ -655,35 +644,50 @@ unsigned long write_coreboot_table( } #endif /* Record where RAM is located */ + /* FIXME(dhendrix): add global resources */ + printk(BIOS_DEBUG, "%s: head: 0x%p\n", __func__, head); mem = build_lb_mem(head); + /* FIXME: we seem to get a bogus return value */ + printk(BIOS_DEBUG, "%s: mem: 0x%p\n", __func__, mem); + if ((unsigned long)mem < CONFIG_RAMBASE) { + printk(BIOS_DEBUG, "%s: ZOMG PANIC!!!111n", __func__); + while (1); + } /* Record the mptable and the the lb_table (This will be adjusted later) */ lb_add_memory_range(mem, LB_MEM_TABLE, - low_table_start, low_table_end - low_table_start); + table_start, table_end - table_start); + printk(BIOS_DEBUG, "%s: checkpoint 1\n", __func__); /* Record the pirq table, acpi tables, and maybe the mptable */ lb_add_memory_range(mem, LB_MEM_TABLE, - rom_table_start, rom_table_end-rom_table_start); + table_start, table_end - table_start); + printk(BIOS_DEBUG, "%s: checkpoint 2\n", __func__); #if CONFIG_WRITE_HIGH_TABLES printk(BIOS_DEBUG, "Adding high table area\n"); // should this be LB_MEM_ACPI? lb_add_memory_range(mem, LB_MEM_TABLE, - high_tables_base, high_tables_size); + table_start, table_end - table_start); #endif + printk(BIOS_DEBUG, "%s: checkpoint 3\n", __func__); /* Add reserved regions */ add_lb_reserved(mem); + printk(BIOS_DEBUG, "%s: checkpoint 4\n", __func__); lb_dump_memory_ranges(mem); + printk(BIOS_DEBUG, "%s: checkpoint 5\n", __func__); /* Note: * I assume that there is always memory at immediately after - * the low_table_end. This means that after I setup the coreboot table. + * the table_end. This means that after I setup the coreboot table. * I can trivially fixup the reserved memory ranges to hold the correct * size of the coreboot table. */ + printk(BIOS_DEBUG, "%s: checkpoint 5\n", __func__); + /* FIXME(dhendrix): Most of these do nothing at the moment */ /* Record our motherboard */ lb_mainboard(head); /* Record the serial port, if present */ @@ -695,6 +699,7 @@ unsigned long write_coreboot_table( /* Record our framebuffer */ lb_framebuffer(head); +#if 0 #if CONFIG_CHROMEOS /* Record our GPIO settings (ChromeOS specific) */ lb_gpios(head); @@ -705,9 +710,12 @@ unsigned long write_coreboot_table( /* pass along VBNV offsets in CMOS */ lb_vbnv(head); #endif +#endif add_cbmem_pointers(head); /* Remember where my valid memory ranges are */ - return lb_table_fini(head, 1); + fini = lb_table_fini(head, 1); + printk(BIOS_DEBUG, "%s: DONE: fini is 0x%lx\n", __func__, fini); + return fini; } diff --git a/src/arch/armv7/boot/tables.c b/src/arch/armv7/boot/tables.c index 07c5635..a60ebca 100644 --- a/src/arch/armv7/boot/tables.c +++ b/src/arch/armv7/boot/tables.c @@ -28,6 +28,10 @@ #include <cbmem.h> #include <lib.h> +/* + * TODO: "High" tables are a convention used on x86. Maybe we can + * clean up that naming at some point. + */ uint64_t high_tables_base = 0; uint64_t high_tables_size; @@ -37,59 +41,40 @@ void cbmem_arch_init(void) struct lb_memory *write_tables(void) { - unsigned long low_table_start, low_table_end; - unsigned long rom_table_start, rom_table_end; - - /* Even if high tables are configured, some tables are copied both to - * the low and the high area, so payloads and OSes don't need to know - * about the high tables. - */ - unsigned long high_table_pointer; + unsigned long table_pointer; if (!high_tables_base) { - printk(BIOS_ERR, "ERROR: High Tables Base is not set.\n"); + printk(BIOS_ERR, "ERROR: coreboot_tables_base is not set.\n"); // Are there any boards without? // Stepan thinks we should die() here! } - printk(BIOS_DEBUG, "High Tables Base is %llx.\n", high_tables_base); - - rom_table_start = 0xf0000; - rom_table_end = 0xf0000; - - /* Start low addr at 0x500, so we don't run into conflicts with the BDA - * in case our data structures grow beyound 0x400. Only multiboot, GDT - * and the coreboot table use low_tables. - */ - low_table_start = 0; - low_table_end = 0x500; + printk(BIOS_DEBUG, "high_tables_base: %llx.\n", high_tables_base); #define MAX_COREBOOT_TABLE_SIZE (8 * 1024) post_code(0x9d); - high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, MAX_COREBOOT_TABLE_SIZE); - - if (high_table_pointer) { - unsigned long new_high_table_pointer; - - /* Also put a forwarder entry into 0-4K */ - new_high_table_pointer = write_coreboot_table(low_table_start, low_table_end, - high_tables_base, high_table_pointer); - - if (new_high_table_pointer > (high_table_pointer + - MAX_COREBOOT_TABLE_SIZE)) + table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, + MAX_COREBOOT_TABLE_SIZE); + if (table_pointer) { + unsigned long new_table_pointer; + new_table_pointer = write_coreboot_table(table_pointer, + high_tables_size); + if (table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) { printk(BIOS_ERR, "%s: coreboot table didn't fit (%lx)\n", - __func__, new_high_table_pointer - - high_table_pointer); - - printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", - new_high_table_pointer - high_table_pointer); - } else { + __func__, new_table_pointer - table_pointer); + } + printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", + new_table_pointer - table_pointer); + } +#if 0 + else { /* The coreboot table must be in 0-4K or 960K-1M */ rom_table_end = write_coreboot_table( low_table_start, low_table_end, rom_table_start, rom_table_end); } +#endif post_code(0x9e); diff --git a/src/arch/armv7/include/arch/coreboot_tables.h b/src/arch/armv7/include/arch/coreboot_tables.h index 3c9bf98..e8bb7be 100644 --- a/src/arch/armv7/include/arch/coreboot_tables.h +++ b/src/arch/armv7/include/arch/coreboot_tables.h @@ -5,8 +5,7 @@ /* This file holds function prototypes for building the coreboot table. */ unsigned long write_coreboot_table( - unsigned long low_table_start, unsigned long low_table_end, - unsigned long rom_table_start, unsigned long rom_table_end); + unsigned long table_start, unsigned long table_end); void lb_memory_range(struct lb_memory *mem, uint32_t type, uint64_t start, uint64_t size); diff --git a/src/lib/compute_ip_checksum.c b/src/lib/compute_ip_checksum.c index 48f93d4..8526f6d 100644 --- a/src/lib/compute_ip_checksum.c +++ b/src/lib/compute_ip_checksum.c @@ -1,6 +1,8 @@ #include <stdint.h> #include <ip_checksum.h> +#include <console/console.h> + unsigned long compute_ip_checksum(void *addr, unsigned long length) { uint8_t *ptr; diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 85c05f5..43a11ad 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -114,7 +114,8 @@ void hardwaremain(int boot_complete) timestamp_stash(TS_DEVICE_DONE); #if CONFIG_WRITE_HIGH_TABLES - cbmem_initialize(); + int rc = cbmem_initialize(); + printk(BIOS_DEBUG, "cbmem_initialize returned %d\n", rc); #if CONFIG_CONSOLE_CBMEM cbmemc_reinit(); #endif diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index f9d9c96..d280dbe 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -19,12 +19,21 @@ #include <console/console.h> +#if CONFIG_WRITE_HIGH_TABLES +#include <cbmem.h> +#endif + +void hardwaremain(int boot_complete); void main(void) { -// volatile unsigned long *pshold = (unsigned long *)0x1004330c; -// *pshold &= ~0x100; /* shut down */ - console_init(); printk(BIOS_INFO, "hello from ramstage\n"); - while (1); + +#if CONFIG_WRITE_HIGH_TABLES + /* Leave some space for ACPI tables */ + high_tables_base = CONFIG_RAMBASE; + high_tables_size = CONFIG_RAMBASE + 0x100000; +#endif + + hardwaremain(0); }

1 0

Patch set updated for coreboot: 7ac1720 snow: cleanup ramstage and call hardwaremain()
by Ronald G. Minnich 09 Feb '13

09 Feb '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2302 -gerrit commit 7ac172046b06b6be462b679bc7ba6eaaa12cdb62 Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Feb 6 16:29:42 2013 -0800 snow: cleanup ramstage and call hardwaremain() ** do not submit (work-in-progress) ** It *no longer* dies in write_coreboot_tables(). The trick is that lb_table_fini is more than informational, it writes a record and hence can not be called before any other record has been written, or it writes garbage. Oops. That's a problem with the original too: it assumes at least one record written, which is safe, because there's always one record written. Hence one can not call lb_table_fini just to ask a question. It can only be called once. Note 1: For ARM we can get away with only using one table, the high table and low table distinction is an x86-ism. Note 2: We'll eventually need to fill in the device structure so that search_global_resources() can mark regions appropriately. Fortunately we can get by with the assumption that 0x4000_0000- 0xffff_ffff is plain memory without any IO holes (We'll probably want to specify which regions are IO later on). Change-Id: I30200432535244de971a7cea9f7902f5e9b46403 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/boot/coreboot_table.c | 90 +++++++++++++++------------ src/arch/armv7/boot/tables.c | 59 +++++++----------- src/arch/armv7/include/arch/coreboot_tables.h | 3 +- src/lib/compute_ip_checksum.c | 2 + src/lib/hardwaremain.c | 3 +- src/mainboard/google/snow/ramstage.c | 17 +++-- 6 files changed, 89 insertions(+), 85 deletions(-) diff --git a/src/arch/armv7/boot/coreboot_table.c b/src/arch/armv7/boot/coreboot_table.c index b2d88aa..3acfe16 100644 --- a/src/arch/armv7/boot/coreboot_table.c +++ b/src/arch/armv7/boot/coreboot_table.c @@ -559,11 +559,13 @@ struct lb_memory *get_lb_mem(void) return mem_ranges; } +#if 0 static void build_lb_mem_range(void *gp, struct device *dev, struct resource *res) { struct lb_memory *mem = gp; new_lb_memory_range(mem, LB_MEM_RAM, res->base, res->size); } +#endif static struct lb_memory *build_lb_mem(struct lb_header *head) { @@ -573,11 +575,15 @@ static struct lb_memory *build_lb_mem(struct lb_header *head) mem = lb_memory(head); mem_ranges = mem; + /* FIXME: implement this */ +#if 0 /* Build the raw table of memory */ search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, build_lb_mem_range, mem); - lb_cleanup_memory_ranges(mem); +#endif + /* FIXME: things die in cleanup_memory_ranges(), skip for now */ +// lb_cleanup_memory_ranges(mem); return mem; } @@ -596,47 +602,30 @@ static void add_lb_reserved(struct lb_memory *mem) } unsigned long write_coreboot_table( - unsigned long low_table_start, unsigned long low_table_end, - unsigned long rom_table_start, unsigned long rom_table_end) + unsigned long table_start, unsigned long table_end) { struct lb_header *head; struct lb_memory *mem; + unsigned long fini; -#if CONFIG_WRITE_HIGH_TABLES - printk(BIOS_DEBUG, "Writing high table forward entry at 0x%08lx\n", - low_table_end); - head = lb_table_init(low_table_end); - lb_forward(head, (struct lb_header*)rom_table_end); - - low_table_end = (unsigned long) lb_table_fini(head, 0); - printk(BIOS_DEBUG, "New low_table_end: 0x%08lx\n", low_table_end); - printk(BIOS_DEBUG, "Now going to write high coreboot table at 0x%08lx\n", - rom_table_end); - - head = lb_table_init(rom_table_end); - rom_table_end = (unsigned long)head; - printk(BIOS_DEBUG, "rom_table_end = 0x%08lx\n", rom_table_end); -#else - if(low_table_end > (0x1000 - sizeof(struct lb_header))) { /* after 4K */ - /* We need to put lbtable on to [0xf0000,0x100000) */ - head = lb_table_init(rom_table_end); - rom_table_end = (unsigned long)head; - } else { - head = lb_table_init(low_table_end); - low_table_end = (unsigned long)head; - } -#endif + printk(BIOS_DEBUG, "table_start: 0x%lx, table_end: 0x%lx, ", + table_start, table_end); + head = lb_table_init(table_start); + + printk(BIOS_DEBUG, "writing head (0x%p)... ", head); + printk(BIOS_DEBUG, "Writing table forward entry at 0x%08lx\n", + table_end); + lb_forward(head, (struct lb_header*)table_end); + printk(BIOS_DEBUG, "done\n"); - printk(BIOS_DEBUG, "Adjust low_table_end from 0x%08lx to ", low_table_end); - low_table_end += 0xfff; // 4K aligned - low_table_end &= ~0xfff; - printk(BIOS_DEBUG, "0x%08lx \n", low_table_end); + table_end = (unsigned long) head + head->table_bytes; + printk(BIOS_DEBUG, "New table_end: 0x%08lx\n", table_end); - /* The Linux kernel assumes this region is reserved */ - printk(BIOS_DEBUG, "Adjust rom_table_end from 0x%08lx to ", rom_table_end); - rom_table_end += 0xffff; // 64K align - rom_table_end &= ~0xffff; - printk(BIOS_DEBUG, "0x%08lx \n", rom_table_end); + /* FIXME(dhendrix): do we need this? */ + printk(BIOS_DEBUG, "Adjust table_end from 0x%08lx to ", table_end); + table_end += 0xfff; // 4K aligned + table_end &= ~0xfff; + printk(BIOS_DEBUG, "0x%08lx \n", table_end); #if CONFIG_USE_OPTION_TABLE { @@ -655,35 +644,50 @@ unsigned long write_coreboot_table( } #endif /* Record where RAM is located */ + /* FIXME(dhendrix): add global resources */ + printk(BIOS_DEBUG, "%s: head: 0x%p\n", __func__, head); mem = build_lb_mem(head); + /* FIXME: we seem to get a bogus return value */ + printk(BIOS_DEBUG, "%s: mem: 0x%p\n", __func__, mem); + if ((unsigned long)mem < CONFIG_RAMBASE) { + printk(BIOS_DEBUG, "%s: ZOMG PANIC!!!111n", __func__); + while (1); + } /* Record the mptable and the the lb_table (This will be adjusted later) */ lb_add_memory_range(mem, LB_MEM_TABLE, - low_table_start, low_table_end - low_table_start); + table_start, table_end - table_start); + printk(BIOS_DEBUG, "%s: checkpoint 1\n", __func__); /* Record the pirq table, acpi tables, and maybe the mptable */ lb_add_memory_range(mem, LB_MEM_TABLE, - rom_table_start, rom_table_end-rom_table_start); + table_start, table_end - table_start); + printk(BIOS_DEBUG, "%s: checkpoint 2\n", __func__); #if CONFIG_WRITE_HIGH_TABLES printk(BIOS_DEBUG, "Adding high table area\n"); // should this be LB_MEM_ACPI? lb_add_memory_range(mem, LB_MEM_TABLE, - high_tables_base, high_tables_size); + table_start, table_end - table_start); #endif + printk(BIOS_DEBUG, "%s: checkpoint 3\n", __func__); /* Add reserved regions */ add_lb_reserved(mem); + printk(BIOS_DEBUG, "%s: checkpoint 4\n", __func__); lb_dump_memory_ranges(mem); + printk(BIOS_DEBUG, "%s: checkpoint 5\n", __func__); /* Note: * I assume that there is always memory at immediately after - * the low_table_end. This means that after I setup the coreboot table. + * the table_end. This means that after I setup the coreboot table. * I can trivially fixup the reserved memory ranges to hold the correct * size of the coreboot table. */ + printk(BIOS_DEBUG, "%s: checkpoint 5\n", __func__); + /* FIXME(dhendrix): Most of these do nothing at the moment */ /* Record our motherboard */ lb_mainboard(head); /* Record the serial port, if present */ @@ -695,6 +699,7 @@ unsigned long write_coreboot_table( /* Record our framebuffer */ lb_framebuffer(head); +#if 0 #if CONFIG_CHROMEOS /* Record our GPIO settings (ChromeOS specific) */ lb_gpios(head); @@ -705,9 +710,12 @@ unsigned long write_coreboot_table( /* pass along VBNV offsets in CMOS */ lb_vbnv(head); #endif +#endif add_cbmem_pointers(head); /* Remember where my valid memory ranges are */ - return lb_table_fini(head, 1); + fini = lb_table_fini(head, 1); + printk(BIOS_DEBUG, "%s: DONE: fini is 0x%lx\n", __func__, fini); + return fini; } diff --git a/src/arch/armv7/boot/tables.c b/src/arch/armv7/boot/tables.c index 07c5635..a60ebca 100644 --- a/src/arch/armv7/boot/tables.c +++ b/src/arch/armv7/boot/tables.c @@ -28,6 +28,10 @@ #include <cbmem.h> #include <lib.h> +/* + * TODO: "High" tables are a convention used on x86. Maybe we can + * clean up that naming at some point. + */ uint64_t high_tables_base = 0; uint64_t high_tables_size; @@ -37,59 +41,40 @@ void cbmem_arch_init(void) struct lb_memory *write_tables(void) { - unsigned long low_table_start, low_table_end; - unsigned long rom_table_start, rom_table_end; - - /* Even if high tables are configured, some tables are copied both to - * the low and the high area, so payloads and OSes don't need to know - * about the high tables. - */ - unsigned long high_table_pointer; + unsigned long table_pointer; if (!high_tables_base) { - printk(BIOS_ERR, "ERROR: High Tables Base is not set.\n"); + printk(BIOS_ERR, "ERROR: coreboot_tables_base is not set.\n"); // Are there any boards without? // Stepan thinks we should die() here! } - printk(BIOS_DEBUG, "High Tables Base is %llx.\n", high_tables_base); - - rom_table_start = 0xf0000; - rom_table_end = 0xf0000; - - /* Start low addr at 0x500, so we don't run into conflicts with the BDA - * in case our data structures grow beyound 0x400. Only multiboot, GDT - * and the coreboot table use low_tables. - */ - low_table_start = 0; - low_table_end = 0x500; + printk(BIOS_DEBUG, "high_tables_base: %llx.\n", high_tables_base); #define MAX_COREBOOT_TABLE_SIZE (8 * 1024) post_code(0x9d); - high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, MAX_COREBOOT_TABLE_SIZE); - - if (high_table_pointer) { - unsigned long new_high_table_pointer; - - /* Also put a forwarder entry into 0-4K */ - new_high_table_pointer = write_coreboot_table(low_table_start, low_table_end, - high_tables_base, high_table_pointer); - - if (new_high_table_pointer > (high_table_pointer + - MAX_COREBOOT_TABLE_SIZE)) + table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, + MAX_COREBOOT_TABLE_SIZE); + if (table_pointer) { + unsigned long new_table_pointer; + new_table_pointer = write_coreboot_table(table_pointer, + high_tables_size); + if (table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) { printk(BIOS_ERR, "%s: coreboot table didn't fit (%lx)\n", - __func__, new_high_table_pointer - - high_table_pointer); - - printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", - new_high_table_pointer - high_table_pointer); - } else { + __func__, new_table_pointer - table_pointer); + } + printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", + new_table_pointer - table_pointer); + } +#if 0 + else { /* The coreboot table must be in 0-4K or 960K-1M */ rom_table_end = write_coreboot_table( low_table_start, low_table_end, rom_table_start, rom_table_end); } +#endif post_code(0x9e); diff --git a/src/arch/armv7/include/arch/coreboot_tables.h b/src/arch/armv7/include/arch/coreboot_tables.h index 3c9bf98..e8bb7be 100644 --- a/src/arch/armv7/include/arch/coreboot_tables.h +++ b/src/arch/armv7/include/arch/coreboot_tables.h @@ -5,8 +5,7 @@ /* This file holds function prototypes for building the coreboot table. */ unsigned long write_coreboot_table( - unsigned long low_table_start, unsigned long low_table_end, - unsigned long rom_table_start, unsigned long rom_table_end); + unsigned long table_start, unsigned long table_end); void lb_memory_range(struct lb_memory *mem, uint32_t type, uint64_t start, uint64_t size); diff --git a/src/lib/compute_ip_checksum.c b/src/lib/compute_ip_checksum.c index 48f93d4..8526f6d 100644 --- a/src/lib/compute_ip_checksum.c +++ b/src/lib/compute_ip_checksum.c @@ -1,6 +1,8 @@ #include <stdint.h> #include <ip_checksum.h> +#include <console/console.h> + unsigned long compute_ip_checksum(void *addr, unsigned long length) { uint8_t *ptr; diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 85c05f5..43a11ad 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -114,7 +114,8 @@ void hardwaremain(int boot_complete) timestamp_stash(TS_DEVICE_DONE); #if CONFIG_WRITE_HIGH_TABLES - cbmem_initialize(); + int rc = cbmem_initialize(); + printk(BIOS_DEBUG, "cbmem_initialize returned %d\n", rc); #if CONFIG_CONSOLE_CBMEM cbmemc_reinit(); #endif diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index f9d9c96..d280dbe 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -19,12 +19,21 @@ #include <console/console.h> +#if CONFIG_WRITE_HIGH_TABLES +#include <cbmem.h> +#endif + +void hardwaremain(int boot_complete); void main(void) { -// volatile unsigned long *pshold = (unsigned long *)0x1004330c; -// *pshold &= ~0x100; /* shut down */ - console_init(); printk(BIOS_INFO, "hello from ramstage\n"); - while (1); + +#if CONFIG_WRITE_HIGH_TABLES + /* Leave some space for ACPI tables */ + high_tables_base = CONFIG_RAMBASE; + high_tables_size = CONFIG_RAMBASE + 0x100000; +#endif + + hardwaremain(0); }

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Patch set updated for filo: 615549e Show coreboot version in FILO header
by Patrick Georgi 09 Feb '13

09 Feb '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2324 -gerrit commit 615549ea0b062e421c30fbe1a29981c0c8082a3d Author: Mathias Krause <mathias.krause(a)secunet.com> Date: Thu Oct 20 14:07:31 2011 +0200 Show coreboot version in FILO header Add get_cb_version(). Print coreboot version in the FILO header. Change-Id: I9a8831e574f71a22a10f10e7946062019ebb0e9f Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- include/sys_info.h | 1 + main/filo.c | 1 + main/grub/char_io.c | 4 ++-- x86/sys_info.c | 8 ++++++++ 4 files changed, 12 insertions(+), 2 deletions(-) diff --git a/include/sys_info.h b/include/sys_info.h index f9af89e..33fc785 100644 --- a/include/sys_info.h +++ b/include/sys_info.h @@ -42,6 +42,7 @@ struct sys_info { void collect_sys_info(struct sys_info *info); void collect_elfboot_info(struct sys_info *info); void collect_linuxbios_info(struct sys_info *info); +const char *get_cb_version(void); /* Our name and version. I want to see single instance of these in the image */ extern const char *program_name, *program_version; diff --git a/main/filo.c b/main/filo.c index 3187165..7d83d80 100644 --- a/main/filo.c +++ b/main/filo.c @@ -68,6 +68,7 @@ static void init(void) /* Set up the consoles. */ console_init(); + printf("coreboot: %s\n", get_cb_version()); printf("%s version %s\n", program_name, program_version); collect_sys_info(&sys_info); relocate(); diff --git a/main/grub/char_io.c b/main/grub/char_io.c index f37cc23..fec3387 100644 --- a/main/grub/char_io.c +++ b/main/grub/char_io.c @@ -100,8 +100,8 @@ void init_page(void) { color_set(1, NULL); cls(); - grub_printf("\n %s %s\n", - PROGRAM_NAME, PROGRAM_VERSION); + grub_printf("\n %s %s, coreboot: %s\n", + PROGRAM_NAME, PROGRAM_VERSION, get_cb_version()); grub_printf(" root_dev = %s\n", root_device[0] ? root_device : "unset"); } diff --git a/x86/sys_info.c b/x86/sys_info.c index 8e7d14e..68450ae 100644 --- a/x86/sys_info.c +++ b/x86/sys_info.c @@ -32,3 +32,11 @@ void collect_sys_info(struct sys_info *info) debug("boot EBX = %#lx\n", info->boot_data); debug("boot arg = %#lx\n", info->boot_arg); } + +const char *get_cb_version() +{ + const char *cb_version = lib_sysinfo.cb_version ? + lib_sysinfo.cb_version : "<unknown version>"; + + return cb_version; +}

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Patch merged into coreboot/master: 22ae2b9 VBE: Skip graphics mode setting for non-VGA devices
by gerrit＠coreboot.org 09 Feb '13

09 Feb '13

the following patch was just integrated into master: commit 22ae2b937856d6927216d88b7f61b7623eabdb8c Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Feb 8 08:48:20 2013 -0800 VBE: Skip graphics mode setting for non-VGA devices This hit me when running the latest Qemu with coreboot: First the graphics OPROM is running, then an iPXE OPROM. The iPXE OPROM has no int10 support (obviously) so calling vbe_set_graphics() wipes the framebuffer information from the coreboot table. Change-Id: Ie0453c4a908ea4a6216158f663407a3e72ce4d34 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/2325 Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Feb 8 17:55:47 2013, giving +2 Build-Tested: build bot (Jenkins) at Fri Feb 8 17:59:31 2013, giving +1 See http://review.coreboot.org/2325 for details. -gerrit

1 0

New patch to review for coreboot: fc342bf VBE: Skip graphics mode setting for non-VGA devices
by Stefan Reinauer 09 Feb '13

09 Feb '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2325 -gerrit commit fc342bfdac1e1037ff02459071cc72f35bf95ff4 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Feb 8 08:48:20 2013 -0800 VBE: Skip graphics mode setting for non-VGA devices This hit me when running the latest Qemu with coreboot: First the graphics OPROM is running, then an iPXE OPROM. The iPXE OPROM has no int10 support (obviously) so calling vbe_set_graphics() wipes the framebuffer information from the coreboot table. Change-Id: Ie0453c4a908ea4a6216158f663407a3e72ce4d34 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/device/oprom/realmode/x86.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 6e76992..5fd11b5 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -34,6 +34,7 @@ /* we use x86emu's register file representation */ #include <x86emu/regs.h> #include <boot/coreboot_tables.h> +#include <device/pci_ids.h> /* to have a common register file for interrupt handlers */ X86EMU_sysEnv _X86EMU_env; @@ -322,7 +323,8 @@ void run_bios(struct device *dev, unsigned long addr) printk(BIOS_DEBUG, "... Option ROM returned.\n"); #if CONFIG_FRAMEBUFFER_SET_VESA_MODE - vbe_set_graphics(); + if ((dev->class >> 8)== PCI_CLASS_DISPLAY_VGA) + vbe_set_graphics(); #endif }

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coreboot February 2013