coreboot February 2013

coreboot@coreboot.org

27 participants
790 discussions

Patch set updated for coreboot: bc3fd08 AMD S3: Add missing erasing flash sector for saving MTRR register
by Zheng Bao 10 Feb '13

10 Feb '13

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2304 -gerrit commit bc3fd08824e572377f8093dc40db7980d64b6563 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Sun Feb 10 21:20:39 2013 +0800 AMD S3: Add missing erasing flash sector for saving MTRR register It has worked up to now because the region is already erased the first time the board boots, and every additional boot the same data is being written over the old data.(by Dave Frodin) Change-Id: Id334c60668e31d23c1d552d0ace8eb6ae5513e6b Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 7069c77..5b4c2c3 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -168,6 +168,8 @@ void OemAgesaSaveMtrr(void) flash->spi->rw = SPI_WRITE_FLAG; spi_claim_bus(flash->spi); + flash->erase(flash, S3_DATA_MTRR_POS, S3_DATA_MTRR_SIZE); + /* Enable access to AMD RdDram and WrDram extension bits */ msr_data = rdmsr(SYS_CFG); msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn;

1 0

Patch set updated for coreboot: 7d13d8a AMD S3: Change the hardcoded data size to macros.
by Zheng Bao 10 Feb '13

10 Feb '13

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2303 -gerrit commit 7d13d8a269daa68a0e8047f27f589013bef4747f Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Sun Feb 10 21:10:52 2013 +0800 AMD S3: Change the hardcoded data size to macros. Change-Id: Ieefc4213a6dee9c399826b1daa98bbf4bc10d881 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 4 ++-- src/cpu/amd/agesa/s3_resume.h | 8 ++++++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 42e950f..7069c77 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -283,9 +283,9 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) spi_claim_bus(flash->spi); if (S3DataType == S3DataTypeNonVolatile) { - flash->erase(flash, S3_DATA_NONVOLATILE_POS, 0x1000); + flash->erase(flash, S3_DATA_NONVOLATILE_POS, S3_DATA_NONVOLATILE_SIZE); } else { - flash->erase(flash, S3_DATA_VOLATILE_POS, 0x6000); + flash->erase(flash, S3_DATA_VOLATILE_POS, S3_DATA_VOLATILE_SIZE); } nvram_pos = 0; diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h index 10bc826..39ad30a 100644 --- a/src/cpu/amd/agesa/s3_resume.h +++ b/src/cpu/amd/agesa/s3_resume.h @@ -20,9 +20,13 @@ #ifndef S3_RESUME_H #define S3_RESUME_H -#define S3_DATA_NONVOLATILE_POS (CONFIG_S3_VOLATILE_POS + 0x7000) +/* The size needs to be 4k aligned, which is the sector size of most flashes. */ +#define S3_DATA_VOLATILE_SIZE 0x6000 +#define S3_DATA_MTRR_SIZE 0x1000 +#define S3_DATA_NONVOLATILE_SIZE 0x1000 #define S3_DATA_VOLATILE_POS CONFIG_S3_VOLATILE_POS -#define S3_DATA_MTRR_POS (CONFIG_S3_VOLATILE_POS + 0x6000) +#define S3_DATA_MTRR_POS (CONFIG_S3_VOLATILE_POS + S3_DATA_VOLATILE_SIZE) +#define S3_DATA_NONVOLATILE_POS (CONFIG_S3_VOLATILE_POS + S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE) typedef enum { S3DataTypeNonVolatile=0, ///< NonVolatile Data Type

1 0

Patch set updated for coreboot: 0350a7a build system: Don't run the full build system on "make clean"
by Patrick Georgi 10 Feb '13

10 Feb '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2338 -gerrit commit 0350a7ab7d101e5b27f24b23bac7aace33d7eaa6 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Feb 9 15:45:02 2013 +0100 build system: Don't run the full build system on "make clean" When running "make clean" the build system used to parse the entire build system. Besides costing time, it prevents cleaning the tree if a blobs-board is selected but blobs are not enabled. Instead, clean always removes all of $(obj) and .xcompile, while distclean additionally removes .config and the like. Besides cleaning up more completely (eg. dependency files), a side effect is that this also removes $(obj)/util, if it exists (default location for build tools). Change-Id: Ief6362460d4eb7edcb4b0a47ec76cb9a61bf3b86 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- Makefile | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/Makefile b/Makefile index 527fbcc..92b4d0b 100644 --- a/Makefile +++ b/Makefile @@ -97,10 +97,10 @@ ifeq ($(strip $(HAVE_DOTCONFIG)),) NOCOMPILE:=1 endif ifneq ($(MAKECMDGOALS),) -ifneq ($(filter %config distclean,$(MAKECMDGOALS)),) +ifneq ($(filter %config %clean,$(MAKECMDGOALS)),) NOCOMPILE:=1 endif -ifeq ($(MAKECMDGOALS), distclean) +ifeq ($(MAKECMDGOALS), %clean) NOMKDIR:=1 endif endif @@ -299,9 +299,7 @@ doxygen-clean: rm -rf $(DOXYGEN_OUTPUT_DIR) clean-for-update: doxygen-clean clean-for-update-target - rm -f $(allobjs) .xcompile - rm -f $(DEPENDENCIES) - rmdir -p $(alldirs) 2>/dev/null >/dev/null || true + rm -rf $(obj) .xcompile clean: clean-for-update clean-target rm -f .ccwrap @@ -309,8 +307,7 @@ clean: clean-for-update clean-target clean-cscope: rm -f cscope.out -distclean: - rm -rf $(obj) +distclean: clean rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig* .ccwrap .xcompile -.PHONY: $(PHONY) clean clean-cscope cscope distclean doxygen doxy .xcompile +.PHONY: $(PHONY) clean clean-for-update clean-cscope cscope distclean doxygen doxy .xcompile

1 0

Patch set updated for coreboot: abb6747 Intel: Replace MSR 0xcd with MSR_FSB_FREQ
by Patrick Georgi 10 Feb '13

10 Feb '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2339 -gerrit commit abb6747f7a46698f055bd9debead3e3cd6928e0d Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Feb 9 15:56:04 2013 +0100 Intel: Replace MSR 0xcd with MSR_FSB_FREQ And move the corresponding #define to speedstep.h Change-Id: I8c884b8ab9ba54e01cfed7647a59deafeac94f2d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/cpu/intel/model_1067x/model_1067x_init.c | 1 - src/cpu/intel/speedstep/acpi.c | 2 +- src/cpu/x86/lapic/apic_timer.c | 5 +++-- src/include/cpu/intel/speedstep.h | 3 +++ src/northbridge/intel/gm45/delay.c | 3 ++- src/northbridge/intel/i3100/raminit.c | 3 ++- src/northbridge/intel/i3100/raminit_ep80579.c | 5 +++-- src/northbridge/intel/i5000/raminit.c | 3 ++- src/northbridge/intel/i5000/udelay.c | 3 ++- src/northbridge/intel/i945/udelay.c | 3 ++- 10 files changed, 20 insertions(+), 11 deletions(-) diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index e81a6a7..c821474 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -99,7 +99,6 @@ static void enable_vmx(void) } #define MSR_BBL_CR_CTL3 0x11e -#define MSR_FSB_FREQ 0xcd static void configure_c_states(const int quad) { diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 910055d..dfcc82e 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -67,7 +67,7 @@ static int determine_total_number_of_cores(void) */ static int get_fsb(void) { - const u32 fsbcode = rdmsr(0xcd).lo & 7; + const u32 fsbcode = rdmsr(MSR_FSB_FREQ).lo & 7; switch (fsbcode) { case 0: return 800; /* / 3 == 266 */ case 1: return 400; /* / 3 == 133 */ diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 53209fb..93e948f 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -25,6 +25,7 @@ #include <cpu/x86/car.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> +#include <cpu/intel/speedstep.h> /* NOTE: This code uses global variables, so it can not be used during * memory init. @@ -53,11 +54,11 @@ static int set_timer_fsb(void) switch (c.x86_model) { case 0xe: /* Core Solo/Duo */ case 0x1c: /* Atom */ - timer_fsb = core_fsb[rdmsr(0xcd).lo & 7]; + timer_fsb = core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; break; case 0xf: /* Core 2 or Xeon */ case 0x17: /* Enhanced Core */ - timer_fsb = core2_fsb[rdmsr(0xcd).lo & 7]; + timer_fsb = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; break; case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/ case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/ diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index 86778b1..f4c4d72 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -45,6 +45,7 @@ #define IA32_PERF_CTL 0x199 #define MSR_THERM2_CTL 0x19D #define IA32_MISC_ENABLES 0x1A0 +#define MSR_FSB_FREQ 0xcd #define MSR_FSB_CLOCK_VCC 0xce #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_BASE_ADDR 0xe3 @@ -104,7 +105,9 @@ typedef struct { int num_states; } sst_table_t; +#ifndef __ROMCC__ void speedstep_gen_pstates(sst_table_t *); +#endif #define SPEEDSTEP_MAX_POWER_YONAH 31000 #define SPEEDSTEP_MIN_POWER_YONAH 13100 diff --git a/src/northbridge/intel/gm45/delay.c b/src/northbridge/intel/gm45/delay.c index 50bea2c..c33bbe2 100644 --- a/src/northbridge/intel/gm45/delay.c +++ b/src/northbridge/intel/gm45/delay.c @@ -21,6 +21,7 @@ #include <stdint.h> #include <cpu/x86/tsc.h> #include <cpu/x86/msr.h> +#include <cpu/intel/speedstep.h> #include "delay.h" /* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ @@ -45,7 +46,7 @@ static void _udelay(const u32 us, const u32 numerator, const int total) u32 fsb = 0, divisor; u32 d; /* ticks per us */ - msr = rdmsr(0xcd); + msr = rdmsr(MSR_FSB_FREQ); switch (msr.lo & 0x07) { case 5: fsb = 400; diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c index b453e8b..fa42efc 100644 --- a/src/northbridge/intel/i3100/raminit.c +++ b/src/northbridge/intel/i3100/raminit.c @@ -21,6 +21,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> +#include <cpu/intel/speedstep.h> #include <stdlib.h> #include "raminit.h" #include "i3100.h" @@ -583,7 +584,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, drc |= (1 << 4); /* independent clocks */ /* set front side bus speed */ - msr = rdmsr(0xcd); /* returns 0 on Pentium M 90nm */ + msr = rdmsr(MSR_FSB_FREQ); /* returns 0 on Pentium M 90nm */ value = msr.lo & 0x07; drc &= ~(3 << 2); drc |= (fsb_conversion[value] << 2); diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 5fe206f..4c688d5 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -20,6 +20,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> +#include <cpu/intel/speedstep.h> #include "raminit_ep80579.h" #include "ep80579.h" @@ -441,8 +442,8 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, /* TODO check: */ /* set front side bus speed */ - msr = rdmsr(0xcd); /* returns 0 on Pentium M 90nm */ - print_debug("msr 0xcd = "); + msr = rdmsr(MSR_FSB_FREQ); /* returns 0 on Pentium M 90nm */ + print_debug("MSR FSB_FREQ(0xcd) = "); print_debug_hex32(msr.hi); print_debug_hex32(msr.lo); print_debug("\n"); diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c index ffc579a..3c913cf 100644 --- a/src/northbridge/intel/i5000/raminit.c +++ b/src/northbridge/intel/i5000/raminit.c @@ -25,6 +25,7 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> +#include <cpu/intel/speedstep.h> #include <console/console.h> #include <spd.h> #include <types.h> @@ -1560,7 +1561,7 @@ static int i5000_setup_clocking(struct i5000_fbd_setup *setup) return 1; } - msr = rdmsr(0xcd); + msr = rdmsr(MSR_FSB_FREQ); switch(msr.lo & 7) { case 1: diff --git a/src/northbridge/intel/i5000/udelay.c b/src/northbridge/intel/i5000/udelay.c index 6462fe0..ff2da6f 100644 --- a/src/northbridge/intel/i5000/udelay.c +++ b/src/northbridge/intel/i5000/udelay.c @@ -21,6 +21,7 @@ #include <stdint.h> #include <cpu/x86/tsc.h> #include <cpu/x86/msr.h> +#include <cpu/intel/speedstep.h> #include <console/console.h> /** * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock @@ -35,7 +36,7 @@ void udelay(u32 us) u32 d; /* ticks per us */ u32 dn = 0x1000000 / 2; /* how many us before we need to use hi */ - msr = rdmsr(0xcd); + msr = rdmsr(MSR_FSB_FREQ); switch (msr.lo & 0x07) { case 5: fsb = 400; diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c index ce5e9d8..be56008 100644 --- a/src/northbridge/intel/i945/udelay.c +++ b/src/northbridge/intel/i945/udelay.c @@ -22,6 +22,7 @@ #include <stdint.h> #include <cpu/x86/tsc.h> #include <cpu/x86/msr.h> +#include <cpu/intel/speedstep.h> /* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) @@ -46,7 +47,7 @@ void udelay(u32 us) u32 fsb = 0, divisor; u32 d; /* ticks per us */ - msr = rdmsr(0xcd); + msr = rdmsr(MSR_FSB_FREQ); switch (msr.lo & 0x07) { case 5: fsb = 400;

1 0

Patch merged into coreboot/master: a40435a armv7/snow: Remove unused modules in bootblock and romstage.
by gerrit＠coreboot.org 10 Feb '13

10 Feb '13

the following patch was just integrated into master: commit a40435af84c5cd2175b842ff0cbd9d1e909c2ce6 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Fri Feb 8 13:49:10 2013 +0800 armv7/snow: Remove unused modules in bootblock and romstage. For Exynos/snow, cpu_info and power modules and also some parts of the GPIO API (which require timer and pwm modules) are not used in the current bootblock. Clock init only needs to be used if early console is enabled. Now our bootblock is 22420 bytes with early serial console and 11192 bytes without. Those include the 8KB BL1 region. Change-Id: I9c958dafb9cf522df0dcfbef373ce741aa162544 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2322 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sun Feb 10 02:50:46 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sun Feb 10 04:04:50 2013, giving +2 See http://review.coreboot.org/2322 for details. -gerrit

1 0

Patch merged into coreboot/master: 0b153bd exynos/snow: move SPI GPIO setup to mainboard bootblock code
by gerrit＠coreboot.org 10 Feb '13

10 Feb '13

the following patch was just integrated into master: commit 0b153bdda97fad6033a1d5aea58af1dd9df6125d Author: David Hendricks <dhendrix(a)chromium.org> Date: Sat Feb 9 17:24:17 2013 -0800 exynos/snow: move SPI GPIO setup to mainboard bootblock code This moves GPIO setup from chip-specific SPI code to mainboard- specific bootblock code. This makes exynos_spi_open a bit more generic so it can eventually be used for any SPI channel. This also benefits CBFS since the user can set media->context to to any set of SPI registers. Change-Id: I2bcb9de370df0a79353c14b4d021b471ddebfacd Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2347 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sun Feb 10 03:06:21 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sun Feb 10 04:03:28 2013, giving +2 See http://review.coreboot.org/2347 for details. -gerrit

1 0

Patch merged into coreboot/master: 0f7b400 exynos/snow: set SPI clock rate in romstage main
by gerrit＠coreboot.org 10 Feb '13

10 Feb '13

the following patch was just integrated into master: commit 0f7b400f2e3497cf37758f4b14040930bea22391 Author: David Hendricks <dhendrix(a)chromium.org> Date: Sat Feb 9 16:42:23 2013 -0800 exynos/snow: set SPI clock rate in romstage main This moves the setting of SPI clock rate into romstage's main, which allows us to eliminate a bunch of dependencies from the bootblock (about 7KB worth). Change-Id: I371499bb4af6a6aa838294bc56f9dbc21864957a Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2346 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sun Feb 10 02:58:51 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sun Feb 10 04:02:46 2013, giving +2 See http://review.coreboot.org/2346 for details. -gerrit

1 0

Patch set updated for coreboot: bc47a3f exynos/snow: move SPI GPIO setup to mainboard bootblock code
by David Hendricks 10 Feb '13

10 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2347 -gerrit commit bc47a3fa62ec2d873f2c32352e23e8ef315cb839 Author: David Hendricks <dhendrix(a)chromium.org> Date: Sat Feb 9 17:24:17 2013 -0800 exynos/snow: move SPI GPIO setup to mainboard bootblock code This moves GPIO setup from chip-specific SPI code to mainboard- specific bootblock code. This makes exynos_spi_open a bit more generic so it can eventually be used for any SPI channel. This also benefits CBFS since the user can set media->context to to any set of SPI registers. Change-Id: I2bcb9de370df0a79353c14b4d021b471ddebfacd Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5-common/spi.c | 11 +---------- src/mainboard/google/snow/bootblock.c | 1 + 2 files changed, 2 insertions(+), 10 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/spi.c b/src/cpu/samsung/exynos5-common/spi.c index 0e5d5e5..8192737 100644 --- a/src/cpu/samsung/exynos5-common/spi.c +++ b/src/cpu/samsung/exynos5-common/spi.c @@ -81,20 +81,11 @@ static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo, } } +/* set up SPI channel */ int exynos_spi_open(struct exynos_spi *regs) { /* set the spi1 GPIO */ - // TODO Some of these should be done in board's bootblock file. - // We should fix-up the mainboard-specific vs. exynos-specific parts in a - // follow-up CL. - -// exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE); - gpio_cfg_pin(GPIO_A24, 0x2); - gpio_cfg_pin(GPIO_A25, 0x2); - gpio_cfg_pin(GPIO_A26, 0x2); - gpio_cfg_pin(GPIO_A27, 0x2); - /* set pktcnt and enable it */ writel(4 | SPI_PACKET_CNT_EN, &regs->pkt_cnt); /* set FB_CLK_SEL */ diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 9725af3..17a3267 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -30,6 +30,7 @@ void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) { + exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE); #if CONFIG_EARLY_CONSOLE exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); console_init();

1 0

Patch set updated for coreboot: f59f356 exynos/snow: set SPI clock rate in romstage main
by David Hendricks 10 Feb '13

10 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2346 -gerrit commit f59f3567a06109971261c5d105b7332f4c331c94 Author: David Hendricks <dhendrix(a)chromium.org> Date: Sat Feb 9 16:42:23 2013 -0800 exynos/snow: set SPI clock rate in romstage main This moves the setting of SPI clock rate into romstage's main, which allows us to eliminate a bunch of dependencies from the bootblock (about 7KB worth). Change-Id: I371499bb4af6a6aa838294bc56f9dbc21864957a Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5-common/spi.c | 1 - src/mainboard/google/snow/romstage.c | 4 ++++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/cpu/samsung/exynos5-common/spi.c b/src/cpu/samsung/exynos5-common/spi.c index 90b74c0..0e5d5e5 100644 --- a/src/cpu/samsung/exynos5-common/spi.c +++ b/src/cpu/samsung/exynos5-common/spi.c @@ -83,7 +83,6 @@ static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo, int exynos_spi_open(struct exynos_spi *regs) { - clock_set_rate(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ /* set the spi1 GPIO */ // TODO Some of these should be done in board's bootblock file. diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index c0bb6f4..719337b 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -24,8 +24,10 @@ #include <cbfs.h> #include <common.h> +#include <cpu/samsung/exynos5250/clk.h> #include <cpu/samsung/exynos5250/dmc.h> #include <cpu/samsung/exynos5250/setup.h> +#include <cpu/samsung/exynos5250/periph.h> #include <cpu/samsung/exynos5250/clock_init.h> #include <console/console.h> @@ -53,6 +55,8 @@ void main(void) int ret; void *entry; + clock_set_rate(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ + /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ mem = get_mem_timings();

1 0

Patch set updated for coreboot: 4d49eb9 armv7/snow: Remove unused modules in bootblock and romstage.
by David Hendricks 10 Feb '13

10 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2322 -gerrit commit 4d49eb9050d77567c77bdffc73e5c12852cd209c Author: Hung-Te Lin <hungte(a)chromium.org> Date: Fri Feb 8 13:49:10 2013 +0800 armv7/snow: Remove unused modules in bootblock and romstage. For Exynos/snow, cpu_info and power modules and also some parts of the GPIO API (which require timer and pwm modules) are not used in the current bootblock. Clock init only needs to be used if early console is enabled. Now our bootblock is 22420 bytes with early serial console and 11192 bytes without. Those include the 8KB BL1 region. Change-Id: I9c958dafb9cf522df0dcfbef373ce741aa162544 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/Makefile.inc | 15 ++++++--------- src/cpu/samsung/s5p-common/Makefile.inc | 5 ++--- src/cpu/samsung/s5p-common/s5p_gpio.c | 7 +++++++ 3 files changed, 15 insertions(+), 12 deletions(-) diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 13baa7e..0a58c0c 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -3,23 +3,20 @@ # image outside of CBFS #INTERMEDIATE += exynos5250_add_bl1 -# Clock init is done in bootblock to support UART output for -# debugging. We may add a Kconfig option to disable clock init -# in the bootblock and try moving it entirely into romstage. -bootblock-y += clock_init.c -bootblock-y += clock.c bootblock-y += pinmux.c -bootblock-y += soc.c +# Clock is required for UART +bootblock-$(CONFIG_EARLY_CONSOLE) += clock_init.c +bootblock-$(CONFIG_EARLY_CONSOLE) += clock.c +bootblock-$(CONFIG_EARLY_CONSOLE) += soc.c bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c romstage-y += clock.c romstage-y += clock_init.c +romstage-y += pinmux.c # required by s3c24x0_i2c (s5p-common) and uart. romstage-y += exynos_cache.c -romstage-y += pinmux.c -romstage-y += power.c -romstage-y += soc.c romstage-y += dmc_common.c romstage-y += dmc_init_ddr3.c +romstage-$(CONFIG_EARLY_CONSOLE) += soc.c romstage-$(CONFIG_EARLY_CONSOLE) += uart.c #ramstage-y += tzpc_init.c diff --git a/src/cpu/samsung/s5p-common/Makefile.inc b/src/cpu/samsung/s5p-common/Makefile.inc index 0f4200c..118dd47 100644 --- a/src/cpu/samsung/s5p-common/Makefile.inc +++ b/src/cpu/samsung/s5p-common/Makefile.inc @@ -1,8 +1,7 @@ -bootblock-y += pwm.c bootblock-y += s5p_gpio.c -bootblock-y += timer.c +bootblock-$(CONFIG_EARLY_CONSOLE) += pwm.c +bootblock-$(CONFIG_EARLY_CONSOLE) += timer.c -romstage-y += cpu_info.c romstage-y += pwm.c # needed by timer.c romstage-y += s5p_gpio.c romstage-y += timer.c diff --git a/src/cpu/samsung/s5p-common/s5p_gpio.c b/src/cpu/samsung/s5p-common/s5p_gpio.c index e91b9df..8daae59 100644 --- a/src/cpu/samsung/s5p-common/s5p_gpio.c +++ b/src/cpu/samsung/s5p-common/s5p_gpio.c @@ -414,6 +414,12 @@ int gpio_set_value(unsigned gpio, int value) */ #define GPIO_DELAY_US 5 +#ifndef __BOOT_BLOCK__ +/* + * FIXME(dhendrix): These functions use udelay, which has dependencies on + * pwm code and timer code. These aren't necessary for the bootblock and + * bloat the image significantly. + */ int gpio_read_mvl3(unsigned gpio) { int high, low; @@ -476,6 +482,7 @@ int gpio_decode_number(unsigned gpio_list[], int count) return result; } +#endif /* __BOOT_BLOCK__ */ static const char *get_cfg_name(int cfg) {

1 0

← Newer
1
...
46
47
48
49
50
51
52
...
79
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot February 2013