coreboot February 2013

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Patch set updated for coreboot: 18ada84 Supermicro H8QGI: Substract 1 from MMCONF range limit
by Aladyshev Konstantin 11 Feb '13

11 Feb '13

Aladyshev Konstantin (kostr(a)list.ru) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2193 -gerrit commit 18ada84adb0940ef6e77ef598fa1214c4e3404b0 Author: Konstantin Aladyshev <aladyshev(a)nicevt.ru> Date: Fri Jan 25 19:20:51 2013 +0400 Supermicro H8QGI: Substract 1 from MMCONF range limit MMCONF space is defined by two config parameters: MMCONF_BASE_ADDRESS (0xF800 0000) MMCONF_BUS_NUMBER (64) Coreboot allocates 1MB per bus, so MMCONF limit should be: 0xF800 0000 + 64*(0x0010 0000) - 1 = 0xFBFF FFFF Current code does not have (-1) component, this makes MMCONF limit equal 0xFC00 FFFF. Not 0xFC00 0000, because according to BKDG lower two bytes of MMIO limit always equal 0xFFFF: MMIOLimit = {MMIOLimitRegister[47:16], FFFFh}. Add (-1) to correct this issue. No functionality change has been experienced. The five times slower RAM speed compared to the proprietary vendor BIOS still remains. Change-Id: I2c6494c28bb8d36e54ceb2aa7d8d965b0103cbe9 Signed-off-by: Konstantin Aladyshev <aladyshev(a)nicevt.ru> --- src/mainboard/supermicro/h8qgi/agesawrapper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c index 9720bed..517e136 100644 --- a/src/mainboard/supermicro/h8qgi/agesawrapper.c +++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c @@ -147,7 +147,7 @@ static UINT32 agesawrapper_amdinitcpuio(VOID) * coreboot not implemente the range by range setting yet. */ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xBC); - PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000);//1MB each bus + PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1;//1MB each bus PciData = (PciData >> 8) & 0xFFFFFF00; PciData |= 0x80; //NP PciData |= sblink << 4;

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Patch merged into coreboot/master: 3b19cba AMD/Persimmon: Enable the 2nd COM port
by gerrit＠coreboot.org 11 Feb '13

11 Feb '13

the following patch was just integrated into master: commit 3b19cbae37ab340bd530e35412800a171733fda6 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Fri Feb 8 13:16:58 2013 -0700 AMD/Persimmon: Enable the 2nd COM port The hardware is there, so turn it on. Change-Id: I40aff1e84a22a05599c62b9f0b20397df0a40b15 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2353 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Mon Feb 11 16:18:01 2013, giving +2 See http://review.coreboot.org/2353 for details. -gerrit

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New patch to review for coreboot: b9fb4fe AMD/Persimmon: Enable the 2nd COM port
by Dave Frodin 11 Feb '13

11 Feb '13

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2353 -gerrit commit b9fb4fe05705f5f15ec3cf3b9b00a27638ce1a06 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Fri Feb 8 13:16:58 2013 -0700 AMD/Persimmon: Enable the 2nd COM port The hardware is there, so turn it on. Change-Id: I40aff1e84a22a05599c62b9f0b20397df0a40b15 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/mainboard/amd/persimmon/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb index bd40a43..12cb62f 100644 --- a/src/mainboard/amd/persimmon/devicetree.cb +++ b/src/mainboard/amd/persimmon/devicetree.cb @@ -75,7 +75,7 @@ chip northbridge/amd/agesa/family14/root_complex io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 4e.11 off # COM2 + device pnp 4e.11 on # COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end

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Trac reminder: list of new ticket(s)
by coreboot tracker 11 Feb '13

11 Feb '13

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Patch merged into coreboot/master: ebae438 crossgcc: Support hosts using non-GNU make as default make.
by gerrit＠coreboot.org 11 Feb '13

11 Feb '13

the following patch was just integrated into master: commit ebae438bf25514fe058aa9262adfe6625786da43 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Sat Feb 9 13:08:03 2013 +0800 crossgcc: Support hosts using non-GNU make as default make. On hosts using non-GNU make as default make program (ex, FreeBSD's default is BSD make and having GNU make as "gmake"), building acpica will fail. We should use the correct path of make $(MAKE). Verified to build on FreeBSD 9.0 with gcc 4.7 from ports. Note, the shipped gcc in FreeBSD 9.0 is 4.2.1 and needs more patches to remove -Wbad-function-case and -Wempty-body. That should be fixed in a future patch. Change-Id: Iacbf5a05e84a8a53d9d3e783a10131de603282c9 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: http://review.coreboot.org/2333 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/2333 for details. -gerrit

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Patch set updated for coreboot: 3b3fa33 crossgcc: fix building acpica on BSD/non-linux
by Idwer Vollering 11 Feb '13

11 Feb '13

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2340 -gerrit commit 3b3fa33a0a8880e8e4a0a66c2b2d3baff4a56447 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sat Feb 9 19:23:35 2013 +0100 crossgcc: fix building acpica on BSD/non-linux Fix building acpica on BSD/non-linux. Rename patches/acpica-unix-20121114_drop_cflags_unknown_to_xcode.patch to patches/acpica-unix-20121114_drop_unknown_cflags.patch Error message: cc1: warnings being treated as errors ../../../source/components/executer/exdump.c: In function 'AcpiExDumpObject': ../../../source/components/executer/exdump.c:516: warning: cast from function call of type 'const char *' to non-matching type 'unsigned int' gmake[2]: *** [obj32/exdump.o] Error 1 Also new is the removal of -Wempty-body. Reason of its removal: cc -c -O -m32 -D_CYGWIN -D_GNU_SOURCE -D_FORTIFY_SOURCE=2 -I../../../source/include -DACPI_ASL_COMPILER -I../../../source/compiler -Iobj32 -ansi -Wall -Wbad-function-cast -Wdeclaration-after-statement -Werror -Wformat=2 -Wmissing-declarations -Wmissing-prototypes -Wstrict-aliasing=0 -Wstrict-prototypes -Wswitch-default -Wpointer-arith -Wundef -Waddress -Waggregate-return -Wchar-subscripts -Wempty-body -Wmissing-declarations -Wmissing-field-initializers -Wnested-externs -Wold-style-definition -Wredundant-decls -oobj32/adfile.o ../../../source/common/adfile.c cc1: error: unrecognized command line option "-Wempty-body" This change doesn't appear to be required for GNU/linuxes. Change-Id: Ia1d2915257af2a6631b5294b56f0f66b3830af3c Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- ...nix-20121114_drop_cflags_unknown_to_xcode.patch | 20 --------------- .../acpica-unix-20121114_drop_unknown_cflags.patch | 29 ++++++++++++++++++++++ 2 files changed, 29 insertions(+), 20 deletions(-) diff --git a/util/crossgcc/patches/acpica-unix-20121114_drop_cflags_unknown_to_xcode.patch b/util/crossgcc/patches/acpica-unix-20121114_drop_cflags_unknown_to_xcode.patch deleted file mode 100644 index a4d55da..0000000 --- a/util/crossgcc/patches/acpica-unix-20121114_drop_cflags_unknown_to_xcode.patch +++ /dev/null @@ -1,20 +0,0 @@ -diff -ur acpica-unix-20121114.orig/generate/unix/Makefile.config acpica-unix-20121114/generate/unix/Makefile.config ---- acpica-unix-20121114.orig/generate/unix/Makefile.config 2012-11-14 08:22:38.000000000 -0800 -+++ acpica-unix-20121114/generate/unix/Makefile.config 2012-12-05 15:53:35.000000000 -0800 -@@ -135,15 +135,11 @@ - -Waggregate-return \ - -Wchar-subscripts \ - -Wempty-body \ -- -Wlogical-op \ - -Wmissing-declarations \ - -Wmissing-field-initializers \ -- -Wmissing-parameter-type \ - -Wnested-externs \ -- -Wold-style-declaration \ - -Wold-style-definition \ -- -Wredundant-decls \ -- -Wtype-limits -+ -Wredundant-decls - - # - # Extra warning flags (possible future use) diff --git a/util/crossgcc/patches/acpica-unix-20121114_drop_unknown_cflags.patch b/util/crossgcc/patches/acpica-unix-20121114_drop_unknown_cflags.patch new file mode 100644 index 0000000..cfc392c --- /dev/null +++ b/util/crossgcc/patches/acpica-unix-20121114_drop_unknown_cflags.patch @@ -0,0 +1,29 @@ +diff -ur acpica-unix-20121114.orig/generate/unix/Makefile.config acpica-unix-20121114/generate/unix/Makefile.config +--- acpica-unix-20121114.orig/generate/unix/Makefile.config 2012-11-14 17:22:38.000000000 +0100 ++++ acpica-unix-20121114/generate/unix/Makefile.config 2013-02-09 17:57:59.000000000 +0100 +@@ -115,7 +115,6 @@ + CWARNINGFLAGS = \ + -ansi \ + -Wall \ +- -Wbad-function-cast \ + -Wdeclaration-after-statement \ + -Werror \ + -Wformat=2 \ +@@ -134,16 +133,11 @@ + -Waddress \ + -Waggregate-return \ + -Wchar-subscripts \ +- -Wempty-body \ +- -Wlogical-op \ + -Wmissing-declarations \ + -Wmissing-field-initializers \ +- -Wmissing-parameter-type \ + -Wnested-externs \ +- -Wold-style-declaration \ + -Wold-style-definition \ +- -Wredundant-decls \ +- -Wtype-limits ++ -Wredundant-decls + + # + # Extra warning flags (possible future use)

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Patch set updated for coreboot: 12dfd5d crossgcc: don't use libdl while building GDB on FreeBSD
by Idwer Vollering 11 Feb '13

11 Feb '13

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2342 -gerrit commit 12dfd5dda09cf57edfd9ce189cb0384113da53d2 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sat Feb 9 23:58:06 2013 +0100 crossgcc: don't use libdl while building GDB on FreeBSD crossgcc: fix building GDB on FreeBSD (and possibly NetBSD/OpenBSD). Since FreeBSD doesn't have libdl, these errors are shown: - config.log: /usr/bin/ld: cannot find -ldl - crossgcc-build.log: configure: error: C compiler cannot create executables Conditionally remove -ldl from LDFLAGS. Change-Id: I79c48da7e6700a4606c9e0c1314241db8997d3f3 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- util/crossgcc/buildgcc | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index eaff24d..90e45d5 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -562,11 +562,19 @@ printf "Building GDB ${GDB_VERSION} ... " cd build-gdb export PYTHONHOME=$DESTDIR$TARGETDIR rm -f .failed + if [ $(uname) = "FreeBSD" -o $(uname) = "NetBSD" ] ; then LDFLAGS="-Wl,-rpath,\$\$ORIGIN/../lib/ -L$DESTDIR$TARGETDIR/lib \ - -lpthread -ldl -lutil" \ + -lpthread -lutil" \ CC="$CC" CFLAGS="$HOSTCFLAGS -I$DESTDIR$TARGETDIR/include" \ ../gdb-${GDB_VERSION}/configure --prefix=$TARGETDIR \ --target=${TARGETARCH} --disable-werror --disable-nls + else + LDFLAGS="-Wl,-rpath,\$\$ORIGIN/../lib/ -L$DESTDIR$TARGETDIR/lib \ + -lpthread -ldl -lutil" \ + CC="$CC" CFLAGS="$HOSTCFLAGS -I$DESTDIR$TARGETDIR/include" \ + ../gdb-${GDB_VERSION}/configure --prefix=$TARGETDIR \ + --target=${TARGETARCH} --disable-werror --disable-nls + fi $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed if [ ! -f .failed ]; then touch .success; fi

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Patch merged into coreboot/master: 3d990ff Supermicro H8QGI: Substract 1 from MMCONF range limit
by gerrit＠coreboot.org 11 Feb '13

11 Feb '13

the following patch was just integrated into master: commit 3d990ffc88f5d54f32de28cc6a2a87f490bd701a Author: Konstantin Aladyshev <aladyshev(a)nicevt.ru> Date: Fri Jan 25 19:20:51 2013 +0400 Supermicro H8QGI: Substract 1 from MMCONF range limit MMCONF space is defined by two config parameters: MMCONF_BASE_ADDRESS (0xF800 0000) MMCONF_BUS_NUMBER (64) Coreboot allocates 1MB per bus, so MMCONF limit should be: 0xF800 0000 + 64*(0x0010 0000) - 1 = 0xFBFF FFFF Current code does not have (-1) component, this makes MMCONF limit equal 0xFC00 FFFF. Not 0xFC00 0000, because according to BKDG lower two bytes of MMIO limit always equal 0xFFFF: MMIOLimit = {MMIOLimitRegister[47:16], FFFFh}. Add (-1) to correct this issue. No functionality change has been experienced. The five times slower RAM speed compared to the proprietary vendor BIOS still remains. Change-Id: I2c6494c28bb8d36e54ceb2aa7d8d965b0103cbe9 Signed-off-by: Konstantin Aladyshev <aladyshev(a)nicevt.ru> Reviewed-on: http://review.coreboot.org/2193 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Mon Feb 11 08:27:51 2013, giving +2 See http://review.coreboot.org/2193 for details. -gerrit

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Patch merged into coreboot/master: 96e3035 AMD SB900: fix warnings
by gerrit＠coreboot.org 11 Feb '13

11 Feb '13

the following patch was just integrated into master: commit 96e3035a1f9f6ade63d31c4f5e6f806df609f5c1 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Sun Feb 10 14:26:20 2013 -0700 AMD SB900: fix warnings Add a prototype to a .h file Remove an unused file (GppHp.c) from the build by deleting it from the makefile. I left the file since this is vendorcode. This is the code for PCIe hotplug. Inside GppHp.c, make functions not called from outside static. This obviously isn't important since the file isn't used, but for the sake of the cleanup I thought I'd go ahead with it... This was tested with the torpedo build. This fixes these warnings: src/vendorcode/amd/cimx/sb900/Dispatcher.c: In function 'LocateImage': src/vendorcode/amd/cimx/sb900/Dispatcher.c:193:38: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/cimx/sb900/Usb.c:740:1: warning: no previous prototype for 'XhciA12Fix' [-Wmissing-prototypes] src/vendorcode/amd/cimx/sb900/GppHp.c:65:1: warning: no previous prototype for 'sbGppHotPlugSmiProcess' [-Wmissing-prototypes] src/vendorcode/amd/cimx/sb900/GppHp.c: In function 'sbGppHotPlugSmiProcess': src/vendorcode/amd/cimx/sb900/GppHp.c:76:5: warning: implicit declaration of function 'SbStall' [-Wimplicit-function-declaration] src/vendorcode/amd/cimx/sb900/GppHp.c: At top level: src/vendorcode/amd/cimx/sb900/GppHp.c:101:1: warning: no previous prototype for 'sbGppHotUnplugSmiProcess' [-Wmissing-prototypes] src/vendorcode/amd/cimx/sb900/GppHp.c:134:1: warning: no previous prototype for 'sbGppHotplugSmiCallback' [-Wmissing-prototypes] src/vendorcode/amd/cimx/sb900/GppHp.c: In function 'sbGppHotplugSmiCallback': src/vendorcode/amd/cimx/sb900/GppHp.c:158:5: warning: implicit declaration of function 'outPort80' [-Wimplicit-function-declaration] Change-Id: I5a1a20eeb81e1f4d59e3e3192f081e11d8506f56 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2349 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Mon Feb 11 08:25:44 2013, giving +2 See http://review.coreboot.org/2349 for details. -gerrit

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Patch merged into coreboot/master: c52e106 AMD S3: Add missing erasing flash sector for saving MTRR register
by gerrit＠coreboot.org 11 Feb '13

11 Feb '13

the following patch was just integrated into master: commit c52e1065df07c24606381efb7598b1d29dc625b1 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Sun Feb 10 21:20:39 2013 +0800 AMD S3: Add missing erasing flash sector for saving MTRR register It has worked up to now because the region is already erased the first time the board boots, and every additional boot the same data is being written over the old data.(by Dave Frodin) Change-Id: Id334c60668e31d23c1d552d0ace8eb6ae5513e6b Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Reviewed-on: http://review.coreboot.org/2304 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Mon Feb 11 08:24:01 2013, giving +2 See http://review.coreboot.org/2304 for details. -gerrit

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coreboot February 2013