the following patch was just integrated into master:
commit e07e253bc87d6a86e5fb7f62bb63438ae4f6c5ba
Author: Zheng Bao <fishbaozi(a)gmail.com>
Date: Sun Feb 10 21:10:52 2013 +0800
AMD S3: Change the hardcoded data size to macros.
Change-Id: Ieefc4213a6dee9c399826b1daa98bbf4bc10d881
Signed-off-by: Zheng Bao <zheng.bao(a)amd.com>
Signed-off-by: zbao <fishbaozi(a)gmail.com>
Reviewed-on: http://review.coreboot.org/2303
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Mon Feb 11 08:23:36 2013, giving +2
See http://review.coreboot.org/2303 for details.
-gerrit
the following patch was just integrated into master:
commit e7c76b475c03ee7f907dbbef87ca7d755bcef6d1
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Sun Feb 10 16:05:26 2013 -0800
snow: make build script erase 192KB instead of 128KB
This will make the build script wipe out more flash memory content.
Our image is a bit bigger now that we're testing with payloads, so
this is just added paranoia to prevent weird surprises caused by not
flashing the full image.
Change-Id: I31969922079e96886573d9d802266eb0052277cd
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-on: http://review.coreboot.org/2352
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Mon Feb 11 01:42:18 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Feb 11 02:33:18 2013, giving +2
See http://review.coreboot.org/2352 for details.
-gerrit
the following patch was just integrated into master:
commit 5d994634a268d29b61c98f40f4793334078509c4
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Sun Feb 10 15:50:20 2013 -0800
armv7/exynos5250/snow: deprecate CONFIG_{RAMBASE,RAMTOP}
RAMBASE and RAMTOP are leftovers from the x86 port and do not apply
the same way on ARM platforms. On x86 they refer to the low memory
region where coreboot tables reside.
However on ARM we don't have such a region which is architecturally
defined. So instead we'll use the CPU-defined DRAM base address and
the mainboard-defined DRAM size.
This also has the pleasant side-effect of fixing the coreboot tables
to not clobber ramstage code...
Change-Id: I5548ecf05e82f9d9ecec8548fabdd99cc1e39c3b
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-on: http://review.coreboot.org/2351
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Mon Feb 11 01:34:17 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Feb 11 02:31:33 2013, giving +2
See http://review.coreboot.org/2351 for details.
-gerrit
David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2352
-gerrit
commit 91f8b716989facc2fce9b018243829ea1bf7a408
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Sun Feb 10 16:05:26 2013 -0800
snow: make build script erase 192KB instead of 128KB
This will make the build script wipe out more flash memory content.
Our image is a bit bigger now that we're testing with payloads, so
this is just added paranoia to prevent weird surprises caused by not
flashing the full image.
Change-Id: I31969922079e96886573d9d802266eb0052277cd
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
---
src/vendorcode/google/chromeos/build | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/vendorcode/google/chromeos/build b/src/vendorcode/google/chromeos/build
index 13f7d92..a749ba5 100755
--- a/src/vendorcode/google/chromeos/build
+++ b/src/vendorcode/google/chromeos/build
@@ -16,11 +16,11 @@ die() {
exit 1
}
-create_diff_128k() {
+create_diff_192k() {
local image_file="$1"
local diff_file="$2"
cp -f "$image_file" "$diff_file"
- dd if=/dev/zero of=$diff_file bs=1 count=$((128*1024)) conv=notrunc
+ dd if=/dev/zero of=$diff_file bs=1 count=$((192*1024)) conv=notrunc
}
fast_flash_image() {
@@ -67,7 +67,7 @@ is_servod_ready() {
main() {
make
merge_bl1 "$OUTPUT"
- create_diff_128k "$OUTPUT" "$TMP_DIFF"
+ create_diff_192k "$OUTPUT" "$TMP_DIFF"
echo "OK: Generated image (with BL1) in $OUTPUT"
if is_servod_ready; then
echo "servod detected - flashing into device."
David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2351
-gerrit
commit 8421155b4dfc076339bee9405bd68f4a73bc4a1e
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Sun Feb 10 15:50:20 2013 -0800
armv7/exynos5250/snow: deprecate CONFIG_{RAMBASE,RAMTOP}
RAMBASE and RAMTOP are leftovers from the x86 port and do not apply
the same way on ARM platforms. On x86 they refer to the low memory
region where coreboot tables reside.
However on ARM we don't have such a region which is architecturally
defined. So instead we'll use the CPU-defined DRAM base address and
the mainboard-defined DRAM size.
This also has the pleasant side-effect of fixing the coreboot tables
to not clobber ramstage code...
Change-Id: I5548ecf05e82f9d9ecec8548fabdd99cc1e39c3b
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
---
src/arch/armv7/coreboot_ram.ld | 7 +------
src/cpu/samsung/exynos5250/Kconfig | 9 ++-------
src/mainboard/google/snow/ramstage.c | 8 +++++---
3 files changed, 8 insertions(+), 16 deletions(-)
diff --git a/src/arch/armv7/coreboot_ram.ld b/src/arch/armv7/coreboot_ram.ld
index c69499c..0644e36 100644
--- a/src/arch/armv7/coreboot_ram.ld
+++ b/src/arch/armv7/coreboot_ram.ld
@@ -26,7 +26,7 @@ ENTRY(_start)
SECTIONS
{
- . = CONFIG_RAMBASE;
+ . = CONFIG_SYS_SDRAM_BASE;
/* First we place the code and read only data (typically const declared).
* This could theoretically be placed in rom.
*/
@@ -123,11 +123,6 @@ SECTIONS
_ram_seg = _text;
_eram_seg = _eheap;
- /* CONFIG_RAMTOP is the upper address of cached memory (among other
- * things). We must not exceed beyond that address, there be dragons.
- */
- _bogus = ASSERT( ( _eram_seg < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
-
/* Discard the sections we don't need/want */
/DISCARD/ : {
diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig
index f62195a..2869d76 100644
--- a/src/cpu/samsung/exynos5250/Kconfig
+++ b/src/cpu/samsung/exynos5250/Kconfig
@@ -90,11 +90,6 @@ config SYS_TEXT_BASE
hex "Executable code section"
default 0x43e00000
-config RAMBASE
+config COREBOOT_TABLES_SIZE
hex
- default SYS_SDRAM_BASE
-# according to stefan, this is RAMBASE + 1M.
-config RAMTOP
- hex
- default 0x40100000
-
+ default 0x100000
diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c
index d280dbe..b779999 100644
--- a/src/mainboard/google/snow/ramstage.c
+++ b/src/mainboard/google/snow/ramstage.c
@@ -30,9 +30,11 @@ void main(void)
printk(BIOS_INFO, "hello from ramstage\n");
#if CONFIG_WRITE_HIGH_TABLES
- /* Leave some space for ACPI tables */
- high_tables_base = CONFIG_RAMBASE;
- high_tables_size = CONFIG_RAMBASE + 0x100000;
+ /* place at top of physical memory */
+ high_tables_size = CONFIG_COREBOOT_TABLES_SIZE;
+ high_tables_base = CONFIG_SYS_SDRAM_BASE +
+ ((CONFIG_DRAM_SIZE_MB * 1024) * CONFIG_NR_DRAM_BANKS) -
+ CONFIG_COREBOOT_TABLES_SIZE;
#endif
hardwaremain(0);
David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2351
-gerrit
commit 8260019697733a27730e7c96806dd0c3f5ead166
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Sun Feb 10 15:50:20 2013 -0800
armv7/exynos5250/snow: deprecate CONFIG_{RAMBASE,RAMTOP}
RAMBASE and RAMTOP are leftovers from the x86 port and do not apply
the same way on ARM platforms. On x86 they refer to the low memory
region where coreboot tables reside.
However on ARM we don't have such a region which is architecturally
defined. So instead we'll use the CPU-defined DRAM base address and
the mainboard-defined DRAM size.
This also has the pleasant side-effect of fixing the coreboot tables
to not clobber ramstage code...
Change-Id: I5548ecf05e82f9d9ecec8548fabdd99cc1e39c3b
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
---
src/arch/armv7/coreboot_ram.ld | 4 ++--
src/cpu/samsung/exynos5250/Kconfig | 9 ++-------
src/mainboard/google/snow/ramstage.c | 8 +++++---
3 files changed, 9 insertions(+), 12 deletions(-)
diff --git a/src/arch/armv7/coreboot_ram.ld b/src/arch/armv7/coreboot_ram.ld
index c69499c..7839aeb 100644
--- a/src/arch/armv7/coreboot_ram.ld
+++ b/src/arch/armv7/coreboot_ram.ld
@@ -26,7 +26,7 @@ ENTRY(_start)
SECTIONS
{
- . = CONFIG_RAMBASE;
+ . = CONFIG_SYS_SDRAM_BASE;
/* First we place the code and read only data (typically const declared).
* This could theoretically be placed in rom.
*/
@@ -126,7 +126,7 @@ SECTIONS
/* CONFIG_RAMTOP is the upper address of cached memory (among other
* things). We must not exceed beyond that address, there be dragons.
*/
- _bogus = ASSERT( ( _eram_seg < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
+ /*_bogus = ASSERT( ( _eram_seg < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP"); */
/* Discard the sections we don't need/want */
diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig
index f62195a..2869d76 100644
--- a/src/cpu/samsung/exynos5250/Kconfig
+++ b/src/cpu/samsung/exynos5250/Kconfig
@@ -90,11 +90,6 @@ config SYS_TEXT_BASE
hex "Executable code section"
default 0x43e00000
-config RAMBASE
+config COREBOOT_TABLES_SIZE
hex
- default SYS_SDRAM_BASE
-# according to stefan, this is RAMBASE + 1M.
-config RAMTOP
- hex
- default 0x40100000
-
+ default 0x100000
diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c
index d280dbe..b779999 100644
--- a/src/mainboard/google/snow/ramstage.c
+++ b/src/mainboard/google/snow/ramstage.c
@@ -30,9 +30,11 @@ void main(void)
printk(BIOS_INFO, "hello from ramstage\n");
#if CONFIG_WRITE_HIGH_TABLES
- /* Leave some space for ACPI tables */
- high_tables_base = CONFIG_RAMBASE;
- high_tables_size = CONFIG_RAMBASE + 0x100000;
+ /* place at top of physical memory */
+ high_tables_size = CONFIG_COREBOOT_TABLES_SIZE;
+ high_tables_base = CONFIG_SYS_SDRAM_BASE +
+ ((CONFIG_DRAM_SIZE_MB * 1024) * CONFIG_NR_DRAM_BANKS) -
+ CONFIG_COREBOOT_TABLES_SIZE;
#endif
hardwaremain(0);
David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2350
-gerrit
commit 9f4c56689b01efcedf91a86acf7eb194fb7b6fc9
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Sun Feb 10 15:59:22 2013 -0800
snow: switch to stack in DRAM once in ramstage
This patch gives us some stack space in RAM and sets our stack
pointer to once we begin ramstage.
Note: We may not need this patch after all since we should have
plenty of stack space in SRAM. It might be simpler (and perhaps
faster) to keep the stack in SRAM.
(credit to Gabe for this one, I'm just putting it up on gerrit)
Change-Id: I2e447d6359d52e4615e1cd7811e6f167e3dc314b
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/arch/armv7/Kconfig | 4 ++++
src/mainboard/google/snow/ramstage.c | 13 ++++++++++++-
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/src/arch/armv7/Kconfig b/src/arch/armv7/Kconfig
index 488ca97..fe36d79 100644
--- a/src/arch/armv7/Kconfig
+++ b/src/arch/armv7/Kconfig
@@ -49,4 +49,8 @@ config ARM_DCACHE_POLICY_WRITETHROUGH
bool
default n
+config STACK_SIZE
+ hex
+ default 0x1000
+
endmenu
diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c
index d280dbe..2045c5f 100644
--- a/src/mainboard/google/snow/ramstage.c
+++ b/src/mainboard/google/snow/ramstage.c
@@ -17,6 +17,7 @@
* MA 02111-1307 USA
*/
+#include <lib.h>
#include <console/console.h>
#if CONFIG_WRITE_HIGH_TABLES
@@ -24,7 +25,7 @@
#endif
void hardwaremain(int boot_complete);
-void main(void)
+static void real_main(void)
{
console_init();
printk(BIOS_INFO, "hello from ramstage\n");
@@ -37,3 +38,13 @@ void main(void)
hardwaremain(0);
}
+
+void main(void)
+{
+ __asm__ __volatile__(
+ "mov sp, %0\n\r"
+ "mov pc, %1\n\r"
+ :
+ :"r"(_estack), "r"(&real_main)
+ );
+}