coreboot February 2013

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Patch set updated for coreboot: 90f4c5b armv7: Add emulation/qemu-armv7 board.
by Hung-Te Lin 12 Feb '13

12 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2354 -gerrit commit 90f4c5b663330a7e24b7f26a6e39e3b8a43bc521 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Tue Feb 12 00:07:38 2013 +0800 armv7: Add emulation/qemu-armv7 board. To simplify testing ARM implementation, we need a QEMU configuration for ARM. The qemu-armv7 provides serial output, CBFS simulation, and full boot path (bootblock, romstage, ramstage) to verify the boot loader functionality. To run with QEMU: export QEMU_AUDIO_DRV=none qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom Verified to boot until ramstage loaded successfully by QEMU v1.0.50. Change-Id: I1f23ffaf408199811a0756236821c7e0f2a85004 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/cpu/Kconfig | 1 + src/cpu/Makefile.inc | 1 + src/cpu/armltd/Kconfig | 8 ++ src/cpu/armltd/Makefile.inc | 1 + src/cpu/armltd/cortex-a9/Kconfig | 5 + src/cpu/armltd/cortex-a9/Makefile.inc | 2 + src/cpu/armltd/cortex-a9/bootblock.c | 17 ++++ src/cpu/armltd/cortex-a9/cache.c | 44 +++++++++ src/mainboard/emulation/Kconfig | 4 + src/mainboard/emulation/qemu-armv7/Kconfig | 116 +++++++++++++++++++++++ src/mainboard/emulation/qemu-armv7/Makefile.inc | 30 ++++++ src/mainboard/emulation/qemu-armv7/bootblock.c | 23 +++++ src/mainboard/emulation/qemu-armv7/devicetree.cb | 20 ++++ src/mainboard/emulation/qemu-armv7/mainboard.c | 27 ++++++ src/mainboard/emulation/qemu-armv7/media.c | 57 +++++++++++ src/mainboard/emulation/qemu-armv7/ramstage.c | 24 +++++ src/mainboard/emulation/qemu-armv7/romstage.c | 31 ++++++ src/mainboard/emulation/qemu-armv7/timer.c | 24 +++++ src/mainboard/emulation/qemu-armv7/uart.c | 56 +++++++++++ 19 files changed, 491 insertions(+) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index f60ffe7..caf4ebc 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -3,6 +3,7 @@ # (See also src/Kconfig) if ARCH_ARMV7 +source src/cpu/armltd/Kconfig source src/cpu/samsung/Kconfig endif # ARCH_ARM diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 93b16ae..e1efecc 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -2,6 +2,7 @@ ## Subdirectories ################################################################################ subdirs-y += amd +subdirs-y += armltd subdirs-y += intel subdirs-y += samsung subdirs-y += via diff --git a/src/cpu/armltd/Kconfig b/src/cpu/armltd/Kconfig new file mode 100644 index 0000000..b1f4c2e --- /dev/null +++ b/src/cpu/armltd/Kconfig @@ -0,0 +1,8 @@ +config CPU_ARMLTD_CORTEX_A9 + depends on ARCH_ARMV7 + bool + default n + +if CPU_ARMLTD_CORTEX_A9 +source src/cpu/armltd/cortex-a9/Kconfig +endif diff --git a/src/cpu/armltd/Makefile.inc b/src/cpu/armltd/Makefile.inc new file mode 100644 index 0000000..014742f --- /dev/null +++ b/src/cpu/armltd/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_CPU_ARMLTD_CORTEX_A9) += cortex-a9 diff --git a/src/cpu/armltd/cortex-a9/Kconfig b/src/cpu/armltd/cortex-a9/Kconfig new file mode 100644 index 0000000..7f35cfd --- /dev/null +++ b/src/cpu/armltd/cortex-a9/Kconfig @@ -0,0 +1,5 @@ +config BOOTBLOCK_CPU_INIT + string + default "cpu/armltd/cortex-a9/bootblock.c" + help + CPU/SoC-specific bootblock code. diff --git a/src/cpu/armltd/cortex-a9/Makefile.inc b/src/cpu/armltd/cortex-a9/Makefile.inc new file mode 100644 index 0000000..d1e7edf --- /dev/null +++ b/src/cpu/armltd/cortex-a9/Makefile.inc @@ -0,0 +1,2 @@ +ramstage-y += cache.c +romstage-y += cache.c diff --git a/src/cpu/armltd/cortex-a9/bootblock.c b/src/cpu/armltd/cortex-a9/bootblock.c new file mode 100644 index 0000000..8925439 --- /dev/null +++ b/src/cpu/armltd/cortex-a9/bootblock.c @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2013 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +void bootblock_cpu_init(void); +void bootblock_cpu_init(void) +{ +} diff --git a/src/cpu/armltd/cortex-a9/cache.c b/src/cpu/armltd/cortex-a9/cache.c new file mode 100644 index 0000000..957871d --- /dev/null +++ b/src/cpu/armltd/cortex-a9/cache.c @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2013 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <system.h> +#include <armv7.h> + +/* + * Sets L2 cache related parameters before enabling data cache + */ +void v7_outer_cache_enable(void) +{ +} + +/* stubs so we don't need weak symbols in cache_v7.c */ +void v7_outer_cache_disable(void) +{ +} + +void v7_outer_cache_flush_all(void) +{ +} + +void v7_outer_cache_inval_all(void) +{ +} + +void v7_outer_cache_flush_range(u32 start, u32 end) +{ +} + +void v7_outer_cache_inval_range(u32 start, u32 end) +{ +} diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig index 5661f0e..ea6b180 100644 --- a/src/mainboard/emulation/Kconfig +++ b/src/mainboard/emulation/Kconfig @@ -6,9 +6,13 @@ choice config BOARD_EMULATION_QEMU_X86 bool "QEMU x86" +config BOARD_EMULATION_QEMU_ARMV7 + bool "QEMU armv7 (vexpress-a9)" + endchoice source "src/mainboard/emulation/qemu-x86/Kconfig" +source "src/mainboard/emulation/qemu-armv7/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig new file mode 100644 index 0000000..38b1da2 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -0,0 +1,116 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +# Emulation for ARM Ltd Versatile Express Cortex-A9 +# http://www.arm.com/products/tools/development-boards/versatile-express + +# To execute, do: +# export QEMU_AUDIO_DRV=none +# qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom + +if BOARD_EMULATION_QEMU_ARMV7 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_ARMV7 + select CPU_ARMLTD_CORTEX_A9 + select DEFAULT_EARLY_CONSOLE + select HAVE_UART_SPECIAL + select BOARD_ROMSIZE_KB_4096 + +config MAINBOARD_DIR + string + default emulation/qemu-armv7 + +config MAINBOARD_PART_NUMBER + string + default "QEMU ARMV7" + +config MAX_CPUS + int + default 2 + +config MAINBOARD_VENDOR + string + default "ARM Ltd." + +config BOOTBLOCK_MAINBOARD_INIT + string + default "mainboard/emulation/qemu-armv7/bootblock.c" + +config DRAM_SIZE_MB + int + default 1024 + +# Memory map for qemu vexpress-a9: +# +# 0x0000_0000: jump instruction (by qemu) +# 0x0001_0000: bootblock (entry of kernel / firmware) +# 0x0002_0000: romstage, assume up to 128KB in size. +# 0x0007_ff00: stack pointer +# 0x0010_0000: CBFS header +# 0x0011_0000: CBFS data +# 0x0100_0000: reserved for ramstage +# 0x1000_0000: I/O map address + +config BOOTBLOCK_BASE + hex + default 0x00010000 + +config ID_SECTION_BASE + hex + default 0x0001f000 + +config ROMSTAGE_BASE + hex + default 0x00020000 + +config ROMSTAGE_SIZE + hex + default 0x20000 + +config CBFS_HEADER_ROM_OFFSET + hex + default 0x0100000 + +config CBFS_ROM_OFFSET + hex + default 0x0110000 + +config IRAM_STACK + hex + default 0x0007ff00 + +config XIP_ROM_SIZE + hex + default ROMSTAGE_SIZE + +config SYS_SDRAM_BASE + hex "SDRAM base address" + default 0x01000000 + +config SYS_TEXT_BASE + hex "Executable code section" + default 0x04e00000 + +config RAMBASE + hex + default SYS_SDRAM_BASE + +# according to stefan, this is RAMBASE + 1M. +config RAMTOP + hex + default 0x01100000 + +endif # BOARD_EMULATION_QEMU_ARMV7 diff --git a/src/mainboard/emulation/qemu-armv7/Makefile.inc b/src/mainboard/emulation/qemu-armv7/Makefile.inc new file mode 100644 index 0000000..cea3b15 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv7/Makefile.inc @@ -0,0 +1,30 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +romstage-y += romstage.c +ramstage-y += ramstage.c + +bootblock-y += media.c +romstage-y += media.c +ramstage-y += media.c + +bootblock-y += timer.c +romstage-y += timer.c +ramstage-y += timer.c + +bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c +romstage-$(CONFIG_EARLY_CONSOLE) += uart.c +ramstage-y += uart.c + +SRC_ROOT = $(src)/mainboard/emulation/qemu-armv7a diff --git a/src/mainboard/emulation/qemu-armv7/bootblock.c b/src/mainboard/emulation/qemu-armv7/bootblock.c new file mode 100644 index 0000000..5654667 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv7/bootblock.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> + +void bootblock_mainboard_init(void); +void bootblock_mainboard_init(void) +{ + console_init(); + printk(BIOS_INFO, "\n\n\n%s: ARMv7 Emulation Started.\n", __func__); +} diff --git a/src/mainboard/emulation/qemu-armv7/devicetree.cb b/src/mainboard/emulation/qemu-armv7/devicetree.cb new file mode 100644 index 0000000..9153442 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv7/devicetree.cb @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google, Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +# TODO fill with Versatile Express board data in QEMU. +chip cpu/armltd/cortex-a9 + chip drivers/generic/generic # I2C0 controller + device i2c 6 on end # Fake component for testing + end +end diff --git a/src/mainboard/emulation/qemu-armv7/mainboard.c b/src/mainboard/emulation/qemu-armv7/mainboard.c new file mode 100644 index 0000000..cbc3197 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv7/mainboard.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> + +static void enable_dev(device_t dev) +{ + printk(BIOS_INFO, "Enable qemu/armv7 device...\n"); +} + +struct chip_operations mainboard_ops = { + .enable_dev = enable_dev, +}; + diff --git a/src/mainboard/emulation/qemu-armv7/media.c b/src/mainboard/emulation/qemu-armv7/media.c new file mode 100644 index 0000000..d024b5d --- /dev/null +++ b/src/mainboard/emulation/qemu-armv7/media.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <cbfs.h> +#include <string.h> +#include <console/console.h> + +/* Simple memory-mapped ROM emulation. */ + +static int emu_rom_open(struct cbfs_media *media) { + return 0; +} + +static void *emu_rom_map(struct cbfs_media *media, size_t offset, size_t count) { + return (void*)(offset + CONFIG_BOOTBLOCK_BASE); +} + +static void *emu_rom_unmap(struct cbfs_media *media, const void *address) { + return NULL; +} + +static size_t emu_rom_read(struct cbfs_media *media, void *dest, size_t offset, + size_t count) { + void *ptr = emu_rom_map(media, offset, count); + memcpy(dest, ptr, count); + emu_rom_unmap(media, ptr); + return count; +} + +static int emu_rom_close(struct cbfs_media *media) { + return 0; +} + +int init_emu_rom_cbfs_media(struct cbfs_media *media); +int init_emu_rom_cbfs_media(struct cbfs_media *media) { + media->open = emu_rom_open; + media->close = emu_rom_close; + media->map = emu_rom_map; + media->unmap = emu_rom_unmap; + media->read = emu_rom_read; + return 0; +} + +int init_default_cbfs_media(struct cbfs_media *media) { + return init_emu_rom_cbfs_media(media); +} diff --git a/src/mainboard/emulation/qemu-armv7/ramstage.c b/src/mainboard/emulation/qemu-armv7/ramstage.c new file mode 100644 index 0000000..24d0d7f --- /dev/null +++ b/src/mainboard/emulation/qemu-armv7/ramstage.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> + +void hardwaremain(int boot_complete); +void main(void) +{ + console_init(); + printk(BIOS_INFO, "hello from ramstage\n"); + hardwaremain(0); +} diff --git a/src/mainboard/emulation/qemu-armv7/romstage.c b/src/mainboard/emulation/qemu-armv7/romstage.c new file mode 100644 index 0000000..81f62b6 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv7/romstage.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <common.h> +#include <console/console.h> +#include <arch/stages.h> + +void main(void) +{ + void *entry; + console_init(); + printk(BIOS_INFO, "hello from romstage\n"); + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); + printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry); + + stage_exit(entry); +} diff --git a/src/mainboard/emulation/qemu-armv7/timer.c b/src/mainboard/emulation/qemu-armv7/timer.c new file mode 100644 index 0000000..53c3789 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv7/timer.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +void udelay(unsigned int n); +void udelay(unsigned int n) { + /* TODO provide delay here. */ +} + +int init_timer(void); +int init_timer(void) { + return 0; +} diff --git a/src/mainboard/emulation/qemu-armv7/uart.c b/src/mainboard/emulation/qemu-armv7/uart.c new file mode 100644 index 0000000..2988777 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv7/uart.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <uart.h> + +#define VEXPRESS_UART0_IO_ADDRESS (0x10009000) + +static void pl011_init_dev(void) { +} + +static void pl011_uart_tx_byte(unsigned char data) { + static volatile unsigned int *uart0_address = + (unsigned int *)VEXPRESS_UART0_IO_ADDRESS; + + *uart0_address = (unsigned int)data; +} + +static void pl011_uart_tx_flush(void) { +} + +#if !defined(__PRE_RAM__) + +static const struct console_driver pl011_uart_console __console = { + .init = pl011_init_dev, + .tx_byte = pl011_uart_tx_byte, + .tx_flush = pl011_uart_tx_flush, +}; + +#else +void uart_init(void) +{ + pl011_init_dev(); +} + +void uart_tx_byte(unsigned char data) +{ + pl011_uart_tx_byte(data); +} + +void uart_tx_flush(void) { + pl011_uart_tx_flush(); +} +#endif

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Re: [coreboot] New patch to review for coreboot: 0ae65d8 Add support for "Butterfly" Chromebook
by Peter Stuge 12 Feb '13

12 Feb '13

ron minnich wrote: > This is another case where I would kind of prefer to let the "shipping > version " if the code go in as is, then put the revs in. I understand that, but it would nevertheless be nice to pretend to care about review feedback. I don't think anyone expects feedback to neccessarily lead to further patchsets on a change, especially for code that is already shipping. On the odd chance that there is something valuable that the community can contribute, leaving next to no room for feedback can easily make people feel discouraged. > it's useful to have a version in the repo that is exactly what's on > that machine Agreed. > I think it would be wonderful if we could get your comments in and do > another rev based on that At the very least maybe keep things in mind for the future. > with the caveat that at that point you're no longer building what's > on the machine and there are no guarantees. Of course. I'd suggest to additionally create a git tag on the commit, with a name that somehow corresponds to supply chain identification of the machine. //Peter

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New patch to review for coreboot: e746c7d armv7: don't do anything in checkstack for now()
by David Hendricks 12 Feb '13

12 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2362 -gerrit commit e746c7ddc7a6b1492933ec3a85b255975b5a260d Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Feb 11 16:32:09 2013 -0800 armv7: don't do anything in checkstack for now() ** do not submit ** Another gross hack. Change-Id: I7d95b3b1e30d422aeb2bdf306bd6c6b30710edc2 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> --- src/lib/stack.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/lib/stack.c b/src/lib/stack.c index 0a6637f..d588f4a 100644 --- a/src/lib/stack.c +++ b/src/lib/stack.c @@ -25,6 +25,7 @@ it with the version available from LANL. int checkstack(void *top_of_stack, int core) { +#if CONFIG_ARCH_X86 // FIXME not yet implemented on ARM! int i; u32 *stack = (u32 *) (top_of_stack - CONFIG_STACK_SIZE); @@ -47,7 +48,7 @@ int checkstack(void *top_of_stack, int core) sizeof(stack[0])] - (unsigned long)&stack[i]); return 0; } - +#endif return 0; }

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Patch set updated for coreboot: 593b61e snow: switch to stack in DRAM once in ramstage
by David Hendricks 12 Feb '13

12 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2350 -gerrit commit 593b61ec770316d569077ef08a7b22597c0d57c3 Author: David Hendricks <dhendrix(a)chromium.org> Date: Sun Feb 10 15:59:22 2013 -0800 snow: switch to stack in DRAM once in ramstage This patch gives us some stack space in RAM and sets our stack pointer to once we begin ramstage. Note: We may not need this patch after all since we should have plenty of stack space in SRAM. It might be simpler (and perhaps faster) to keep the stack in SRAM. (credit to Gabe for this one, I'm just putting it up on gerrit) Change-Id: I2e447d6359d52e4615e1cd7811e6f167e3dc314b Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/Kconfig | 4 ++++ src/mainboard/google/snow/ramstage.c | 37 ++++++++++++------------------------ 2 files changed, 16 insertions(+), 25 deletions(-) diff --git a/src/arch/armv7/Kconfig b/src/arch/armv7/Kconfig index 488ca97..fe36d79 100644 --- a/src/arch/armv7/Kconfig +++ b/src/arch/armv7/Kconfig @@ -49,4 +49,8 @@ config ARM_DCACHE_POLICY_WRITETHROUGH bool default n +config STACK_SIZE + hex + default 0x1000 + endmenu diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index e144388..a15336d 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -17,6 +17,7 @@ * MA 02111-1307 USA */ +#include <lib.h> #include <console/console.h> #include <device/device.h> @@ -25,7 +26,7 @@ #endif void hardwaremain(int boot_complete); -void main(void) +static void real_main(void) { console_init(); printk(BIOS_INFO, "hello from ramstage\n"); @@ -41,30 +42,6 @@ void main(void) hardwaremain(0); } -#if 0 -static void mainboard_read_resources(device_t dev) -{ - printk(BIOS_DEBUG, "%s: entered\n", __func__); - /* Report the memory regions */ - ram_resource(dev, 0, - CONFIG_SYS_SDRAM_BASE + (CONFIG_COREBOOT_ROMSIZE_KB), - ((CONFIG_DRAM_SIZE_MB << 10UL) * CONFIG_NR_DRAM_BANKS) - - CONFIG_COREBOOT_TABLES_SIZE); -} - -static void mainboard_set_resources(device_t dev) -{ - printk(BIOS_DEBUG, "%s: entered\n", __func__); - - assign_resources(dev->link_list); -} - -static struct device_operations mainboard_device_ops = { - .read_resources = mainboard_read_resources, - .set_resources = mainboard_set_resources, -}; -#endif - static void mainboard_enable(device_t dev) { printk(BIOS_DEBUG, "%s: entered\n", __func__); @@ -75,3 +52,13 @@ struct chip_operations mainboard_ops = { .name = "Samsung/Google ARM ChromeBook", .enable_dev = mainboard_enable, }; + +void main(void) +{ + __asm__ __volatile__( + "mov sp, %0\n\r" + "mov pc, %1\n\r" + : + :"r"(_estack), "r"(&real_main) + ); +}

1 0

New patch to review for coreboot: 8f5fa1a exynos5250: add memory resources (dirty hack)
by David Hendricks 12 Feb '13

12 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2361 -gerrit commit 8f5fa1a3234d79904e79da78fd1ef3e3892156d1 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Feb 11 16:05:33 2013 -0800 exynos5250: add memory resources (dirty hack) ** do not submit ** this is just a dirty hack to get the resource allocator to add memory. Change-Id: Ifb264ff159d45ad2f0fd8656abd6cb47fc14c7ac Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/boot/coreboot_table.c | 4 -- src/cpu/samsung/exynos5250/Makefile.inc | 1 + src/cpu/samsung/exynos5250/cpu.c | 66 +++++++++++++++++++++++++++++++++ src/device/device.c | 1 + src/mainboard/google/snow/devicetree.cb | 6 +++ src/mainboard/google/snow/mainboard.c | 21 +++++++++++ src/mainboard/google/snow/ramstage.c | 36 ++++++++++++++++++ 7 files changed, 131 insertions(+), 4 deletions(-) diff --git a/src/arch/armv7/boot/coreboot_table.c b/src/arch/armv7/boot/coreboot_table.c index ed105a4..76fc8fb 100644 --- a/src/arch/armv7/boot/coreboot_table.c +++ b/src/arch/armv7/boot/coreboot_table.c @@ -559,13 +559,11 @@ struct lb_memory *get_lb_mem(void) return mem_ranges; } -#if 0 static void build_lb_mem_range(void *gp, struct device *dev, struct resource *res) { struct lb_memory *mem = gp; new_lb_memory_range(mem, LB_MEM_RAM, res->base, res->size); } -#endif static struct lb_memory *build_lb_mem(struct lb_header *head) { @@ -576,12 +574,10 @@ static struct lb_memory *build_lb_mem(struct lb_header *head) mem_ranges = mem; /* FIXME: implement this */ -#if 0 /* Build the raw table of memory */ search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, build_lb_mem_range, mem); -#endif /* FIXME: things die in cleanup_memory_ranges(), skip for now */ // lb_cleanup_memory_ranges(mem); return mem; diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 0a58c0c..5244692 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -27,6 +27,7 @@ ramstage-y += pinmux.c ramstage-y += power.c ramstage-y += soc.c ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c +ramstage-y += cpu.c #ramstage-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c new file mode 100644 index 0000000..745bf1a --- /dev/null +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -0,0 +1,66 @@ +#include <console/console.h> +#include <device/device.h> + +static void my_pci_domain_read_resources(device_t dev) +{ + printk(BIOS_DEBUG, "%s: ENTERED!!\n", __func__); + ram_resource(dev, 0, + (CONFIG_SYS_SDRAM_BASE >> 10) + (CONFIG_COREBOOT_ROMSIZE_KB), + ((CONFIG_DRAM_SIZE_MB << 10UL) * CONFIG_NR_DRAM_BANKS) - CONFIG_COREBOOT_ROMSIZE_KB +/* - (CONFIG_COREBOOT_TABLES_SIZE >> 10) */); +} + +static void my_pci_domain_set_resources(device_t dev) +{ + printk(BIOS_DEBUG, "%s: ENTERED!!\n", __func__); + assign_resources(dev->link_list); +} + +static unsigned int my_pci_domain_scan_bus(device_t dev, unsigned int max) +{ + //max = pci_scan_bus(dev->link_list, PCI_DEVFN(0, 0), 0xff, max); + return max; +} + + +static struct device_operations pci_domain_ops = { + .read_resources = my_pci_domain_read_resources, + .set_resources = my_pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = my_pci_domain_scan_bus, +}; + +static void cpu_bus_init(device_t dev) +{ + printk(BIOS_DEBUG,"INITIALIZE CPUS!\n"); + //initialize_cpus(dev->link_list); +} + +static void cpu_bus_noop(device_t dev) +{ +} + +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, +}; + +static void enable_dev(device_t dev) +{ + printk (BIOS_DEBUG, "OUR CPU CHIP OPS!!\n"); + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations cpu_samsung_exynos5250_ops = { + CHIP_NAME("CPU Samsung Exynos 5250") + .enable_dev = enable_dev, +}; diff --git a/src/device/device.c b/src/device/device.c index 07bbc7a..7c8905b 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -812,6 +812,7 @@ void assign_resources(struct bus *bus) dev_path(bus->dev), bus->secondary, bus->link_num); for (curdev = bus->children; curdev; curdev = curdev->sibling) { + printk(BIOS_DEBUG, "curdev=%s\n", dev_path(curdev)); if (!curdev->enabled || !curdev->resource_list) continue; diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb index f88835e..5f5de32 100644 --- a/src/mainboard/google/snow/devicetree.cb +++ b/src/mainboard/google/snow/devicetree.cb @@ -19,8 +19,14 @@ # FIXME: this is just a stub for now chip cpu/samsung/exynos5250 + +device lapic_cluster 0 on +end + +device pci_domain 0 on chip drivers/generic/generic # I2C0 controller device i2c 6 on end # ? device i2c 9 on end # ? end end +end diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c index efe6672..79d5715 100644 --- a/src/mainboard/google/snow/mainboard.c +++ b/src/mainboard/google/snow/mainboard.c @@ -69,6 +69,27 @@ int board_get_config(void) } #if 0 +static void mainboard_set_resources(device_t dev) +{ + printk(BIOS_DEBUG, "%s: entered\n", __func__); + /* Report the memory regions */ + ram_resource(dev, 0, + CONFIG_SYS_SDRAM_BASE + (CONFIG_COREBOOT_ROMSIZE_KB), + ((CONFIG_DRAM_SIZE_MB << 10UL) * CONFIG_NR_DRAM_BANKS) - + CONFIG_COREBOOT_TABLES_SIZE); + + assign_resources(dev->link_list); +} + +static struct device_operations mainboard_device_ops = { + .set_resources = mainboard_set_resources, +} + +static void mainboard_enable(device_t dev) +{ + dev->ops = &mainboard_device_ops; +} + struct chip_operations mainboard_ops = { .name = "Samsung/Google ARM ChromeBook", .enable_dev = mainboard_enable, diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index a3e9236..e144388 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -18,6 +18,7 @@ */ #include <console/console.h> +#include <device/device.h> #if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> @@ -39,3 +40,38 @@ void main(void) hardwaremain(0); } + +#if 0 +static void mainboard_read_resources(device_t dev) +{ + printk(BIOS_DEBUG, "%s: entered\n", __func__); + /* Report the memory regions */ + ram_resource(dev, 0, + CONFIG_SYS_SDRAM_BASE + (CONFIG_COREBOOT_ROMSIZE_KB), + ((CONFIG_DRAM_SIZE_MB << 10UL) * CONFIG_NR_DRAM_BANKS) - + CONFIG_COREBOOT_TABLES_SIZE); +} + +static void mainboard_set_resources(device_t dev) +{ + printk(BIOS_DEBUG, "%s: entered\n", __func__); + + assign_resources(dev->link_list); +} + +static struct device_operations mainboard_device_ops = { + .read_resources = mainboard_read_resources, + .set_resources = mainboard_set_resources, +}; +#endif + +static void mainboard_enable(device_t dev) +{ + printk(BIOS_DEBUG, "%s: entered\n", __func__); + //dev->ops = &mainboard_device_ops; +} + +struct chip_operations mainboard_ops = { + .name = "Samsung/Google ARM ChromeBook", + .enable_dev = mainboard_enable, +};

1 0

Patch merged into coreboot/master: d7bd4eb Add support for "Butterfly" Chromebook
by gerrit＠coreboot.org 11 Feb '13

11 Feb '13

the following patch was just integrated into master: commit d7bd4eb003f5b6a13943418ae0ac53248a2e34d2 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Feb 11 11:11:36 2013 -0800 Add support for "Butterfly" Chromebook We're happy to announce coreboot support for the "Butterfly" Chromebook, a.k.a HP Pavilion Chromebook. More information at: http://www.google.com/intl/en/chrome/devices/hp-pavilion-chromebook.html This commit also includes support for the ENE KB3940Q embedded controller running on Quanta's firmware. Change-Id: I194f847a94005218ec04eeba091c3257ac459510 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/2359 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Mon Feb 11 21:58:55 2013, giving +1 See http://review.coreboot.org/2359 for details. -gerrit

5 4

Patch merged into coreboot/master: bc64cae spi-generic.h: Adapt include guard
by gerrit＠coreboot.org 11 Feb '13

11 Feb '13

the following patch was just integrated into master: commit bc64cae995ddab369289e19b41501df5dbc58751 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Feb 11 22:12:55 2013 +0100 spi-generic.h: Adapt include guard Rename _SPI_H_ to _SPI_GENERIC_H_ to match recent file rename. Change-Id: I8b75e2e0a515fb540587630163ad289d0a6a0b22 Reported-by: Peter Stuge <peter(a)stuge.se> Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/2360 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter(a)stuge.se> Build-Tested: build bot (Jenkins) at Mon Feb 11 22:22:42 2013, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Mon Feb 11 22:34:17 2013, giving +2 See http://review.coreboot.org/2360 for details. -gerrit

1 0

New patch to review for coreboot: 79badab spi-generic.h: Adapt include guard
by Patrick Georgi 11 Feb '13

11 Feb '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2360 -gerrit commit 79badab9136389375402261c4b2656a922ade52f Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Feb 11 22:12:55 2013 +0100 spi-generic.h: Adapt include guard Rename _SPI_H_ to _SPI_GENERIC_H_ to match recent file rename. Change-Id: I8b75e2e0a515fb540587630163ad289d0a6a0b22 Reported-by: Peter Stuge <peter(a)stuge.se> Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/include/spi-generic.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index d394531..d252c32 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -21,8 +21,8 @@ * MA 02111-1307 USA */ -#ifndef _SPI_H_ -#define _SPI_H_ +#ifndef _SPI_GENERIC_H_ +#define _SPI_GENERIC_H_ #include <stdint.h> @@ -201,4 +201,4 @@ static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte) return ret < 0 ? ret : din[1]; } -#endif /* _SPI_H_ */ +#endif /* _SPI_GENERIC_H_ */

1 0

Patch merged into coreboot/master: 4815913 build system: Mark clean-for-update phony
by gerrit＠coreboot.org 11 Feb '13

11 Feb '13

the following patch was just integrated into master: commit 4815913968a1077fa7e56d8ec226a9cf18c80ea9 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Feb 11 20:56:46 2013 +0100 build system: Mark clean-for-update phony build system hygiene, not known if this actually matters. Change-Id: Ic800a2acecff123fc2055047fab67df107ac43ab Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/2356 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Mon Feb 11 21:21:16 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Feb 11 21:13:36 2013, giving +2 See http://review.coreboot.org/2356 for details. -gerrit

1 0

Patch merged into coreboot/master: bd5e1a0 Update 3rdparty mark to latest repository
by gerrit＠coreboot.org 11 Feb '13

11 Feb '13

the following patch was just integrated into master: commit bd5e1a0ff362b6f37dfd756f451db3b1630efddb Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Feb 11 12:08:58 2013 -0800 Update 3rdparty mark to latest repository Change-Id: Iad3ee8eae9c3551a4078bd48c3f187e694ba6837 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/2358 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Mon Feb 11 21:30:11 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Feb 11 21:51:05 2013, giving +2 See http://review.coreboot.org/2358 for details. -gerrit

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coreboot February 2013