coreboot February 2013

coreboot@coreboot.org

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Patch set updated for coreboot: 692bcc1 libpayload: Make the 'default serial address' menu item available only on X86
by Ronald G. Minnich 14 Feb '13

14 Feb '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2388 -gerrit commit 692bcc1b975690c855586cc464bc61eaab3ce408 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Feb 14 10:07:48 2013 -0800 libpayload: Make the 'default serial address' menu item available only on X86 PCs are lucky, they've had a default serial port for 30+ years, longer than most coreboot committers have walked the earth. ARMs are insane. There is no "standard" serial port address. If there were, the vendors would feel inclined to change it. ARMs must always inherit a serial port config from coreboot. Don't even bother asking. Change-Id: I6ecc3c78b8a1e1c20178c3cbf8b47c67ef76792f Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- payloads/libpayload/Config.in | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in index a14291d..3a9dad7 100644 --- a/payloads/libpayload/Config.in +++ b/payloads/libpayload/Config.in @@ -170,7 +170,7 @@ config SERIAL_CONSOLE config SERIAL_IOBASE hex "I/O base for the serial port (default 0x3f8)" - depends on SERIAL_CONSOLE + depends on ARCH_X86 && SERIAL_CONSOLE default 0x3f8 config SERIAL_SET_SPEED

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Patch merged into coreboot/master: 7df4ec0 Chromebooks: mainboard.c: Do not spell Chromebook in CamelCase
by gerrit＠coreboot.org 14 Feb '13

14 Feb '13

the following patch was just integrated into master: commit 7df4ec03035d0bbc6f206527164ac4839d29cd0b Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Feb 12 13:12:51 2013 +0100 Chromebooks: mainboard.c: Do not spell Chromebook in CamelCase »Chromebook« is the official spelling [1]. So correct that with the following command. $ git grep -l ChromeBook | xargs sed -i s,ChromeBook,Chromebook, The incorrect spelling was only used for the chip name. [1] http://www.google.com/intl/en/chrome/devices/hp-pavilion-chromebook.html#hp… Change-Id: I9c19f399a3e3d36bd644ec375822daa384a14961 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2370 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Feb 12 13:26:24 2013, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Thu Feb 14 19:25:54 2013, giving +2 See http://review.coreboot.org/2370 for details. -gerrit

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Patch merged into coreboot/master: 835df77 Google Butterfly: thermal.h: Align macro content
by gerrit＠coreboot.org 14 Feb '13

14 Feb '13

the following patch was just integrated into master: commit 835df770e37b42c9a842ffe1696689bc21ad90e1 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Feb 12 12:51:25 2013 +0100 Google Butterfly: thermal.h: Align macro content Change-Id: I3729f9bf66fcd72fa8870bb56a9c253a7368c774 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2371 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Feb 12 13:34:05 2013, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Thu Feb 14 19:24:46 2013, giving +2 See http://review.coreboot.org/2371 for details. -gerrit

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New patch to review for coreboot: d1ab5c7 libpayload: Make the 'default serial address' menu item available only on X86
by Ronald G. Minnich 14 Feb '13

14 Feb '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2388 -gerrit commit d1ab5c7aa21cecd5db2531016c60c8e52714d8a2 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Feb 14 10:07:48 2013 -0800 libpayload: Make the 'default serial address' menu item available only on X86 PCs are lucky, they've had a default serial port for 30+ years, longer than most coreboot committers have walked the earth. ARMs are insane. There is no "standard" serial port address. If there were, the vendors would feel inclined to change it. ARMs must always inherit a serial port config from coreboot. Don't even bother asking. Change-Id: I6ecc3c78b8a1e1c20178c3cbf8b47c67ef76792f Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- payloads/libpayload/Config.in | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in index a14291d..3a9dad7 100644 --- a/payloads/libpayload/Config.in +++ b/payloads/libpayload/Config.in @@ -170,7 +170,7 @@ config SERIAL_CONSOLE config SERIAL_IOBASE hex "I/O base for the serial port (default 0x3f8)" - depends on SERIAL_CONSOLE + depends on ARCH_X86 && SERIAL_CONSOLE default 0x3f8 config SERIAL_SET_SPEED

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New patch to review for coreboot: f13413b Get libpayload to compile cleanly for ARMV7
by Ronald G. Minnich 14 Feb '13

14 Feb '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2387 -gerrit commit f13413bc194d82f3a68e334e4445a01864b97717 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Feb 14 09:54:57 2013 -0800 Get libpayload to compile cleanly for ARMV7 There were just a few nits: on ARM, in/out and read/write are the same, so create synonyms. Get rid of some the nested if bits; add needed function prototypes (that did not used to be needed). This is prep work for getting more ARM drivers into libpayload. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Change-Id: I1e0b2af4a3aaf314b5cdd8a46ec2cb2663ee684e Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- payloads/libpayload/include/armv7/arch/io.h | 10 ++++++++++ payloads/libpayload/include/libpayload.h | 5 +++++ payloads/libpayload/libc/time.c | 19 +++++++++++++------ 3 files changed, 28 insertions(+), 6 deletions(-) diff --git a/payloads/libpayload/include/armv7/arch/io.h b/payloads/libpayload/include/armv7/arch/io.h index e71e1dd..6f4c621 100644 --- a/payloads/libpayload/include/armv7/arch/io.h +++ b/payloads/libpayload/include/armv7/arch/io.h @@ -31,12 +31,22 @@ #ifndef _ARCH_IO_H #define _ARCH_IO_H +/* x86 has to differentiate between inb/readb. + * No such issue on arm, but we still need to define both + * types of operations. + */ #define readb(_a) (*(volatile unsigned char *) (_a)) #define readw(_a) (*(volatile unsigned short *) (_a)) #define readl(_a) (*(volatile unsigned long *) (_a)) +#define inb(_a) (*(volatile unsigned char *) (_a)) +#define inw(_a) (*(volatile unsigned short *) (_a)) +#define inl(_a) (*(volatile unsigned long *) (_a)) #define writeb(_v, _a) (*(volatile unsigned char *) (_a) = (_v)) #define writew(_v, _a) (*(volatile unsigned short *) (_a) = (_v)) #define writel(_v, _a) (*(volatile unsigned long *) (_a) = (_v)) +#define outb(_v, _a) (*(volatile unsigned char *) (_a) = (_v)) +#define outw(_v, _a) (*(volatile unsigned short *) (_a) = (_v)) +#define outl(_v, _a) (*(volatile unsigned long *) (_a) = (_v)) #endif diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index eaa0d0d..d1b9de8 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -294,6 +294,11 @@ long long int llabs(long long int j); u8 bin2hex(u8 b); u8 hex2bin(u8 h); void fatal(const char *msg) __attribute__ ((noreturn)); + +void *default_memset(void *s, int c, size_t n); +void *default_memcpy(void *dst, const void *src, size_t n); +void *default_memmove(void *dst, const void *src, size_t n); +int default_memcmp(const void *s1, const void *s2, size_t len); /** @} */ diff --git a/payloads/libpayload/libc/time.c b/payloads/libpayload/libc/time.c index 5358c02..91f6296 100644 --- a/payloads/libpayload/libc/time.c +++ b/payloads/libpayload/libc/time.c @@ -110,14 +110,20 @@ static void gettimeofday_init(void) clock.secs = (days * 86400) + (tm.tm_hour * 3600) + (tm.tm_min * 60) + tm.tm_sec; } -#else +#endif // CONFIG_NVRAM +#endif // CONFIG_ARCH_X86 + +#ifdef CONFIG_ARCH_ARMV7 +static void update_clock(void) +{ +} + static void gettimeofday_init(void) { - /* Record the number of ticks */ - clock.ticks = rdtsc(); } -#endif -#endif +#endif // CONFIG_ARCH_ARMV7 + + #ifdef CONFIG_ARCH_POWERPC static void update_clock(void) { @@ -126,7 +132,8 @@ static void update_clock(void) static void gettimeofday_init(void) { } -#endif +#endif // CONFIG_ARCH_POWERPC + /** * Return the current time broken into a timeval structure. *

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Patch set updated for coreboot: 69a8252 OT200: add CMOS support
by Christian Gmeiner 14 Feb '13

14 Feb '13

Christian Gmeiner (christian.gmeiner(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2382 -gerrit commit 69a8252025a2c440d13e6cb099849641772a15ab Author: Christian Gmeiner <christian.gmeiner(a)gmail.com> Date: Thu Feb 14 12:08:30 2013 +0100 OT200: add CMOS support nvramtool works as expected. root@CHGM-DEV-OT200:~# /home/vis/nvramtool -a baud_rate = 19200 debug_level = Emergency Change-Id: Ia25dc5b4f0ed3a2dd7cc67b7d3174db3a6eff70e Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- src/mainboard/bachmann/ot200/Kconfig | 1 + src/mainboard/bachmann/ot200/cmos.layout | 61 ++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) diff --git a/src/mainboard/bachmann/ot200/Kconfig b/src/mainboard/bachmann/ot200/Kconfig index 5d185c0..0bf4a70 100644 --- a/src/mainboard/bachmann/ot200/Kconfig +++ b/src/mainboard/bachmann/ot200/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DRIVERS_I2C_IDREG select PLL_MANUAL_CONFIG select CORE_GLIU_500_266 + select HAVE_OPTION_TABLE config MAINBOARD_DIR string diff --git a/src/mainboard/bachmann/ot200/cmos.layout b/src/mainboard/bachmann/ot200/cmos.layout new file mode 100644 index 0000000..90ade93 --- /dev/null +++ b/src/mainboard/bachmann/ot200/cmos.layout @@ -0,0 +1,61 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Bachmann electronic GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +entries + +#start-bit length config config-ID name +# ----------------------------------------------------------------- +# RTC reserved +0 384 r 0 reserved_memory + +# ----------------------------------------------------------------- +# coreboot config options: console +384 3 e 1 baud_rate +387 4 e 2 debug_level + +# ----------------------------------------------------------------- +# coreboot config options: check sums +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 115200 +1 1 57600 +1 2 38400 +1 3 19200 +1 4 9600 +1 5 4800 +1 6 2400 +1 7 1200 +2 0 Emergency +2 1 Alert +2 2 Critical +2 3 Error +2 4 Warning +2 5 Notice +2 6 Info +2 7 Debug +2 8 Spew + +checksums + +checksum 400 1007 1008 + +

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Patch merged into coreboot/master: 0aa37c4 sconfig: rename lapic_cluster -> cpu_cluster
by gerrit＠coreboot.org 14 Feb '13

14 Feb '13

the following patch was just integrated into master: commit 0aa37c488bf785466e0db9897805ebf287af48eb Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Feb 12 15:20:54 2013 -0800 sconfig: rename lapic_cluster -> cpu_cluster The name lapic_cluster is a bit misleading, since the construct is not local APIC specific by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-x86 systems without adding new keywords. Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2377 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Feb 14 05:21:55 2013, giving +1 Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Thu Feb 14 05:06:55 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Feb 14 07:07:15 2013, giving +2 See http://review.coreboot.org/2377 for details. -gerrit

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Patch merged into coreboot/master: 398e84c armv7: don't write a forward entry in coreboot tables
by gerrit＠coreboot.org 14 Feb '13

14 Feb '13

the following patch was just integrated into master: commit 398e84c71a15b7db8c631bb5b17d1a1a60c91128 Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Feb 13 20:00:49 2013 -0800 armv7: don't write a forward entry in coreboot tables We don't seem to need it, and it currently confuses the payload. (credit to Gabe Black for this, I'm just uploading it) Change-Id: I4e3a60eceb9b24e3bc8e50db431c1a731d1cdbae Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/2385 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Feb 14 05:10:54 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Feb 14 07:05:04 2013, giving +2 See http://review.coreboot.org/2385 for details. -gerrit

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Patch merged into coreboot/master: a86e4ba snow: Set up MMU after DRAM is working
by gerrit＠coreboot.org 14 Feb '13

14 Feb '13

the following patch was just integrated into master: commit a86e4ba8bdc7fd45ab76697d32d4e95cf3116700 Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Feb 12 15:37:12 2013 -0800 snow: Set up MMU after DRAM is working This was omitted earlier while we were debugging DRAM code (0a5bc7f). It was likely broken due to inconsistent units earlier on. Now that things are cleaned up and working, let's add it back in. Change-Id: I2f356355c98b2896e2371fa63b9c9f20ae76d634 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2379 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Feb 14 05:40:32 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Feb 14 07:03:55 2013, giving +2 See http://review.coreboot.org/2379 for details. -gerrit

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Patch merged into coreboot/master: 2d0b55b snow: remove superfluous printk's from romstage main
by gerrit＠coreboot.org 14 Feb '13

14 Feb '13

the following patch was just integrated into master: commit 2d0b55bd6bfc2985950224dbca29668cc1aa7eba Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Feb 13 20:29:27 2013 -0800 snow: remove superfluous printk's from romstage main These were left over from earlier debugging and are no longer needed. They don't indicate any status or useful info (other than which line of code has been executed). Error messages are available in case something needs attention. Change-Id: Ie09fac29c42908cb8924169e56d8927fb76f02da Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2386 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Feb 14 05:48:27 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Feb 14 07:02:54 2013, giving +2 See http://review.coreboot.org/2386 for details. -gerrit

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coreboot February 2013