David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2379
-gerrit
commit bc339887c5fa0ebb6672324faa60f038e185a0c0
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Tue Feb 12 15:37:12 2013 -0800
snow: call mmu_setup()
This was omitted earlier while we were debugging DRAM code. May as
well add it back in.
Change-Id: I2f356355c98b2896e2371fa63b9c9f20ae76d634
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
---
src/mainboard/google/snow/romstage.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c
index 719337b..a125227 100644
--- a/src/mainboard/google/snow/romstage.c
+++ b/src/mainboard/google/snow/romstage.c
@@ -85,6 +85,9 @@ void main(void)
printk(BIOS_INFO, "ddr3_init done\n");
+ mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB);
+ printk(BIOS_INFO, "mmu_setup done\n");
+
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry);
David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2378
-gerrit
commit a49b67e2063130e3286aab52607785fd237375e5
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Tue Feb 12 15:30:17 2013 -0800
armv7: use start and size parameters in mmu_setup()
mmu_setup() was originally written in U-Boot to utilize board-specific
global data. Since we're trying to avoid that, we added start and size
parameters so that board-specific info can be passed in via mainboard
code. Let's start using it that way.
Change-Id: I7d7de0e42bd918c9f9f0c177acaf56c110bf8353
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
---
src/arch/armv7/lib/cache-cp15.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/arch/armv7/lib/cache-cp15.c b/src/arch/armv7/lib/cache-cp15.c
index f51ee48..cfbdb94 100644
--- a/src/arch/armv7/lib/cache-cp15.c
+++ b/src/arch/armv7/lib/cache-cp15.c
@@ -114,7 +114,7 @@ static inline void dram_bank_mmu_setup(unsigned long start, unsigned long size)
}
/* to activate the MMU we need to set up virtual memory: use 1M areas */
-inline void mmu_setup(unsigned long start, unsigned long size)
+inline void mmu_setup(unsigned long start, unsigned long size_mb)
{
int i;
u32 reg;
@@ -125,7 +125,7 @@ inline void mmu_setup(unsigned long start, unsigned long size)
for (i = 0; i < 4096; i++)
set_section_dcache(i, DCACHE_OFF);
- dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB << 20);
+ dram_bank_mmu_setup(start, size_mb << 20);
/* Copy the page table address to cp15 */
asm volatile("mcr p15, 0, %0, c2, c0, 0"
David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2379
-gerrit
commit 6001b5c671ddd1d059cc6f68ae0bd6e107bcc1a5
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Tue Feb 12 15:37:12 2013 -0800
snow: call mmu_setup()
This was omitted earlier while we were debugging DRAM code. May as
well add it back in.
Change-Id: I2f356355c98b2896e2371fa63b9c9f20ae76d634
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
---
src/mainboard/google/snow/romstage.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c
index 719337b..a125227 100644
--- a/src/mainboard/google/snow/romstage.c
+++ b/src/mainboard/google/snow/romstage.c
@@ -85,6 +85,9 @@ void main(void)
printk(BIOS_INFO, "ddr3_init done\n");
+ mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB);
+ printk(BIOS_INFO, "mmu_setup done\n");
+
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry);
David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2378
-gerrit
commit cbcd1c09bd8069e76b6c5bf85bf3cf0fa212fbc1
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Tue Feb 12 15:30:17 2013 -0800
armv7: use start and size parameters in mmu_setup()
mmu_setup() was originally written in U-Boot to utilize board-specific
global data. Since we're trying to avoid that, we added start and size
parameters so that board-specific info can be passed in via mainboard
code. Let's start using it that.
Change-Id: I7d7de0e42bd918c9f9f0c177acaf56c110bf8353
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
---
src/arch/armv7/lib/cache-cp15.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/arch/armv7/lib/cache-cp15.c b/src/arch/armv7/lib/cache-cp15.c
index f51ee48..cfbdb94 100644
--- a/src/arch/armv7/lib/cache-cp15.c
+++ b/src/arch/armv7/lib/cache-cp15.c
@@ -114,7 +114,7 @@ static inline void dram_bank_mmu_setup(unsigned long start, unsigned long size)
}
/* to activate the MMU we need to set up virtual memory: use 1M areas */
-inline void mmu_setup(unsigned long start, unsigned long size)
+inline void mmu_setup(unsigned long start, unsigned long size_mb)
{
int i;
u32 reg;
@@ -125,7 +125,7 @@ inline void mmu_setup(unsigned long start, unsigned long size)
for (i = 0; i < 4096; i++)
set_section_dcache(i, DCACHE_OFF);
- dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB << 20);
+ dram_bank_mmu_setup(start, size_mb << 20);
/* Copy the page table address to cp15 */
asm volatile("mcr p15, 0, %0, c2, c0, 0"
I am looking for the Linux Bios for the Transmata TM5600 (Emergecore IT-100/
FIC Maat II server).
We have a couple of thousands of these systems. They are limited to
128MB RAM. We think it is a BIOS limit. Supposedly, it should be
expandable to
512MB per Transmeta literature.
We are willing to pay for the development. Contact us if you think there is a
way to implement the Linux Bios to increase the memory space
--
Best Regards.
Bao C. Ha
Hacom - Embedded Systems and Appliances
http://www.hacom.net
voice: (714) 564-9932
the following patch was just integrated into master:
commit 1b6fecd64d40cae3693d5424a26b9f34e419fd06
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Tue Feb 12 13:41:14 2013 +0100
armv7: stages.c: Fix grammar: s,The is to,This is to,
The comment introduced in
commit 50c0a50ac6a3fa54ed1286e8b76f933701b6d053
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Thu Jan 31 17:05:50 2013 -0800
armv7: unify stage hand-off routines
Reviewed-on: http://review.coreboot.org/2254
contained a typo, which is corrected now.
Change-Id: I87f7cfa82fcd12b6961d3329e634b4c201cc047e
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2372
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Tue Feb 12 14:18:04 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Feb 12 17:38:08 2013, giving +2
See http://review.coreboot.org/2372 for details.
-gerrit
the following patch was just integrated into master:
commit fd72d5a838875d02277099eee065faed77d4eecb
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Tue Feb 12 12:30:26 2013 +0100
Google Butterfly: acpi/thermal.asl: Fix typo »The*re* is no …«
The commit introducing support for the Google Butterfly Chromebook
commit d7bd4eb003f5b6a13943418ae0ac53248a2e34d2
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Mon Feb 11 11:11:36 2013 -0800
Add support for "Butterfly" Chromebook
Reviewed-on: http://review.coreboot.org/2359
contains the typo, which is corrected now.
Change-Id: I932f4cd248cac71c3ede39a7da97162e791827cb
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2373
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-by: Peter Stuge <peter(a)stuge.se>
Build-Tested: build bot (Jenkins) at Tue Feb 12 13:59:56 2013, giving +1
Reviewed-By: Peter Stuge <peter(a)stuge.se> at Tue Feb 12 16:40:51 2013, giving +2
See http://review.coreboot.org/2373 for details.
-gerrit
the following patch was just integrated into master:
commit 1236b842347c1b0671aa56ed80fa0278ded8d6cc
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Tue Feb 12 10:32:00 2013 +0100
Google Butterfly: gpio.h: Correct whitespace errors
Correct some whitespace inconsistencies introduced in the
following commit.
commit d7bd4eb003f5b6a13943418ae0ac53248a2e34d2
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Mon Feb 11 11:11:36 2013 -0800
Add support for "Butterfly" Chromebook
Reviewed-on: http://review.coreboot.org/2359
Change-Id: Ifeda7eb29ddf855cdfea41ddbd685441ede55756
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2374
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov(a)gmail.com>
Build-Tested: build bot (Jenkins) at Tue Feb 12 14:37:02 2013, giving +1
Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Tue Feb 12 15:27:57 2013, giving +2
See http://review.coreboot.org/2374 for details.
-gerrit