David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2386
-gerrit
commit 9893316859618bc3c42c457e58e3e566b455d205
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Wed Feb 13 20:29:27 2013 -0800
snow: remove superfluous printk's from romstage main
These were left over from earlier debugging and are no longer
needed. They don't indicate any status or useful info (other
than which line of code has been executed). Error messages are
available in case something needs attention.
Change-Id: Ie09fac29c42908cb8924169e56d8927fb76f02da
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
---
src/mainboard/google/snow/romstage.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c
index f6f858c..9891011 100644
--- a/src/mainboard/google/snow/romstage.c
+++ b/src/mainboard/google/snow/romstage.c
@@ -64,7 +64,6 @@ void main(void)
system_clock_init(mem, arm_ratios);
console_init();
- printk(BIOS_INFO, "hello from romstage\n");
if (!mem) {
printk(BIOS_CRIT, "Unable to auto-detect memory timings\n");
@@ -83,8 +82,6 @@ void main(void)
while(1);
}
- printk(BIOS_INFO, "ddr3_init done\n");
-
mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB);
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2379
-gerrit
commit 5696e9df858e0969d3ea0aa4aa8b3b3e9a43bbb5
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Tue Feb 12 15:37:12 2013 -0800
snow: Set up MMU after DRAM is working
This was omitted earlier while we were debugging DRAM code (0a5bc7f).
It was likely broken due to inconsistent units earlier on. Now that
things are cleaned up and working, let's add it back in.
Change-Id: I2f356355c98b2896e2371fa63b9c9f20ae76d634
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
---
src/mainboard/google/snow/romstage.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c
index 719337b..f6f858c 100644
--- a/src/mainboard/google/snow/romstage.c
+++ b/src/mainboard/google/snow/romstage.c
@@ -85,6 +85,8 @@ void main(void)
printk(BIOS_INFO, "ddr3_init done\n");
+ mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB);
+
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry);
David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2385
-gerrit
commit 25b5ce286fa0c8603e1d5401f248f7434304f76f
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Wed Feb 13 20:00:49 2013 -0800
armv7: don't write a forward entry in coreboot tables
We don't seem to need it, and it currently confuses the payload.
(credit to Gabe Black for this, I'm just uploading it)
Change-Id: I4e3a60eceb9b24e3bc8e50db431c1a731d1cdbae
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/arch/armv7/boot/coreboot_table.c | 18 ------------------
1 file changed, 18 deletions(-)
diff --git a/src/arch/armv7/boot/coreboot_table.c b/src/arch/armv7/boot/coreboot_table.c
index ed105a4..64f6a66 100644
--- a/src/arch/armv7/boot/coreboot_table.c
+++ b/src/arch/armv7/boot/coreboot_table.c
@@ -329,20 +329,6 @@ static void lb_strings(struct lb_header *header)
}
-#if CONFIG_WRITE_HIGH_TABLES
-static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header *next_header)
-{
- struct lb_record *rec;
- struct lb_forward *forward;
- rec = lb_new_record(header);
- forward = (struct lb_forward *)rec;
- forward->tag = LB_TAG_FORWARD;
- forward->size = sizeof(*forward);
- forward->forward = (uint64_t)(unsigned long)next_header;
- return forward;
-}
-#endif
-
/* FIXME(dhendrix): used to be static void lb_memory_range(), but compiler
started complaining since it shares a name with a non-static struct. ugh. */
static void new_lb_memory_range(struct lb_memory *mem,
@@ -612,10 +598,6 @@ unsigned long write_coreboot_table(
table_start, table_end);
head = lb_table_init(table_start);
- printk(BIOS_DEBUG, "Writing table forward entry at 0x%08lx\n",
- table_end);
- lb_forward(head, (struct lb_header*)table_end);
-
table_end = (unsigned long) head + head->table_bytes;
/* FIXME(dhendrix): do we need this? */
the following patch was just integrated into master:
commit 4aff4458f58398f54c248604694c7005294c1747
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Tue Feb 12 14:17:15 2013 -0800
sconfig: rename pci_domain -> domain
The name pci_domain was a bit misleading, since the construct is only
PCI specific in a particular (northbridge/cpu) implementation, but not
by concept. As implementations and hardware change, be more generic
about our naming. This will allow us to support non-PCI systems without
adding new keywords.
Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: http://review.coreboot.org/2376
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Thu Feb 14 01:15:33 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Feb 14 02:00:04 2013, giving +2
See http://review.coreboot.org/2376 for details.
-gerrit
the following patch was just integrated into master:
commit dc8259ce1d2e866f3133da49c1d6f4773f5698c1
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Tue Feb 12 22:57:04 2013 -0800
armv7/exynos: remove some stale files leftover from initial import
This removes some files leftover from the initial port. Some are
leftover from U-Boot and some were leftover from the skeleton code
derived from x86.
There's a bit more that we'll get in another sweep.
Change-Id: I325793ecb902b3b9430dcf531714ce025d201de6
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-on: http://review.coreboot.org/2380
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Build-Tested: build bot (Jenkins) at Wed Feb 13 08:30:14 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Feb 13 21:22:51 2013, giving +2
See http://review.coreboot.org/2380 for details.
-gerrit
Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2383
-gerrit
commit a6ac626f7c63d5ce8a56b98524cf24e9c7f5ff64
Author: Zheng Bao <fishbaozi(a)gmail.com>
Date: Wed Feb 13 22:13:13 2013 +0800
AMD S3: Introduce Kconfig variable 'S3_VOLATILE_SIZE'
The size of volatile storage for S3 can be configured.
The space is divided into several parts. Make sure the
sum of each part is not above the limit.
Change-Id: I9152797cf0045c8da48109a9d760e417717686db
Signed-off-by: Zheng Bao <zheng.bao(a)amd.com>
Signed-off-by: zheng Bao <fishbaozi(a)gmail.com>
---
src/cpu/amd/agesa/s3_resume.h | 5 +++++
src/southbridge/amd/Makefile.inc | 2 +-
src/southbridge/amd/agesa/hudson/Kconfig | 8 ++++++++
src/southbridge/amd/cimx/sb700/Kconfig | 7 +++++++
src/southbridge/amd/cimx/sb800/Kconfig | 8 ++++++++
src/southbridge/amd/cimx/sb900/Kconfig | 8 ++++++++
6 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h
index 39ad30a..dc4f453 100644
--- a/src/cpu/amd/agesa/s3_resume.h
+++ b/src/cpu/amd/agesa/s3_resume.h
@@ -28,6 +28,11 @@
#define S3_DATA_MTRR_POS (CONFIG_S3_VOLATILE_POS + S3_DATA_VOLATILE_SIZE)
#define S3_DATA_NONVOLATILE_POS (CONFIG_S3_VOLATILE_POS + S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE)
+#if (S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_VOLATILE_SIZE
+#error "Please increase the value of S3_VOLATILE_SIZE"
+#endif
+
+
typedef enum {
S3DataTypeNonVolatile=0, ///< NonVolatile Data Type
S3DataTypeVolatile ///< Volatile Data Type
diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc
index 1b2cb1f..b6af980 100644
--- a/src/southbridge/amd/Makefile.inc
+++ b/src/southbridge/amd/Makefile.inc
@@ -22,7 +22,7 @@ ifeq ($(CONFIG_CPU_AMD_AGESA), y)
$(obj)/coreboot_s3nv.rom: $(obj)/config.h
echo " S3 NVRAM $(CONFIG_S3_VOLATILE_POS) (S3 storage area)"
# force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse)
- LC_ALL=C awk 'BEGIN {for (i=0; i<32768; i++) {printf "%c", 255}}' > $@.tmp
+ printf %d $(CONFIG_S3_VOLATILE_SIZE) | LC_ALL=C awk '{for (i=0; i<$$1; i++) {printf "%c", 255}}' > $@.tmp
mv $@.tmp $@
cbfs-files-y += s3nv
diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig
index 92e5960..c652670 100644
--- a/src/southbridge/amd/agesa/hudson/Kconfig
+++ b/src/southbridge/amd/agesa/hudson/Kconfig
@@ -212,6 +212,14 @@ config S3_VOLATILE_POS
For a system with S3 feature, the BIOS needs to save some data to
non-volitile storage at cold boot stage.
+config S3_VOLATILE_SIZE
+ hex "S3 volatile storage size"
+ default 0x8000
+ depends on HAVE_ACPI_RESUME
+ help
+ For a system with S3 feature, the BIOS needs to save some data to
+ non-volitile storage at cold boot stage.
+
config HUDSON_LEGACY_FREE
bool "System is legacy free"
help
diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig
index f139450..4105393 100644
--- a/src/southbridge/amd/cimx/sb700/Kconfig
+++ b/src/southbridge/amd/cimx/sb700/Kconfig
@@ -68,5 +68,12 @@ config S3_VOLATILE_POS
For a system with S3 feature, the BIOS needs to save some data to
non-volitile storage at cold boot stage.
+config S3_VOLATILE_SIZE
+ hex "S3 volatile storage size"
+ default 0x8000
+ depends on HAVE_ACPI_RESUME
+ help
+ For a system with S3 feature, the BIOS needs to save some data to
+ non-volitile storage at cold boot stage.
endif #SOUTHBRIDGE_AMD_CIMX_SB700
diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index 1f3ee9a..9add77b 100644
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -130,6 +130,14 @@ config S3_VOLATILE_POS
For a system with S3 feature, the BIOS needs to save some data to
non-volitile storage at cold boot stage.
+config S3_VOLATILE_SIZE
+ hex "S3 volatile storage size"
+ default 0x8000
+ depends on HAVE_ACPI_RESUME
+ help
+ For a system with S3 feature, the BIOS needs to save some data to
+ non-volitile storage at cold boot stage.
+
config SB800_IMC_FWM
bool "Add IMC firmware"
default n
diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig
index acc369e..862589c 100755
--- a/src/southbridge/amd/cimx/sb900/Kconfig
+++ b/src/southbridge/amd/cimx/sb900/Kconfig
@@ -61,5 +61,13 @@ config S3_VOLATILE_POS
For a system with S3 feature, the BIOS needs to save some data to
non-volitile storage at cold boot stage.
+config S3_VOLATILE_SIZE
+ hex "S3 volatile storage size"
+ default 0x8000
+ depends on HAVE_ACPI_RESUME
+ help
+ For a system with S3 feature, the BIOS needs to save some data to
+ non-volitile storage at cold boot stage.
+
endif #SOUTHBRIDGE_AMD_CIMX_SB900