coreboot August 2012

coreboot@coreboot.org

30 participants
321 discussions

New patch to review for coreboot: f80c3d9 Trivial: Change <tab># to <tab>@# in Makefile command
by Zheng Bao 03 Aug '12

03 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1401 -gerrit commit f80c3d9eff0d31d02cf8f541a55b3576dc89aedc Author: zbao <fishbaozi(a)gmail.com> Date: Fri Aug 3 14:56:49 2012 +0800 Trivial: Change <tab># to <tab>@# in Makefile command My editor highlights the <tab># as syntax error. I think it is because every line starting with a <tab> is seen as a command. But # is not a makefile accepted command, is it? I found in {top}/Makefile.inc there are some <tab>@#. So I think every makefile should sync with that format. Change-Id: Ib86165df4fefff3007693f9b8077a5a0a00bb6d3 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- Makefile.inc | 2 +- documentation/Makefile | 2 +- payloads/external/FILO/Makefile.inc | 4 ++-- payloads/external/SeaBIOS/Makefile.inc | 4 ++-- src/southbridge/amd/Makefile.inc | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index ca1e066..4259cad 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -95,7 +95,7 @@ $(obj)/$(1).ramstage.o: src/$(1).asl $(obj)/config.h cd $$(dir $$@); $(IASL) -p $$(notdir $$@) -tc $$(notdir $$(basename $$(a))).asl mv $$(basename $$(a)).hex $$(basename $$(a)).c $(CC) $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $(1)))), -DAmlCode=AmlCode_$$(basename $$(notdir $(1)))) -c -o $$@ $$(basename $$(a)).c - # keep %.o: %.c rule from catching the temporary .c file after a make clean + @# keep %.o: %.c rule from catching the temporary .c file after a make clean mv $$(basename $$(a)).c $$(basename $$(a)).hex endef diff --git a/documentation/Makefile b/documentation/Makefile index 84ac0b5..1a19828 100644 --- a/documentation/Makefile +++ b/documentation/Makefile @@ -32,7 +32,7 @@ else ifneq ($(strip $(CONVERT)),) endif LinuxBIOS-AMD64.toc: $(FIGS) LinuxBIOS-AMD64.tex - # 2 times to make sure we have a current toc. + @# 2 times to make sure we have a current toc. $(PDFLATEX) LinuxBIOS-AMD64.tex $(PDFLATEX) LinuxBIOS-AMD64.tex diff --git a/payloads/external/FILO/Makefile.inc b/payloads/external/FILO/Makefile.inc index 311b3c8..cce075b 100644 --- a/payloads/external/FILO/Makefile.inc +++ b/payloads/external/FILO/Makefile.inc @@ -27,8 +27,8 @@ config: libpayload echo "CONFIG_LZMA=y" >> filo/.config echo "CONFIG_FLASH_FLOPPY=y" >> filo/.config echo "CONFIG_VGAHOOKS=y" >> filo/.config - # This shows how to force a previously set .config option *off* - #echo "# CONFIG_SMBIOS is not set" >> filo/.config + @# This shows how to force a previously set .config option *off* + @#echo "# CONFIG_SMBIOS is not set" >> filo/.config filo: config echo " MAKE FILO $(NAME-y)" diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index e0f03b1..8e47576 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -29,8 +29,8 @@ config: checkout echo "CONFIG_LZMA=y" >> $(OUT)/seabios/.config echo "CONFIG_FLASH_FLOPPY=y" >> $(OUT)/seabios/.config echo "CONFIG_VGAHOOKS=y" >> $(OUT)/seabios/.config - # This shows how to force a previously set .config option *off* - #echo "# CONFIG_SMBIOS is not set" >> $(OUT)/seabios/.config + @# This shows how to force a previously set .config option *off* + @#echo "# CONFIG_SMBIOS is not set" >> $(OUT)/seabios/.config build: config echo " MAKE SeaBIOS $(TAG-y)" diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index 9709715..733a9bc 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -21,7 +21,7 @@ ifeq ($(CONFIG_CPU_AMD_AGESA), y) $(obj)/s3.rom: echo " S3 NVRAM 0xffff0000 (S3 storage area)" - # force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse) + @ # force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse) LC_ALL=C awk 'BEGIN {for (i=0; i<32768; i++) {printf "%c", 255}}' > $@.tmp mv $@.tmp $@

1 0

New patch to review for coreboot: 7930ea3 AMD S3: Add a document about S3 on AMD platform
by Zheng Bao 03 Aug '12

03 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1400 -gerrit commit 7930ea30fbd307013159deeb1aeee0ca80d05736 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Aug 3 13:53:10 2012 +0800 AMD S3: Add a document about S3 on AMD platform See the document. Need review. Everything should be in Authentic English. Change-Id: Idc528b8c6b0d5afe08fc4f4387b7bff30698f677 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- documentation/AMD-S3.txt | 95 ++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 95 insertions(+), 0 deletions(-) diff --git a/documentation/AMD-S3.txt b/documentation/AMD-S3.txt new file mode 100644 index 0000000..58ee0d7 --- /dev/null +++ b/documentation/AMD-S3.txt @@ -0,0 +1,95 @@ + _____ ____ _____ ______ ____ ____ ____ _______ + / ____/ __ \| __ \| ____| _ \ / __ \ / __ \__ __| + | | | | | | |__) | |__ | |_) | | | | | | | | | + | | | | | | _ /| __| | _ <| | | | | | | | | + | |___| |__| | | \ \| |____| |_) | |__| | |__| | | | + \_____\____/|_| \_\______|____/ \____/ \____/ |_| + + __ __ _____ _____ ____ + /\ | \/ | __ \ / ____| |___ \ + / \ | \ / | | | | | (___ __) | + / /\ \ | |\/| | | | | \___ \ |__ < + / ____ \| | | | |__| | ____) | ___) | + /_/ \_\_| |_|_____/ |_____/ |____/ + + + S3 in Coreboot +---------------------------------------- + Zheng Bao + <zheng.bao(a)amd.com> + <fishbaozi(a)gmail.com> + +Introduction +============ +This document is about how the feature S3 is implemented on coreboot, +specificly on AMD platform. This topic deals with ACPI spec, hardware, +BIOS, OS. We try to help coreboot users to realize their own S3. + +S3 in a nutshell +================ +The S3 sleeping state is a low wake latency sleeping state where all +system context is lost except system memory. [1]. S3 is a ACPI +definition. +To enter S3, write 3 in SLP_TYPx and setting the SLP_EN bit. But if +you do that, board can not resume at where it sleeps, because you +don't save the context. More often than not, we make the board go into +S3 by the tools which OSes provide. For windows, click +Start->sleep. For linux, some distribution provide a tools called +pm-suspend, which can make the system goto S3. If pm-suspend is not +available, we can run "echo mem > /sys/power/state", but this way may +not save all the needed context. +In S3 state, the power is off. So when the power button is pressed, +BIOS runs as it does in cold boot. If BIOS didn't detect whether +board boots or resume, it would go the same way as boot. It is not +what we expect. BIOS detects the SLP_TYPx. If it is 3, it means BIOS +are waking up. +BIOS is responsible for restore the machine state as it is before +sleep. It needs restore the memory controller, not overwriting memory +which is marked as reserved. For the peripheral which loses its +registers, BIOS needs to write the original value. +When everything is done, BIOS needs to find out the wakeup vector +provided by OSes and jump there. OSes also have work to do. We can go +to linux kernel or some other open source projects to find out how they +handle S3 resume. + +Memory Layout +============= +Restoring memory is the most important job done by BIOS. When the +power is off, the memory is maintained by standby power. BIOS need to +make sure that when flow goes to OS, everything in memory should be +the same as it was. + +The chip vendor will provide a way, or code, to wake up the memory +from sleeping. In AGESA 2008 arch, it is called AmdInitResume. + +The BIOS itself needs some memory to run. Either, BIOS marks the erea +as reserved in e820, or BIOS saves the content into reserved space. + +Here is the address Map for S3 Resume. Assumingly the total memory is 1GB. +00000000 --- 00100000 BIOS Reserved area. +00100000 --- 00200000 Free +00200000 --- 01000000 Coreboot ramstage area. +01000000 --- 2e160000 Free +2e160000 --- 2e170000 ACPI table +2e170000 --- 2ef70000 OSRAM +2ef70000 --- 2efe0000 Stack in highmem +2efe0000 --- 2f000000 heap in highmem +2f000000 TOM + +AMD requirements in S3 +====================== +Chip vendor like AMD will provide bunch of routines to restore the +board.[2] + * AmdS3Save: It is called in cold boot, save required register into + non-volatile storage. Currently, we use SPI flash to store the data. + * AmdInitResume: Restore the memory controller. + * AmdS3LateRestore: Called after AmdInitResume, restore other + register that memory. + * (SouthBridge)InitS3EarlyRestore, (SouthBridge)InitS3LateRestore: + Provided by Southbridge vendor code. Early is called before PCI + enumeration, and Late is called after that. + +Reference +========= +[1] ACPI40 +[2] Coreboot Vendorcode

1 0

New patch to review for coreboot: 6c493d7 AMD Parmer: Remove warning.
by Zheng Bao 03 Aug '12

03 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1399 -gerrit commit 6c493d7bf800fa4e295465f28f8813477121f917 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Aug 3 11:47:53 2012 +0800 AMD Parmer: Remove warning. Change-Id: I4ba2d480fa6df5ee741d887d26524b32c1901d73 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/parmer/acpi_tables.c | 2 +- src/mainboard/amd/parmer/mptable.c | 6 ------ 2 files changed, 1 insertions(+), 7 deletions(-) diff --git a/src/mainboard/amd/parmer/acpi_tables.c b/src/mainboard/amd/parmer/acpi_tables.c index c699d5b..0a64535 100644 --- a/src/mainboard/amd/parmer/acpi_tables.c +++ b/src/mainboard/amd/parmer/acpi_tables.c @@ -76,7 +76,7 @@ unsigned long acpi_fill_madt(unsigned long current) /* 5 mean: 0101 --> Edige-triggered, Active high */ /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi(current, 0xff, 5, 1); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); /* 1: LINT1 connect to NMI */ return current; diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c index 143920e..9dcc845 100644 --- a/src/mainboard/amd/parmer/mptable.c +++ b/src/mainboard/amd/parmer/mptable.c @@ -75,12 +75,6 @@ static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; - int boot_apic_id; - unsigned apic_version; - unsigned cpu_features; - unsigned cpu_feature_flags; - struct cpuid_result result; - unsigned long cpu_flag; u32 dword; u8 byte;

1 0

New patch to review for coreboot: c8584ce Make the device tree available in the rom stage
by Stefan Reinauer 03 Aug '12

03 Aug '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1398 -gerrit commit c8584cefd8799eebab5be4b5564bfc98a2cef468 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 31 16:47:25 2012 -0700 Make the device tree available in the rom stage We thought about two ways to do this change. The way we decided to try was to 1. drop all ops from devices in romstage 2. constify all devices in romstage (make them read-only) so we can compile static.c into romstage 3. the device tree "devices" can be used to read configuration from the device tree (and nothing else, really) 4. the device tree devices are accessed through struct device * in romstage only. device_t stays the typedef to int in romstage 5. Use the same static.c file in ramstage and romstage We declare structs as follows: ROMSTAGE_CONST struct bus dev_root_links[]; ROMSTAGE_CONST is const in romstage and empty in ramstage; This forces all of the device tree into the text area. So a struct looks like this: static ROMSTAGE_CONST struct device _dev21 = { #ifndef __PRE_RAM__ .ops = 0, #endif .bus = &_dev7_links[0], .path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}}, .enabled = 0, .on_mainboard = 1, .subsystem_vendor = 0x1ae0, .subsystem_device = 0xc000, .link_list = NULL, .sibling = &_dev22, #ifndef __PRE_RAM__ .chip_ops = &southbridge_intel_bd82x6x_ops, #endif .chip_info = &southbridge_intel_bd82x6x_info_10, .next=&_dev22 }; Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727 Signed-off-by: Ronald G. Minnich <rminnich(a)chromium.org> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- Makefile.inc | 5 +++ src/cpu/amd/agesa/s3_resume.c | 2 + src/devices/Makefile.inc | 2 + src/devices/device_romstage.c | 80 +++++++++++++++++++++++++++++++++++++++++ src/include/device/device.h | 38 ++++++++++++++------ src/include/device/pci.h | 3 ++ util/sconfig/main.c | 32 ++++++++++------ 7 files changed, 139 insertions(+), 23 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index ca1e066..083d423 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -228,6 +228,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/static.c: $(src)/mainboard/$(MAINBOARDDIR)/devi $(objutil)/sconfig/sconfig $(MAINBOARDDIR) $(obj)/mainboard/$(MAINBOARDDIR) ramstage-y+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c +romstage-y+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c $(objutil)/%.o: $(objutil)/%.c @printf " HOSTCC $(subst $(objutil)/,,$(@))\n" @@ -237,6 +238,10 @@ $(obj)/%.ramstage.o $(abspath $(obj))/%.ramstage.o: $(obj)/%.c $(obj)/config.h $ @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD $(CFLAGS) -c -o $@ $< +$(obj)/%.romstage.o $(abspath $(obj))/%.romstage.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -MMD -D__PRE_RAM__ $(CFLAGS) -c -o $@ $< + ####################################################################### # Clean up rules clean-abuild: diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 6bb053d..0348a9f 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -29,7 +29,9 @@ #endif #include <device/device.h> #include <device/pci.h> +#ifndef __PRE_RAM__ #include <device/pci_ops.h> +#endif #include <arch/io.h> #include <arch/acpi.h> #include <string.h> diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc index 9ffc0bb..9a2f71e 100644 --- a/src/devices/Makefile.inc +++ b/src/devices/Makefile.inc @@ -11,6 +11,8 @@ ramstage-y += pnp_device.c ramstage-y += pci_ops.c ramstage-y += smbus_ops.c +romstage-y+= device_romstage.c + subdirs-y += oprom ifeq ($(CONFIG_PCI_ROM_RUN),y) diff --git a/src/devices/device_romstage.c b/src/devices/device_romstage.c new file mode 100644 index 0000000..475f94a --- /dev/null +++ b/src/devices/device_romstage.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003-2004 Linux Networx + * (Written by Eric Biederman <ebiederman(a)lnxi.com> for Linux Networx) + * Copyright (C) 2003 Greg Watson <jarrah(a)users.sourceforge.net> + * Copyright (C) 2004 Li-Ta Lo <ollie(a)lanl.gov> + * Copyright (C) 2005-2006 Tyan + * (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/path.h> +#include <device/pci.h> +#include <device/resource.h> + +/** Linked list of ALL devices */ +ROMSTAGE_CONST struct device * ROMSTAGE_CONST all_devices = &dev_root; + +/** + * Given a PCI bus and a devfn number, find the device structure. + * + * @param bus The bus number. + * @param devfn A device/function number. + * @return Pointer to the device structure (if found), 0 otherwise. + */ +ROMSTAGE_CONST struct device *dev_find_slot(unsigned int bus, + unsigned int devfn) +{ + ROMSTAGE_CONST struct device *dev, *result; + + result = 0; + for (dev = all_devices; dev; dev = dev->next) { + if ((dev->path.type == DEVICE_PATH_PCI) && + (dev->bus->secondary == bus) && + (dev->path.pci.devfn == devfn)) { + result = dev; + break; + } + } + return result; +} + +/** + * Given an SMBus bus and a device number, find the device structure. + * + * @param bus The bus number. + * @param addr A device number. + * @return Pointer to the device structure (if found), 0 otherwise. + */ +ROMSTAGE_CONST struct device *dev_find_slot_on_smbus(unsigned int bus, + unsigned int addr) +{ + ROMSTAGE_CONST struct device *dev, *result; + + result = 0; + for (dev = all_devices; dev; dev = dev->next) { + if ((dev->path.type == DEVICE_PATH_I2C) && + (dev->bus->secondary == bus) && + (dev->path.i2c.device == addr)) { + result = dev; + break; + } + } + return result; +} + diff --git a/src/include/device/device.h b/src/include/device/device.h index 0b15ac5..88d73c7 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -5,8 +5,14 @@ #include <device/resource.h> #include <device/path.h> +#ifdef __PRE_RAM__ +#define ROMSTAGE_CONST const +#else +#define ROMSTAGE_CONST +#endif struct device; +#ifndef __PRE_RAM__ typedef struct device * device_t; struct pci_operations; struct pci_bus_operations; @@ -42,12 +48,14 @@ struct device_operations { const struct smbus_bus_operations *ops_smbus_bus; const struct pci_bus_operations *ops_pci_bus; }; +#endif struct bus { - device_t dev; /* This bridge device */ - device_t children; /* devices behind this bridge */ - struct bus *next; /* The next bridge on this device */ + + ROMSTAGE_CONST struct device * dev; /* This bridge device */ + ROMSTAGE_CONST struct device * children; /* devices behind this bridge */ + ROMSTAGE_CONST struct bus *next; /* The next bridge on this device */ unsigned bridge_ctrl; /* Bridge control register */ unsigned char link_num; /* The index of this link */ uint16_t secondary; /* secondary bus number */ @@ -70,10 +78,12 @@ struct pci_irq_info { }; struct device { - struct bus * bus; /* bus this device is on, for bridge + ROMSTAGE_CONST struct bus * bus; /* bus this device is on, for bridge * devices, it is the up stream bus */ - device_t sibling; /* next device on this bus */ - device_t next; /* chain of all devices */ + + ROMSTAGE_CONST struct device * sibling; /* next device on this bus */ + + ROMSTAGE_CONST struct device * next; /* chain of all devices */ struct device_path path; unsigned vendor; @@ -89,23 +99,24 @@ struct device { u8 command; /* Base registers for this device. I/O, MEM and Expansion ROM */ - struct resource *resource_list; + ROMSTAGE_CONST struct resource *resource_list; /* links are (downstream) buses attached to the device, usually a leaf * device with no children has 0 buses attached and a bridge has 1 bus */ - struct bus *link_list; + ROMSTAGE_CONST struct bus *link_list; struct device_operations *ops; const struct chip_operations *chip_ops; - void *chip_info; + ROMSTAGE_CONST void *chip_info; }; /** * This is the root of the device tree. The device tree is defined in the * static.c file and is generated by the config tool at compile time. */ -extern struct device dev_root; +extern ROMSTAGE_CONST struct device dev_root; +#ifndef __PRE_RAM__ extern struct device *all_devices; /* list of all devices */ extern struct resource *free_resources; @@ -195,5 +206,10 @@ void fixed_mem_resource(device_t dev, unsigned long index, void tolm_test(void *gp, struct device *dev, struct resource *new); u32 find_pci_tolm(struct bus *bus); - +#else +ROMSTAGE_CONST struct device * dev_find_slot (unsigned int bus, + unsigned int devfn); +ROMSTAGE_CONST struct device * dev_find_slot_on_smbus (unsigned int bus, + unsigned int addr); +#endif #endif /* DEVICE_H */ diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 51d5283..a215a2a 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -16,9 +16,11 @@ #define PCI_H #include <stdint.h> +#include <stddef.h> #include <device/pci_def.h> #include <device/resource.h> #include <device/device.h> +#ifndef __PRE_RAM__ #include <device/pci_ops.h> #include <device/pci_rom.h> @@ -107,4 +109,5 @@ static inline const struct pci_bus_operations *ops_pci_bus(struct bus *bus) unsigned mainboard_pci_subsystem_vendor_id(struct device *dev); unsigned mainboard_pci_subsystem_device_id(struct device *dev); +#endif #endif /* PCI_H */ diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 824bc6c..82a7491 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -366,13 +366,15 @@ void add_ioapic_info(struct device *dev, int apicid, const char *_srcpin, int ir static void pass0(FILE *fil, struct device *ptr) { if (ptr->type == device && ptr->id == 0) - fprintf(fil, "struct bus %s_links[];\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct bus %s_links[];\n", ptr->name); + if ((ptr->type == device) && (ptr->id != 0) && (!ptr->used)) { - fprintf(fil, "static struct device %s;\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST static struct device %s;\n", ptr->name); if (ptr->rescnt > 0) - fprintf(fil, "struct resource %s_res[];\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct resource %s_res[];\n", ptr->name); if (ptr->children || ptr->multidev) - fprintf(fil, "struct bus %s_links[];\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct bus %s_links[];\n", + ptr->name); } } @@ -382,8 +384,10 @@ static void pass1(FILE *fil, struct device *ptr) if (!ptr->used && (ptr->type == device)) { if (ptr->id != 0) fprintf(fil, "static "); - fprintf(fil, "struct device %s = {\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct device %s = {\n", ptr->name); + fprintf(fil, "#ifndef __PRE_RAM__\n"); fprintf(fil, "\t.ops = %s,\n", (ptr->ops)?(ptr->ops):"0"); + fprintf(fil, "#endif\n"); fprintf(fil, "\t.bus = &%s_links[%d],\n", ptr->bus->name, ptr->bus->link); fprintf(fil, "\t.path = {"); fprintf(fil, ptr->path, ptr->path_a, ptr->path_b); @@ -415,7 +419,9 @@ static void pass1(FILE *fil, struct device *ptr) if (ptr->sibling) fprintf(fil, "\t.sibling = &%s,\n", ptr->sibling->name); if (ptr->chip->chiph_exists) { + fprintf(fil, "#ifndef __PRE_RAM__\n"); fprintf(fil, "\t.chip_ops = &%s_ops,\n", ptr->chip->name_underscore); + fprintf(fil, "#endif\n"); fprintf(fil, "\t.chip_info = &%s_info_%d,\n", ptr->chip->name_underscore, ptr->chip->id); } if (ptr->nextdev) @@ -424,7 +430,8 @@ static void pass1(FILE *fil, struct device *ptr) } if (ptr->rescnt > 0) { int i=1; - fprintf(fil, "struct resource %s_res[] = {\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct resource %s_res[] = {\n", + ptr->name); struct resource *r = ptr->res; while (r) { fprintf(fil, "\t\t{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_"); @@ -441,7 +448,7 @@ static void pass1(FILE *fil, struct device *ptr) fprintf(fil, "\t };\n"); } if (!ptr->used && ptr->type == device && (ptr->children || ptr->multidev)) { - fprintf(fil, "struct bus %s_links[] = {\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct bus %s_links[] = {\n", ptr->name); if (ptr->multidev) { struct device *d = ptr; while (d) { @@ -473,8 +480,9 @@ static void pass1(FILE *fil, struct device *ptr) } if ((ptr->type == chip) && (ptr->chiph_exists)) { if (ptr->reg) { - fprintf(fil, "struct %s_config %s_info_%d\t= {\n", - ptr->name_underscore, ptr->name_underscore, ptr->id); + fprintf(fil, "ROMSTAGE_CONST struct %s_config ROMSTAGE_CONST %s_info_%d = {\n", + ptr->name_underscore, ptr->name_underscore, + ptr->id); struct reg *r = ptr->reg; while (r) { fprintf(fil, "\t.%s = %s,\n", r->key, r->value); @@ -482,7 +490,7 @@ static void pass1(FILE *fil, struct device *ptr) } fprintf(fil, "};\n\n"); } else { - fprintf(fil, "struct %s_config %s_info_%d;\n", + fprintf(fil, "ROMSTAGE_CONST struct %s_config ROMSTAGE_CONST %s_info_%d = { };\n", ptr->name_underscore, ptr->name_underscore, ptr->id); } } @@ -617,9 +625,9 @@ int main(int argc, char** argv) { fprintf(autogen, "\n/* pass 0 */\n"); walk_device_tree(autogen, &root, pass0, NULL); fprintf(autogen, "\n/* pass 1 */\n" - "struct device *last_dev = &%s;\n", lastdev->name); + "ROMSTAGE_CONST struct device * ROMSTAGE_CONST last_dev = &%s;\n", lastdev->name); #ifdef MAINBOARDS_HAVE_CHIP_H - fprintf(autogen, "struct mainboard_config mainboard_info_0;\n"); + fprintf(autogen, "static ROMSTAGE_CONST struct mainboard_config ROMSTAGE_CONST mainboard_info_0;\n"); #endif walk_device_tree(autogen, &root, pass1, NULL);

1 0

Patch merged into coreboot/master: 24a3100 Fix mainboard level enable_dev()
by gerrit＠coreboot.org 03 Aug '12

03 Aug '12

the following patch was just integrated into master: commit 24a31006d5089550f08076b78e51d92d687ae77a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 27 19:22:26 2012 +0300 Fix mainboard level enable_dev() Commit 188e3c2ff06a82f61d7d71e610b32b1a250c0a45 dropped mainboard out of the static device tree. This left dev_root->chip_ops unset, and mainboard_ops.enable_dev() was no longer called. Change-Id: I6d447c8049a66041b8bb36ec9aac3e7e0d20a99b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Jul 27 22:04:59 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Aug 3 00:34:49 2012, giving +2 See http://review.coreboot.org/1374 for details. -gerrit

1 0

Patch set updated for coreboot: 090d4d8 Add a capability for mainboard-specific posting.
by Alexandru Gagniuc 03 Aug '12

03 Aug '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1397 -gerrit commit 090d4d8421bb113ce98aca598f587fd558b17c80 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Aug 2 09:34:05 2012 -0700 Add a capability for mainboard-specific posting. Some mainboards have really nice capabilities for posting, beyond simple POST cards. Further, some can not use a POST card. This change defines a weak symbol (mainboard_post) that can be overridden by a real mainboard_post function. If, for example, you'd like to do something fancy before the payload starts, you can add this to mainboard.c: void mainboard_post(u8 value) { switch(value){ case 0xfe: some_fancy_lights(); break; } } Maybe the post function should be an entry in the device. We're beginning to over-use weak symbols. BUG=None TEST=Build and boot a google chromebook. Observe that it still works. Use it to drive some pretty lights. Change-Id: I3512d2ec34a66c747287191851c3f68b6a7cc1b2 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/console/post.c | 12 ++++++++++++ src/include/console/console.h | 2 ++ 2 files changed, 14 insertions(+), 0 deletions(-) diff --git a/src/console/post.c b/src/console/post.c index 08336a2..9cdad99 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -24,6 +24,15 @@ /* Write POST information */ +/* someday romcc will be gone. */ +#ifndef __ROMCC__ +/* Some mainboards have very nice features beyond just a simple + * display. They can override this function. + */ +void __attribute__((weak)) mainboard_post(uint8_t value) +{ +} +#endif void post_code(uint8_t value) { #if !CONFIG_NO_POST @@ -34,4 +43,7 @@ void post_code(uint8_t value) #endif outb(value, CONFIG_POST_PORT); #endif +#ifndef __ROMCC__ + mainboard_post(value); +#endif } diff --git a/src/include/console/console.h b/src/include/console/console.h index 56e202d..00be96f 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -69,6 +69,8 @@ extern int console_loglevel; #ifndef __ROMCC__ void console_init(void); void post_code(u8 value); +/* this function is weak and can be overridden by a mainboard function. */ +void mainboard_post(u8 value); void __attribute__ ((noreturn)) die(const char *msg); int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));

1 0

Patch merged into coreboot/master: 31b06e2 RTC: Add a routine to check if the CMOS date is valid
by gerrit＠coreboot.org 02 Aug '12

02 Aug '12

the following patch was just integrated into master: commit 31b06e2259ccfd84e8fe1f5f0bc1b2bcb58c6a28 Author: zbao <fishbaozi(a)gmail.com> Date: Thu Aug 2 19:02:26 2012 +0800 RTC: Add a routine to check if the CMOS date is valid If the CMOS is cleared or someone writes some random date/time on purpose, the CMOS date register has a invalid date. This will hurts some OS, like Windows 7, which hangs at MS logo forever. When we detect that, we need to write a reasonable date in CMOS. Alexandru Gagniuc: Hmm, it would be interesting to use the date the coreboot image was built and set that as the default date. At least until time travel is invented. Change-Id: Ic1c7a2d60e711265686441c77bdf7891a7efb42e Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Thu Aug 2 12:37:23 2012, giving +2 Build-Tested: build bot (Jenkins) at Thu Aug 2 12:27:22 2012, giving +1 See http://review.coreboot.org/1389 for details. -gerrit

1 0

Patch set updated for coreboot: 2e42103 Add a capability for mainboard-specific posting.
by Ronald G. Minnich 02 Aug '12

02 Aug '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1397 -gerrit commit 2e4210338aa7a2a8d3725432458e24dae071280d Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Aug 2 09:34:05 2012 -0700 Add a capability for mainboard-specific posting. Some mainboards have really nice capabilities for posting, beyond simple POST cards. Further, some can not use a POST card. This change defines a weak symbol (mainboard_post) that can be overridden by a real mainboard_post function. If, for example, you'd like to do something fancy before the payload starts, you can add this to mainboard.c: void mainboard_post(u8 value) { switch(value){ case 0xfe: some_fancy_lights(); break; } } Maybe the post function should be an entry in the device. We're beginning to over-use weak symbols. BUG=None TEST=Build and boot a google chromebook. Observe that it still works. Use it to drive some pretty lights. Change-Id: I3512d2ec34a66c747287191851c3f68b6a7cc1b2 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/console/post.c | 12 ++++++++++++ src/include/console/console.h | 2 ++ 2 files changed, 14 insertions(+), 0 deletions(-) diff --git a/src/console/post.c b/src/console/post.c index 08336a2..9cdad99 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -24,6 +24,15 @@ /* Write POST information */ +/* someday romcc will be gone. */ +#ifndef __ROMCC__ +/* Some mainboards have very nice features beyond just a simple + * display. They can override this function. + */ +void __attribute__((weak)) mainboard_post(uint8_t value) +{ +} +#endif void post_code(uint8_t value) { #if !CONFIG_NO_POST @@ -34,4 +43,7 @@ void post_code(uint8_t value) #endif outb(value, CONFIG_POST_PORT); #endif +#ifndef __ROMCC__ + mainboard_post(value); +#endif } diff --git a/src/include/console/console.h b/src/include/console/console.h index 56e202d..00be96f 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -69,6 +69,8 @@ extern int console_loglevel; #ifndef __ROMCC__ void console_init(void); void post_code(u8 value); +/* this function is weak and can be overridden by a mainboard function. */ +void mainboard_post(u8 value); void __attribute__ ((noreturn)) die(const char *msg); int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));

1 0

New patch to review for coreboot: 8f45a84 Add a capability for mainboard-specific posting.
by Ronald G. Minnich 02 Aug '12

02 Aug '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1397 -gerrit commit 8f45a843b44583fdeade2a78e657efe8424b144b Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Aug 2 09:34:05 2012 -0700 Add a capability for mainboard-specific posting. Some mainboards have really nice capabilities for posting, beyond simple POST cards. Further, some can not use a POST card. This change defines a weak symbol (mainboard_post) that can be overridden by a real mainboard_post function. If, for example, you'd like to do something fancy before the payload starts, you can add this to mainboard.c: void mainboard_post(u8 value) { switch(value){ case 0xfe: some_fancy_lights(); break; } } Maybe the post function should be an entry in the device. We're beginning to over-use weak symbols. BUG=None TEST=Build and boot a google chromebook. Observe that it still works. Use it to drive some pretty lights. Change-Id: I3512d2ec34a66c747287191851c3f68b6a7cc1b2 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/console/post.c | 8 ++++++++ src/include/console/console.h | 2 ++ 2 files changed, 10 insertions(+), 0 deletions(-) diff --git a/src/console/post.c b/src/console/post.c index 08336a2..0f95427 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -24,6 +24,13 @@ /* Write POST information */ +/* Some mainboards have very nice features beyond just a simple + * display. They can override this function. + */ +void __attribute__((weak)) mainboard_post(uint8_t value) +{ +} + void post_code(uint8_t value) { #if !CONFIG_NO_POST @@ -33,5 +40,6 @@ void post_code(uint8_t value) print_emerg("\n"); #endif outb(value, CONFIG_POST_PORT); + mainboard_post(value); #endif } diff --git a/src/include/console/console.h b/src/include/console/console.h index 56e202d..00be96f 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -69,6 +69,8 @@ extern int console_loglevel; #ifndef __ROMCC__ void console_init(void); void post_code(u8 value); +/* this function is weak and can be overridden by a mainboard function. */ +void mainboard_post(u8 value); void __attribute__ ((noreturn)) die(const char *msg); int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));

1 0

Patch merged into coreboot/master: 6c9e7d7 Limit the device field to 5 bits.
by gerrit＠coreboot.org 02 Aug '12

02 Aug '12

the following patch was just integrated into master: commit 6c9e7d7c6d8eb28b39c9bef1211031a88fd5773e Author: zbao <fishbaozi(a)gmail.com> Date: Mon Jul 23 19:49:40 2012 +0800 Limit the device field to 5 bits. The field device in PCI_ADDRESS only takes 5 bits. So if the device number is more than 32, it will truncated to 5 bits. Before this patch, other pci devices will be incorrectly probed as processor node. Change-Id: I64dcd4f4fda7b7080a9905dce580feb829584b94 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Jul 31 13:08:25 2012, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Thu Aug 2 13:03:08 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 31 17:45:57 2012, giving +2 See http://review.coreboot.org/1264 for details. -gerrit

1 0

← Newer
1
...
25
26
27
28
29
30
31
32
33
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot August 2012