coreboot August 2012

coreboot@coreboot.org

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321 discussions

Patch set updated for coreboot: 5710acf Replicate TOP_MEM and TOP_MEM2 from BSP to AP CPU
by Kyösti Mälkki 03 Aug '12

03 Aug '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1388 -gerrit commit 5710acf9a3d8a8f92ec8e603c6c434ec54049d82 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Aug 1 14:32:13 2012 +0300 Replicate TOP_MEM and TOP_MEM2 from BSP to AP CPU The search loop for UMA resource was only used to check for the highest RAM address below 4GB. The cached values from BSP CPU can now be used for the replication. Change-Id: I5244ffa6f8a93f5ff5aaf8a71bd006b0f9cd518a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/mtrr/amd_mtrr.c | 49 ++++++++++++++++++------------------------ 1 files changed, 21 insertions(+), 28 deletions(-) diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 9349ad4..bff6702 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -102,20 +102,6 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc } -static void uma_fb_resource(void *gp, struct device *dev, struct resource *res) -{ - struct mem_state *state = gp; - unsigned long topk; - - topk = resk(res->base + res->size); - if (state->tom2k < topk) { - state->tom2k = topk; - } - if ((topk < 4*1024*1024) && (state->tomk < topk)) { - state->tomk = topk; - } -} - /* These will likely move to some device node or cbmem. */ static uint64_t amd_topmem = 0; static uint64_t amd_topmem2 = 0; @@ -154,6 +140,25 @@ void setup_bsp_ramtop(void) amd_topmem2 = (uint64_t) msr2.hi<<32 | msr2.lo; } +static void setup_ap_ramtop(void) +{ + msr_t msr; + uint64_t v; + + v = bsp_topmem(); + if (!v) + return; + + msr.hi = v >> 32; + msr.lo = (uint32_t) v; + wrmsr(TOP_MEM, msr); + + v = bsp_topmem2(); + msr.hi = v >> 32; + msr.lo = (uint32_t) v; + wrmsr(TOP_MEM2, msr); +} + void amd_setup_mtrrs(void) { unsigned long address_bits; @@ -185,9 +190,6 @@ void amd_setup_mtrrs(void) state.tomk = state.tom2k = 0; search_global_resources( - IORESOURCE_MEM | IORESOURCE_UMA_FB, IORESOURCE_MEM | IORESOURCE_UMA_FB, - uma_fb_resource, &state); - search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, set_fixed_mtrr_resource, &state); @@ -195,20 +197,11 @@ void amd_setup_mtrrs(void) disable_cache(); - /* Round state.tomk up to the next greater size that will fit in TOP_MEM */ - state.tomk = (state.tomk + TOP_MEM_MASK_KB) & ~TOP_MEM_MASK_KB; - msr.hi = state.tomk >> 22; - msr.lo = state.tomk << 10; - wrmsr(TOP_MEM, msr); + setup_ap_ramtop(); /* if DRAM above 4GB: set SYSCFG_MSR_TOM2En and SYSCFG_MSR_TOM2WB */ sys_cfg.lo &= ~(SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB); - if(state.tom2k > (4*1024*1024)) { - /* Round state.tomk up to the next greater size that will fit in TOP_MEM2 */ - state.tom2k = (state.tom2k + TOP_MEM_MASK_KB) & ~TOP_MEM_MASK_KB; - msr.hi = state.tom2k >> 22; - msr.lo = state.tom2k << 10; - wrmsr(TOP_MEM2, msr); + if (bsp_topmem2() > (uint64_t)1<<32) { sys_cfg.lo |= SYSCFG_MSR_TOM2En; if(has_tom2wb) sys_cfg.lo |= SYSCFG_MSR_TOM2WB;

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Patch set updated for coreboot: 67928b4 AMD f15: Change multiply ONE_MB to bit shifting (Propagation)
by Kyösti Mälkki 03 Aug '12

03 Aug '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1405 -gerrit commit 67928b476da1150db806a63dde367586f89606be Author: zbao <fishbaozi(a)gmail.com> Date: Fri Aug 3 16:06:08 2012 +0800 AMD f15: Change multiply ONE_MB to bit shifting (Propagation) Apply the change http://review.coreboot.org/1263 to family15 northbridge. Change-Id: If1109f20ffd833a716e092c5e4f6f16ee6b968c7 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> [km: rebased] Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/agesa/family15/northbridge.c | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 6ce73cb..11edbf0 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -627,7 +627,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#define ONE_MB 0x100000 +#define ONE_MB_SHIFT 20 static void setup_uma_memory(void) { @@ -643,13 +643,13 @@ static void setup_uma_memory(void) * >=1G 256M * <1G 64M */ - sys_mem = topmem + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size - if ((bsp_topmem2()>>32) || (sys_mem >= 2048 * ONE_MB)) { - uma_memory_size = 512 * ONE_MB; - } else if (sys_mem >= 1024 * ONE_MB) { - uma_memory_size = 256 * ONE_MB; + sys_mem = topmem + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size + if ((bsp_topmem2()>>32) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { + uma_memory_size = 512 << ONE_MB_SHIFT; + } else if (sys_mem >= 1024 << ONE_MB_SHIFT) { + uma_memory_size = 256 << ONE_MB_SHIFT; } else { - uma_memory_size = 64 * ONE_MB; + uma_memory_size = 64 << ONE_MB_SHIFT; } uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */

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Patch set updated for coreboot: b39ea47 Technexion TIM5690: drop add_mainboard_resources()
by Kyösti Mälkki 03 Aug '12

03 Aug '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1396 -gerrit commit b39ea475fbdeb64bb94f02d83859264fb3ec193e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Aug 2 09:44:14 2012 +0300 Technexion TIM5690: drop add_mainboard_resources() Move the POST display to take place just before jumping the payload, a bit later than before. Change-Id: Ie1d1ff24dc6c1640e25681be7dc5740943c7f112 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/technexion/tim5690/Kconfig | 1 - src/mainboard/technexion/tim5690/mainboard.c | 9 ++++++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/src/mainboard/technexion/tim5690/Kconfig b/src/mainboard/technexion/tim5690/Kconfig index 404ddfe..172b478 100644 --- a/src/mainboard/technexion/tim5690/Kconfig +++ b/src/mainboard/technexion/tim5690/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SB_HT_CHAIN_UNITID_OFFSET_ONLY select HAVE_ACPI_TABLES select GFXUMA - select HAVE_MAINBOARD_RESOURCES select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index 41147cd..b87058c 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -242,10 +242,13 @@ static void tim5690_enable(device_t dev) set_thermal_config(); } -int add_mainboard_resources(struct lb_memory *mem) +void mainboard_post(u8 value) { - technexion_post_code(LED_MESSAGE_FINISH); - return 0; + switch (value) { + case POST_ENTER_ELF_BOOT: + technexion_post_code(LED_MESSAGE_FINISH); + break; + } } struct chip_operations mainboard_ops = {

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New patch to review for coreboot: 7d06a07 AMD Thatcher: Add BIOS callback hook for getting VBIOS Image
by Zheng Bao 03 Aug '12

03 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1407 -gerrit commit 7d06a0764ae69af74c46aeb18e582f8799865d20 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Aug 3 17:12:45 2012 +0800 AMD Thatcher: Add BIOS callback hook for getting VBIOS Image Apply the change http://review.coreboot.org/1351 to thatcher. Change-Id: I33e7ad0cad2ae06f5934c60939d60a18444aa24e Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/thatcher/BiosCallOuts.c | 12 ++++++++++++ src/mainboard/amd/thatcher/BiosCallOuts.h | 2 ++ 2 files changed, 14 insertions(+), 0 deletions(-) diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index 34936e0..8660e05 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -25,6 +25,7 @@ #include "OptionsIds.h" #include "heapManager.h" #include "FchPlatform.h" +#include "cbfs.h" STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = { @@ -71,6 +72,9 @@ STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, + BiosHookGfxGetVbiosImage + } }; AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) @@ -735,3 +739,11 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) return AGESA_SUCCESS; } + +AGESA_STATUS BiosHookGfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt) +{ + GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt; + pVbiosImageInfo->ImagePtr = cbfs_find_file("pci"CONFIG_VGA_BIOS_ID".rom", CBFS_TYPE_OPTIONROM); + /* printk(BIOS_DEBUG, "IMGptr=%x\n", pVbiosImageInfo->ImagePtr); */ + return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS; +} diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.h b/src/mainboard/amd/thatcher/BiosCallOuts.h index 1993c64..b7b9eaf 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.h +++ b/src/mainboard/amd/thatcher/BiosCallOuts.h @@ -71,6 +71,8 @@ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *Conf AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* FCH OEM Config*/ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); +/* Get Vbios Image */ +AGESA_STATUS BiosHookGfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt); #define SB_GPIO_REG02 2 #define SB_GPIO_REG09 9 #define SB_GPIO_REG10 10

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New patch to review for coreboot: 29ac975 AMD SB: Call the rtc update if needed (Propagation)
by Zheng Bao 03 Aug '12

03 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1406 -gerrit commit 29ac9757e06350dbaad8f780b8ce3a51ed419a9a Author: zbao <fishbaozi(a)gmail.com> Date: Fri Aug 3 16:58:53 2012 +0800 AMD SB: Call the rtc update if needed (Propagation) Apply the change http://review.coreboot.org/1390 to all the AMD southbridge. Change-Id: I8e94014f8883a0408b68355d9aa33aea4373881f Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/southbridge/amd/cimx/sb700/late.c | 12 +++++++++++- src/southbridge/amd/cimx/sb800/late.c | 12 +++++++++++- src/southbridge/amd/cimx/sb900/late.c | 3 +++ src/southbridge/amd/sb600/lpc.c | 1 + src/southbridge/amd/sb700/lpc.c | 2 ++ src/southbridge/amd/sb800/lpc.c | 2 ++ 6 files changed, 30 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c index 4e51e0a..be2b8cd 100644 --- a/src/southbridge/amd/cimx/sb700/late.c +++ b/src/southbridge/amd/cimx/sb700/late.c @@ -23,6 +23,7 @@ #include <device/pci_ids.h> #include <arch/ioapic.h> #include <device/smbus.h> /* smbus_bus_operations */ +#include <pc80/mc146818rtc.h> #include <console/console.h> /* printk */ #include "lpc.h" /* lpc_read_resources */ #include "Platform.h" /* Platfrom Specific Definitions */ @@ -72,11 +73,20 @@ static void lpc_enable_resources(device_t dev) printk(BIOS_SPEW, "SB700 - Late.c - %s - End.\n", __func__); } +static void lpc_init(device_t dev) +{ + printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - Start.\n"); + + rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); + + printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - End.\n"); +} + static struct device_operations lpc_ops = { .read_resources = lpc_read_resources, .set_resources = lpc_set_resources, .enable_resources = lpc_enable_resources, - .init = 0, + .init = lpc_init, .scan_bus = scan_static_bus, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 0ce82b3..7286a6d 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -23,6 +23,7 @@ #include <device/pci_ids.h> #include <arch/ioapic.h> #include <device/smbus.h> /* smbus_bus_operations */ +#include <pc80/mc146818rtc.h> #include <console/console.h> /* printk */ #include <arch/acpi.h> #include "lpc.h" /* lpc_read_resources */ @@ -120,11 +121,20 @@ static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; +static void lpc_init(device_t dev) +{ + printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n"); + + rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); + + printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n"); +} + static struct device_operations lpc_ops = { .read_resources = lpc_read_resources, .set_resources = lpc_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, + .init = lpc_init, .scan_bus = scan_static_bus, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index 71c65e3..85485ed 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -22,6 +22,7 @@ #include <device/pci.h> /* device_operations */ #include <device/pci_ids.h> #include <device/smbus.h> /* smbus_bus_operations */ +#include <pc80/mc146818rtc.h> #include <console/console.h> /* printk */ #include "lpc.h" /* lpc_read_resources */ #include "SbPlatform.h" /* Platfrom Specific Definitions */ @@ -98,6 +99,8 @@ static void lpc_init(device_t dev) printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - Start.\n"); /* SB Configure HPET base and enable bit */ //- hpetInit(sb_config, &(sb_config->BuildParameters)); + rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); + printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - End.\n"); } diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c index 6f16ea8..22945a7 100644 --- a/src/southbridge/amd/sb600/lpc.c +++ b/src/southbridge/amd/sb600/lpc.c @@ -60,6 +60,7 @@ static void lpc_init(device_t dev) byte &= ~(1 << 1); pci_write_config8(dev, 0x78, byte); + rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); } static void sb600_lpc_read_resources(device_t dev) diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index c968927..be940e3 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -81,6 +81,8 @@ static void lpc_init(device_t dev) printk(BIOS_DEBUG, "SLP_TYP type was %x\n", acpi_slp_type); } #endif + + rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); } void set_cbmem_toc(struct cbmem_entry *toc) diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 4e2031f..3cb0789 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -67,6 +67,8 @@ static void lpc_init(device_t dev) byte = pci_read_config8(dev, 0xBB); byte |= 1 << 0 | 1 << 3; pci_write_config8(dev, 0xBB, byte); + + rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); } static void sb800_lpc_read_resources(device_t dev)

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New patch to review for coreboot: a1b1a4d AMD f15: Change multiply ONE_MB to bit shifting (Propagation)
by Zheng Bao 03 Aug '12

03 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1405 -gerrit commit a1b1a4df8b07141ee7e8cfc13095ba36c9f883ed Author: zbao <fishbaozi(a)gmail.com> Date: Fri Aug 3 16:06:08 2012 +0800 AMD f15: Change multiply ONE_MB to bit shifting (Propagation) Apply the change http://review.coreboot.org/1263 to family15 northbridge. Change-Id: If1109f20ffd833a716e092c5e4f6f16ee6b968c7 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/northbridge/amd/agesa/family15/northbridge.c | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index d7e9521..d9a153b 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -627,7 +627,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#define ONE_MB 0x100000 +#define ONE_MB_SHIFT 20 static void setup_uma_memory(void) { @@ -654,13 +654,13 @@ static void setup_uma_memory(void) * >=1G 256M * <1G 64M */ - sys_mem = msr.lo + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size - if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 * ONE_MB)) { - uma_memory_size = 512 * ONE_MB; - } else if (sys_mem >= 1024 * ONE_MB) { - uma_memory_size = 256 * ONE_MB; + sys_mem = msr.lo + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size + if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { + uma_memory_size = 512 << ONE_MB_SHIFT; + } else if (sys_mem >= 1024 << ONE_MB_SHIFT) { + uma_memory_size = 256 << ONE_MB_SHIFT; } else { - uma_memory_size = 64 * ONE_MB; + uma_memory_size = 64 << ONE_MB_SHIFT; } uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */

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New patch to review for coreboot: 1400723 AMD f15 nb: Remove the misleading 0x100 from the limitk (Propagation)
by Zheng Bao 03 Aug '12

03 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1404 -gerrit commit 14007235fe60e386584d75148ae9c65cabcae577 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Aug 3 15:56:21 2012 +0800 AMD f15 nb: Remove the misleading 0x100 from the limitk (Propagation) Apply the change http://review.coreboot.org/1265 to all the AMD northbridge. Change-Id: Idf3994c1e9ec76cd19db9f740d825cf24059884f Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/northbridge/amd/agesa/family15/northbridge.c | 4 ++-- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 8d64a30..d7e9521 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -619,7 +619,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) mem_hole.node_id = i; break; //only one hole } - limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9; + limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; limitk_pri = limit_k; } } @@ -779,7 +779,7 @@ static void domain_set_resources(device_t dev) if (!(d.mask & 1)) continue; basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9 ; + limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; sizek = limitk - basek; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 7f8650c..c63890d 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -628,7 +628,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) mem_hole.node_id = i; break; //only one hole } - limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9; + limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; limitk_pri = limit_k; } }

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New patch to review for coreboot: cbe5a5b AMD NB: Limit the device field to 5 bits. (Propagation)
by Zheng Bao 03 Aug '12

03 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1403 -gerrit commit cbe5a5b90010158d78913f83817390e332894eae Author: zbao <fishbaozi(a)gmail.com> Date: Fri Aug 3 15:44:42 2012 +0800 AMD NB: Limit the device field to 5 bits. (Propagation) Apply the change http://review.coreboot.org/1264 to all the AMD northbridge. Change-Id: Ied74d6f579d2c0350288e2619d7810f8d44fa574 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/northbridge/amd/agesa/family10/northbridge.c | 4 ++-- src/northbridge/amd/agesa/family12/northbridge.c | 6 +++++- src/northbridge/amd/agesa/family14/northbridge.c | 6 +++++- src/northbridge/amd/agesa/family15/northbridge.c | 4 ++-- src/northbridge/amd/amdfam10/northbridge.c | 4 ++-- 5 files changed, 16 insertions(+), 8 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 831aec0..8cc9475 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -361,8 +361,8 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi static device_t get_node_pci(u32 nodeid, u32 fn) { -#if NODE_NUMS == 64 - if (nodeid < 32) { +#if NODE_NUMS + CONFIG_CDB >= 32 + if ((CONFIG_CDB + nodeid) < 32) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); } else { return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index f3f03a4..af1d4f0 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -50,7 +50,11 @@ static unsigned fx_devs=0; device_t get_node_pci(u32 nodeid, u32 fn) { - return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); + if ((CONFIG_CDB + nodeid) < 32) { + return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); + } else { + return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); + } } diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index af6dfcc..a03939c 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -51,7 +51,11 @@ static unsigned fx_devs = 0; device_t get_node_pci(u32 nodeid, u32 fn) { - return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); + if ((CONFIG_CDB + nodeid) < 32) { + return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); + } else { + return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); + } } static void get_fx_devs(void) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index a080293..8d64a30 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -122,8 +122,8 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi static device_t get_node_pci(u32 nodeid, u32 fn) { -#if MAX_NODE_NUMS == 64 - if (nodeid < 32) { +#if MAX_NODE_NUMS + CONFIG_CDB >= 32 + if ((CONFIG_CDB + nodeid) < 32) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); } else { return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 15b29f6..aa15fdd 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -63,8 +63,8 @@ static unsigned fx_devs=0; device_t get_node_pci(u32 nodeid, u32 fn) { -#if NODE_NUMS == 64 - if(nodeid<32) { +#if NODE_NUMS + CONFIG_CDB >= 32 + if((CONFIG_CDB + nodeid) < 32) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); } else { return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));

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New patch to review for coreboot: 8452211 SuperIO LPC47N217: Remove warnings
by Zheng Bao 03 Aug '12

03 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1402 -gerrit commit 8452211aaea71a5b01b22708fa606e653f336d11 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Aug 3 15:09:09 2012 +0800 SuperIO LPC47N217: Remove warnings Change-Id: Id5756f1bb748ae7bec0bcdc21804f5338e850baa Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/superio/smsc/lpc47n217/early_serial.c | 4 ++-- src/superio/smsc/lpc47n217/superio.c | 7 ++++--- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/superio/smsc/lpc47n217/early_serial.c b/src/superio/smsc/lpc47n217/early_serial.c index ce79db8..d767e05 100644 --- a/src/superio/smsc/lpc47n217/early_serial.c +++ b/src/superio/smsc/lpc47n217/early_serial.c @@ -42,7 +42,7 @@ static void pnp_exit_conf_state(device_t dev) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Base I/O port for the logical device. */ -void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase) +static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase) { /* LPC47N217 requires base ports to be a multiple of 4. */ ASSERT(!(iobase & 0x3)); @@ -74,7 +74,7 @@ void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param enable 0 to disable, anythig else to enable. */ -void lpc47n217_pnp_set_enable(device_t dev, int enable) +static void lpc47n217_pnp_set_enable(device_t dev, int enable) { u8 power_register = 0, power_mask = 0, current_power, new_power; diff --git a/src/superio/smsc/lpc47n217/superio.c b/src/superio/smsc/lpc47n217/superio.c index 88832e1..01c96b1 100644 --- a/src/superio/smsc/lpc47n217/superio.c +++ b/src/superio/smsc/lpc47n217/superio.c @@ -133,7 +133,8 @@ static void lpc47n217_pnp_enable(device_t dev) */ static void lpc47n217_init(device_t dev) { - struct superio_smsc_lpc47n217_config* conf = dev->chip_info; + /* TODO: Reserved for future. */ + /* struct superio_smsc_lpc47n217_config* conf = dev->chip_info; */ if (!dev->enabled) return; @@ -142,7 +143,7 @@ static void lpc47n217_init(device_t dev) static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource) { if (!(resource->flags & IORESOURCE_ASSIGNED)) { - printk(BIOS_ERR, "ERROR: %s %02x not allocated\n", + printk(BIOS_ERR, "ERROR: %s %02lx not allocated\n", dev_path(dev), resource->index); return; } @@ -160,7 +161,7 @@ static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource) } else if (resource->flags & IORESOURCE_IRQ) { lpc47n217_pnp_set_irq(dev, resource->base); } else { - printk(BIOS_ERR, "ERROR: %s %02x unknown resource type\n", + printk(BIOS_ERR, "ERROR: %s %02lx unknown resource type\n", dev_path(dev), resource->index); return; }

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Patch set updated for coreboot: 09c93e1 Technexion TIM5690: drop add_mainboard_resources()
by Kyösti Mälkki 03 Aug '12

03 Aug '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1396 -gerrit commit 09c93e14176aa5c8a77638ef9102a06924fa5215 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Aug 2 09:44:14 2012 +0300 Technexion TIM5690: drop add_mainboard_resources() Move the POST display to take place just before jumping the payload, a bit later than before. Change-Id: Ie1d1ff24dc6c1640e25681be7dc5740943c7f112 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/technexion/tim5690/Kconfig | 1 - src/mainboard/technexion/tim5690/mainboard.c | 10 +++++++--- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/mainboard/technexion/tim5690/Kconfig b/src/mainboard/technexion/tim5690/Kconfig index 404ddfe..172b478 100644 --- a/src/mainboard/technexion/tim5690/Kconfig +++ b/src/mainboard/technexion/tim5690/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SB_HT_CHAIN_UNITID_OFFSET_ONLY select HAVE_ACPI_TABLES select GFXUMA - select HAVE_MAINBOARD_RESOURCES select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index 41147cd..c1aa389 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -242,10 +242,14 @@ static void tim5690_enable(device_t dev) set_thermal_config(); } -int add_mainboard_resources(struct lb_memory *mem) +void mainboard_post(u8 value) { - technexion_post_code(LED_MESSAGE_FINISH); - return 0; + switch (value) { + case POST_ENTER_ELF_BOOT: + technexion_post_code(LED_MESSAGE_FINISH); + break; + default: + } } struct chip_operations mainboard_ops = {

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coreboot August 2012