coreboot August 2012

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New patch to review for coreboot: 5c663a9 Perform additional programming requirements for SATA
by Stefan Reinauer 04 Aug '12

04 Aug '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1411 -gerrit commit 5c663a9caa0c310687919dbaa6299d150ef89742 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 17 16:42:51 2012 -0700 Perform additional programming requirements for SATA In accordance to PCH EDS 14.1.35.1 Change-Id: I2e6cec6d4f49f404e33a171a8fbd6e4880327896 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/southbridge/intel/bd82x6x/pch.h | 2 + src/southbridge/intel/bd82x6x/sata.c | 49 ++++++++++++++++++++++++++++++--- 2 files changed, 46 insertions(+), 5 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index beed63a..7e67e3b 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -196,6 +196,8 @@ int smbus_read_byte(unsigned device, unsigned address); #define PCB1 (1 << 1) #define PCB0 (1 << 0) +#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ +#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ #define SATA_SP 0xd0 /* Scratchpad */ /* SATA IOBP Registers */ diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 2e41158..fb29d73 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -27,6 +27,18 @@ typedef struct southbridge_intel_bd82x6x_config config_t; +static inline u32 sir_read(struct device *dev, int idx) +{ + pci_write_config32(dev, SATA_SIRI, idx); + return pci_read_config32(dev, SATA_SIRD); +} + +static inline void sir_write(struct device *dev, int idx, u32 value) +{ + pci_write_config32(dev, SATA_SIRI, idx); + pci_write_config32(dev, SATA_SIRD, value); +} + static void sata_init(struct device *dev) { u32 reg32; @@ -34,10 +46,10 @@ static void sata_init(struct device *dev) /* Get the chip configuration */ config_t *config = dev->chip_info; - printk(BIOS_DEBUG, "pch_sata: initializing...\n"); + printk(BIOS_DEBUG, "SATA: Initializing...\n"); if (config == NULL) { - printk(BIOS_ERR, "pch_sata: error: device not in devicetree.cb!\n"); + printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); return; } @@ -47,7 +59,7 @@ static void sata_init(struct device *dev) pci_write_config16(dev, PCI_COMMAND, 0x0007); if (config->ide_legacy_combined) { - printk(BIOS_DEBUG, "SATA controller in combined mode.\n"); + printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); /* No AHCI: clear AHCI base */ pci_write_config32(dev, 0x24, 0x00000000); @@ -85,7 +97,7 @@ static void sata_init(struct device *dev) } else if(config->sata_ahci) { u32 abar; - printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n"); + printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); /* Set Interrupt Line */ /* Interrupt Pin is set by D31IP.PIP */ @@ -137,7 +149,7 @@ static void sata_init(struct device *dev) reg32 &= ~0x00000005; write32(abar + 0xa0, reg32); } else { - printk(BIOS_DEBUG, "SATA controller in plain mode.\n"); + printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); /* No AHCI: clear AHCI base */ pci_write_config32(dev, 0x24, 0x00000000); @@ -191,6 +203,33 @@ static void sata_init(struct device *dev) if (config->sata_port1_gen3_tx) pch_iobp_update(SATA_IOBP_SP1G3IR, 0, config->sata_port1_gen3_tx); + + /* Additional Programming Requirements */ + sir_write(dev, 0x04, 0x00001600); + sir_write(dev, 0x28, 0xa0000033); + reg32 = sir_read(dev, 0x54); + reg32 &= 0xff000000; + reg32 |= 0x5555aa; + sir_write(dev, 0x54, reg32); + sir_write(dev, 0x64, 0xcccc8484); + reg32 = sir_read(dev, 0x68); + reg32 &= 0xffff0000; + reg32 |= 0xcccc; + sir_write(dev, 0x68, reg32); + reg32 = sir_read(dev, 0x78); + reg32 &= 0x0000ffff; + reg32 |= 0x88880000; + sir_write(dev, 0x78, reg32); + sir_write(dev, 0x84, 0x001c7000); + sir_write(dev, 0x88, 0x88338822); + sir_write(dev, 0xa0, 0x001c7000); + // a4 + sir_write(dev, 0xc4, 0x0c0c0c0c); + sir_write(dev, 0xc8, 0x0c0c0c0c); + sir_write(dev, 0xd4, 0x10000000); + + pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000); + pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100); } static void sata_enable(device_t dev)

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New patch to review for coreboot: 4974878 bd82x6x: Add beep commands
by Stefan Reinauer 04 Aug '12

04 Aug '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1410 -gerrit commit 4974878d81fa32f95dfdc5f62308a8f66926c4b1 Author: Dylan Reid <dgreid(a)chromium.org> Date: Fri Apr 27 11:37:33 2012 -0700 bd82x6x: Add beep commands Move beep commands to board-specific area as they need to be different for different codecs. Change-Id: I2a1ac938c49827cc816a95df10793a7e234942bf Signed-off-by: Dylan Reid <dgreid(a)chromium.org> --- src/mainboard/samsung/lumpy/hda_verb.h | 10 ++++++++++ src/mainboard/samsung/lumpy/mainboard.c | 4 ++++ src/mainboard/samsung/stumpy/hda_verb.h | 9 +++++++++ src/mainboard/samsung/stumpy/mainboard.c | 4 ++++ src/southbridge/intel/bd82x6x/azalia.c | 12 ++++++++++++ 5 files changed, 39 insertions(+), 0 deletions(-) diff --git a/src/mainboard/samsung/lumpy/hda_verb.h b/src/mainboard/samsung/lumpy/hda_verb.h index 732f0aa..3871aa1 100644 --- a/src/mainboard/samsung/lumpy/hda_verb.h +++ b/src/mainboard/samsung/lumpy/hda_verb.h @@ -69,3 +69,13 @@ static const u32 mainboard_cim_verb_data[] = { 0x00a71e45, 0x00a71f43 }; + +static const u32 mainboard_pc_beep_verbs[] = { + 0x00170500, /* power up codec */ + 0x00270500, /* power up DAC */ + 0x00670500, /* power up speaker */ + 0x00670740, /* enable speaker output */ + 0x0023B04B, /* set DAC gain */ +}; +static const u32 mainboard_pc_beep_verbs_size = + sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]); diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index e83516a..62d87b6 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -253,11 +253,15 @@ static void int15_install(void) extern const u32 * cim_verb_data; extern u32 cim_verb_data_size; +extern const u32 * pc_beep_verbs; +extern u32 pc_beep_verbs_size; static void verb_setup(void) { cim_verb_data = mainboard_cim_verb_data; cim_verb_data_size = sizeof(mainboard_cim_verb_data); + pc_beep_verbs = mainboard_pc_beep_verbs; + pc_beep_verbs_size = mainboard_pc_beep_verbs_size; } static void mainboard_init(device_t dev) diff --git a/src/mainboard/samsung/stumpy/hda_verb.h b/src/mainboard/samsung/stumpy/hda_verb.h index 9a4a740..c9a49c5 100644 --- a/src/mainboard/samsung/stumpy/hda_verb.h +++ b/src/mainboard/samsung/stumpy/hda_verb.h @@ -97,3 +97,12 @@ static const u32 mainboard_cim_verb_data[] = { 0x30771f18 }; +static const u32 mainboard_pc_beep_verbs[] = { + 0x00170500, /* power up codec */ + 0x00270500, /* power up DAC */ + 0x00670500, /* power up speaker */ + 0x00670740, /* enable speaker output */ + 0x0023B04B, /* set DAC gain */ +}; +static const u32 mainboard_pc_beep_verbs_size = + sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]); diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c index 246b261..c70673b 100644 --- a/src/mainboard/samsung/stumpy/mainboard.c +++ b/src/mainboard/samsung/stumpy/mainboard.c @@ -223,11 +223,15 @@ static void int15_install(void) extern const u32 * cim_verb_data; extern u32 cim_verb_data_size; +extern const u32 * pc_beep_verbs; +extern u32 pc_beep_verbs_size; static void verb_setup(void) { cim_verb_data = mainboard_cim_verb_data; cim_verb_data_size = sizeof(mainboard_cim_verb_data); + pc_beep_verbs = mainboard_pc_beep_verbs; + pc_beep_verbs_size = mainboard_pc_beep_verbs_size; } // mainboard_enable is executed as first thing after diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index e40bbe3..a257daf 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -92,6 +92,8 @@ no_codec: const u32 * cim_verb_data = NULL; u32 cim_verb_data_size = 0; +const u32 * pc_beep_verbs = NULL; +u32 pc_beep_verbs_size = 0; static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb) { @@ -218,6 +220,16 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask) if (codec_mask & (1 << i)) codec_init(dev, base, i); } + + for (i = 0; i < pc_beep_verbs_size; i++) { + if (wait_for_ready(base) == -1) + return; + + write32(base + 0x60, pc_beep_verbs[i]); + + if (wait_for_valid(base) == -1) + return; + } } static void azalia_init(struct device *dev)

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Patch set updated for coreboot: 3bf9ed1 Make the device tree available in the rom stage
by Stefan Reinauer 03 Aug '12

03 Aug '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1398 -gerrit commit 3bf9ed165efd91cb8d51e42e71528c140b4caf15 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 31 16:47:25 2012 -0700 Make the device tree available in the rom stage We thought about two ways to do this change. The way we decided to try was to 1. drop all ops from devices in romstage 2. constify all devices in romstage (make them read-only) so we can compile static.c into romstage 3. the device tree "devices" can be used to read configuration from the device tree (and nothing else, really) 4. the device tree devices are accessed through struct device * in romstage only. device_t stays the typedef to int in romstage 5. Use the same static.c file in ramstage and romstage We declare structs as follows: ROMSTAGE_CONST struct bus dev_root_links[]; ROMSTAGE_CONST is const in romstage and empty in ramstage; This forces all of the device tree into the text area. So a struct looks like this: static ROMSTAGE_CONST struct device _dev21 = { #ifndef __PRE_RAM__ .ops = 0, #endif .bus = &_dev7_links[0], .path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}}, .enabled = 0, .on_mainboard = 1, .subsystem_vendor = 0x1ae0, .subsystem_device = 0xc000, .link_list = NULL, .sibling = &_dev22, #ifndef __PRE_RAM__ .chip_ops = &southbridge_intel_bd82x6x_ops, #endif .chip_info = &southbridge_intel_bd82x6x_info_10, .next=&_dev22 }; Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727 Signed-off-by: Ronald G. Minnich <rminnich(a)chromium.org> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- Makefile.inc | 5 ++ src/arch/x86/include/stddef.h | 6 ++ src/cpu/amd/agesa/s3_resume.c | 2 + src/devices/Makefile.inc | 2 + src/devices/device_romstage.c | 80 ++++++++++++++++++++++++++ src/ec/lenovo/pmh7/pmh7.c | 4 + src/include/device/device.h | 35 +++++++---- src/include/device/pci.h | 3 + src/include/device/resource.h | 3 +- util/lint/lint-stable-002-build-dir-handling | 17 ++++-- util/sconfig/main.c | 32 +++++++---- 11 files changed, 158 insertions(+), 31 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index ca1e066..083d423 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -228,6 +228,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/static.c: $(src)/mainboard/$(MAINBOARDDIR)/devi $(objutil)/sconfig/sconfig $(MAINBOARDDIR) $(obj)/mainboard/$(MAINBOARDDIR) ramstage-y+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c +romstage-y+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c $(objutil)/%.o: $(objutil)/%.c @printf " HOSTCC $(subst $(objutil)/,,$(@))\n" @@ -237,6 +238,10 @@ $(obj)/%.ramstage.o $(abspath $(obj))/%.ramstage.o: $(obj)/%.c $(obj)/config.h $ @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD $(CFLAGS) -c -o $@ $< +$(obj)/%.romstage.o $(abspath $(obj))/%.romstage.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -MMD -D__PRE_RAM__ $(CFLAGS) -c -o $@ $< + ####################################################################### # Clean up rules clean-abuild: diff --git a/src/arch/x86/include/stddef.h b/src/arch/x86/include/stddef.h index a6c3fc6..fc89de5 100644 --- a/src/arch/x86/include/stddef.h +++ b/src/arch/x86/include/stddef.h @@ -15,4 +15,10 @@ typedef unsigned int wint_t; #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) +#ifdef __PRE_RAM__ +#define ROMSTAGE_CONST const +#else +#define ROMSTAGE_CONST +#endif + #endif /* I386_STDDEF_H */ diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 6bb053d..0348a9f 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -29,7 +29,9 @@ #endif #include <device/device.h> #include <device/pci.h> +#ifndef __PRE_RAM__ #include <device/pci_ops.h> +#endif #include <arch/io.h> #include <arch/acpi.h> #include <string.h> diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc index 9ffc0bb..9a2f71e 100644 --- a/src/devices/Makefile.inc +++ b/src/devices/Makefile.inc @@ -11,6 +11,8 @@ ramstage-y += pnp_device.c ramstage-y += pci_ops.c ramstage-y += smbus_ops.c +romstage-y+= device_romstage.c + subdirs-y += oprom ifeq ($(CONFIG_PCI_ROM_RUN),y) diff --git a/src/devices/device_romstage.c b/src/devices/device_romstage.c new file mode 100644 index 0000000..475f94a --- /dev/null +++ b/src/devices/device_romstage.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003-2004 Linux Networx + * (Written by Eric Biederman <ebiederman(a)lnxi.com> for Linux Networx) + * Copyright (C) 2003 Greg Watson <jarrah(a)users.sourceforge.net> + * Copyright (C) 2004 Li-Ta Lo <ollie(a)lanl.gov> + * Copyright (C) 2005-2006 Tyan + * (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/path.h> +#include <device/pci.h> +#include <device/resource.h> + +/** Linked list of ALL devices */ +ROMSTAGE_CONST struct device * ROMSTAGE_CONST all_devices = &dev_root; + +/** + * Given a PCI bus and a devfn number, find the device structure. + * + * @param bus The bus number. + * @param devfn A device/function number. + * @return Pointer to the device structure (if found), 0 otherwise. + */ +ROMSTAGE_CONST struct device *dev_find_slot(unsigned int bus, + unsigned int devfn) +{ + ROMSTAGE_CONST struct device *dev, *result; + + result = 0; + for (dev = all_devices; dev; dev = dev->next) { + if ((dev->path.type == DEVICE_PATH_PCI) && + (dev->bus->secondary == bus) && + (dev->path.pci.devfn == devfn)) { + result = dev; + break; + } + } + return result; +} + +/** + * Given an SMBus bus and a device number, find the device structure. + * + * @param bus The bus number. + * @param addr A device number. + * @return Pointer to the device structure (if found), 0 otherwise. + */ +ROMSTAGE_CONST struct device *dev_find_slot_on_smbus(unsigned int bus, + unsigned int addr) +{ + ROMSTAGE_CONST struct device *dev, *result; + + result = 0; + for (dev = all_devices; dev; dev = dev->next) { + if ((dev->path.type == DEVICE_PATH_I2C) && + (dev->bus->secondary == bus) && + (dev->path.i2c.device == addr)) { + result = dev; + break; + } + } + return result; +} + diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index 844e233..28f3814 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -19,8 +19,12 @@ #include <arch/io.h> #include <console/console.h> +#ifndef __PRE_RAM__ +#ifndef __SMM__ #include <device/device.h> #include <device/pnp.h> +#endif +#endif #include <stdlib.h> #include "pmh7.h" #include "chip.h" diff --git a/src/include/device/device.h b/src/include/device/device.h index 0b15ac5..b44a551 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -2,11 +2,12 @@ #define DEVICE_H #include <stdint.h> +#include <stddef.h> #include <device/resource.h> #include <device/path.h> - struct device; +#ifndef __PRE_RAM__ typedef struct device * device_t; struct pci_operations; struct pci_bus_operations; @@ -42,12 +43,14 @@ struct device_operations { const struct smbus_bus_operations *ops_smbus_bus; const struct pci_bus_operations *ops_pci_bus; }; +#endif struct bus { - device_t dev; /* This bridge device */ - device_t children; /* devices behind this bridge */ - struct bus *next; /* The next bridge on this device */ + + ROMSTAGE_CONST struct device * dev; /* This bridge device */ + ROMSTAGE_CONST struct device * children; /* devices behind this bridge */ + ROMSTAGE_CONST struct bus *next; /* The next bridge on this device */ unsigned bridge_ctrl; /* Bridge control register */ unsigned char link_num; /* The index of this link */ uint16_t secondary; /* secondary bus number */ @@ -70,10 +73,12 @@ struct pci_irq_info { }; struct device { - struct bus * bus; /* bus this device is on, for bridge + ROMSTAGE_CONST struct bus * bus; /* bus this device is on, for bridge * devices, it is the up stream bus */ - device_t sibling; /* next device on this bus */ - device_t next; /* chain of all devices */ + + ROMSTAGE_CONST struct device * sibling; /* next device on this bus */ + + ROMSTAGE_CONST struct device * next; /* chain of all devices */ struct device_path path; unsigned vendor; @@ -89,23 +94,24 @@ struct device { u8 command; /* Base registers for this device. I/O, MEM and Expansion ROM */ - struct resource *resource_list; + ROMSTAGE_CONST struct resource *resource_list; /* links are (downstream) buses attached to the device, usually a leaf * device with no children has 0 buses attached and a bridge has 1 bus */ - struct bus *link_list; + ROMSTAGE_CONST struct bus *link_list; struct device_operations *ops; const struct chip_operations *chip_ops; - void *chip_info; + ROMSTAGE_CONST void *chip_info; }; /** * This is the root of the device tree. The device tree is defined in the * static.c file and is generated by the config tool at compile time. */ -extern struct device dev_root; +extern ROMSTAGE_CONST struct device dev_root; +#ifndef __PRE_RAM__ extern struct device *all_devices; /* list of all devices */ extern struct resource *free_resources; @@ -195,5 +201,10 @@ void fixed_mem_resource(device_t dev, unsigned long index, void tolm_test(void *gp, struct device *dev, struct resource *new); u32 find_pci_tolm(struct bus *bus); - +#else +ROMSTAGE_CONST struct device * dev_find_slot (unsigned int bus, + unsigned int devfn); +ROMSTAGE_CONST struct device * dev_find_slot_on_smbus (unsigned int bus, + unsigned int addr); +#endif #endif /* DEVICE_H */ diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 51d5283..a215a2a 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -16,9 +16,11 @@ #define PCI_H #include <stdint.h> +#include <stddef.h> #include <device/pci_def.h> #include <device/resource.h> #include <device/device.h> +#ifndef __PRE_RAM__ #include <device/pci_ops.h> #include <device/pci_rom.h> @@ -107,4 +109,5 @@ static inline const struct pci_bus_operations *ops_pci_bus(struct bus *bus) unsigned mainboard_pci_subsystem_vendor_id(struct device *dev); unsigned mainboard_pci_subsystem_device_id(struct device *dev); +#endif #endif /* PCI_H */ diff --git a/src/include/device/resource.h b/src/include/device/resource.h index c28ada5..ddedc2f 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -2,6 +2,7 @@ #define DEVICE_RESOURCE_H #include <stdint.h> +#include <stddef.h> #define IORESOURCE_BITS 0x000000ff /* Bus-specific bits */ @@ -72,7 +73,7 @@ struct resource { resource_t base; /* Base address of the resource */ resource_t size; /* Size of the resource */ resource_t limit; /* Largest valid value base + size -1 */ - struct resource* next; /* Next resource in the list */ + ROMSTAGE_CONST struct resource* next; /* Next resource in the list */ unsigned long flags; /* Descriptions of the kind of resource */ unsigned long index; /* Bus specific per device resource id */ unsigned char align; /* Required alignment (log 2) of the resource */ diff --git a/util/lint/lint-stable-002-build-dir-handling b/util/lint/lint-stable-002-build-dir-handling index c4247b5..d5295d2 100755 --- a/util/lint/lint-stable-002-build-dir-handling +++ b/util/lint/lint-stable-002-build-dir-handling @@ -20,7 +20,7 @@ # $1: command to test for GNU make search_make() { -if [ -n "`$1 --version 2>&1 |grep GNU`" ]; then MAKE=$1; fi +if [ -n "`$1 --version 2>&1 | grep GNU`" ]; then MAKE=$1; fi } # if $1 and $2 differ, exit with failure @@ -33,7 +33,12 @@ fi # $1: object directory run_printall() { -$MAKE CONFIG_USE_BLOBS=n CONFIG_CCACHE=n CONFIG_SCANBUILD_ENABLE=n NOMKDIR=1 DOTCONFIG=$TMPCONFIG obj=$1 printall |sed -e "s,^ *,," -e "s,^ramstage-objs:=,," -e "s,mainboard/[^/]*/[^/]*/,.../," |tr " " "\n"|grep "/static.*\.[co]" |sort |tr '\012\015' ' ' |sed -e "s, *, ,g" -e "s, *$,," +$MAKE CONFIG_USE_BLOBS=n CONFIG_CCACHE=n CONFIG_SCANBUILD_ENABLE=n NOMKDIR=1 \ + DOTCONFIG=$TMPCONFIG obj=$1 printall | \ + sed -e "s,^ *,," -e "s,^r.mstage-objs:=,," \ + -e "s,mainboard/[^/]*/[^/]*/,.../,g" | \ + tr " " "\n" | grep "/static.*\.[co]" | sort | \ + tr '\012\015' ' ' | sed -e "s, *, ,g" -e "s, *$,," } # find GNU make @@ -54,10 +59,10 @@ $MAKE DOTCONFIG=$TMPCONFIG allyesconfig >/dev/null # look up parent directory PARENTDIR=`dirname $PWD` -compare_output "`run_printall build`" "build/.../static.c build/.../static.ramstage.o" -compare_output "`run_printall ../obj`" "$PARENTDIR/obj/.../static.c $PARENTDIR/obj/.../static.ramstage.o" -compare_output "`run_printall /tmp`" "/tmp/.../static.c /tmp/.../static.ramstage.o" -compare_output "`run_printall /../tmp`" "/tmp/.../static.c /tmp/.../static.ramstage.o" +compare_output "`run_printall build`" "build/.../static.c build/.../static.c build/.../static.ramstage.o build/.../static.romstage.o" +compare_output "`run_printall ../obj`" "$PARENTDIR/obj/.../static.c $PARENTDIR/obj/.../static.c $PARENTDIR/obj/.../static.ramstage.o $PARENTDIR/obj/.../static.romstage.o" +compare_output "`run_printall /tmp`" "/tmp/.../static.c /tmp/.../static.c /tmp/.../static.ramstage.o /tmp/.../static.romstage.o" +compare_output "`run_printall /../tmp`" "/tmp/.../static.c /tmp/.../static.c /tmp/.../static.ramstage.o /tmp/.../static.romstage.o" rm -f $TMPCONFIG diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 824bc6c..82a7491 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -366,13 +366,15 @@ void add_ioapic_info(struct device *dev, int apicid, const char *_srcpin, int ir static void pass0(FILE *fil, struct device *ptr) { if (ptr->type == device && ptr->id == 0) - fprintf(fil, "struct bus %s_links[];\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct bus %s_links[];\n", ptr->name); + if ((ptr->type == device) && (ptr->id != 0) && (!ptr->used)) { - fprintf(fil, "static struct device %s;\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST static struct device %s;\n", ptr->name); if (ptr->rescnt > 0) - fprintf(fil, "struct resource %s_res[];\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct resource %s_res[];\n", ptr->name); if (ptr->children || ptr->multidev) - fprintf(fil, "struct bus %s_links[];\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct bus %s_links[];\n", + ptr->name); } } @@ -382,8 +384,10 @@ static void pass1(FILE *fil, struct device *ptr) if (!ptr->used && (ptr->type == device)) { if (ptr->id != 0) fprintf(fil, "static "); - fprintf(fil, "struct device %s = {\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct device %s = {\n", ptr->name); + fprintf(fil, "#ifndef __PRE_RAM__\n"); fprintf(fil, "\t.ops = %s,\n", (ptr->ops)?(ptr->ops):"0"); + fprintf(fil, "#endif\n"); fprintf(fil, "\t.bus = &%s_links[%d],\n", ptr->bus->name, ptr->bus->link); fprintf(fil, "\t.path = {"); fprintf(fil, ptr->path, ptr->path_a, ptr->path_b); @@ -415,7 +419,9 @@ static void pass1(FILE *fil, struct device *ptr) if (ptr->sibling) fprintf(fil, "\t.sibling = &%s,\n", ptr->sibling->name); if (ptr->chip->chiph_exists) { + fprintf(fil, "#ifndef __PRE_RAM__\n"); fprintf(fil, "\t.chip_ops = &%s_ops,\n", ptr->chip->name_underscore); + fprintf(fil, "#endif\n"); fprintf(fil, "\t.chip_info = &%s_info_%d,\n", ptr->chip->name_underscore, ptr->chip->id); } if (ptr->nextdev) @@ -424,7 +430,8 @@ static void pass1(FILE *fil, struct device *ptr) } if (ptr->rescnt > 0) { int i=1; - fprintf(fil, "struct resource %s_res[] = {\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct resource %s_res[] = {\n", + ptr->name); struct resource *r = ptr->res; while (r) { fprintf(fil, "\t\t{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_"); @@ -441,7 +448,7 @@ static void pass1(FILE *fil, struct device *ptr) fprintf(fil, "\t };\n"); } if (!ptr->used && ptr->type == device && (ptr->children || ptr->multidev)) { - fprintf(fil, "struct bus %s_links[] = {\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct bus %s_links[] = {\n", ptr->name); if (ptr->multidev) { struct device *d = ptr; while (d) { @@ -473,8 +480,9 @@ static void pass1(FILE *fil, struct device *ptr) } if ((ptr->type == chip) && (ptr->chiph_exists)) { if (ptr->reg) { - fprintf(fil, "struct %s_config %s_info_%d\t= {\n", - ptr->name_underscore, ptr->name_underscore, ptr->id); + fprintf(fil, "ROMSTAGE_CONST struct %s_config ROMSTAGE_CONST %s_info_%d = {\n", + ptr->name_underscore, ptr->name_underscore, + ptr->id); struct reg *r = ptr->reg; while (r) { fprintf(fil, "\t.%s = %s,\n", r->key, r->value); @@ -482,7 +490,7 @@ static void pass1(FILE *fil, struct device *ptr) } fprintf(fil, "};\n\n"); } else { - fprintf(fil, "struct %s_config %s_info_%d;\n", + fprintf(fil, "ROMSTAGE_CONST struct %s_config ROMSTAGE_CONST %s_info_%d = { };\n", ptr->name_underscore, ptr->name_underscore, ptr->id); } } @@ -617,9 +625,9 @@ int main(int argc, char** argv) { fprintf(autogen, "\n/* pass 0 */\n"); walk_device_tree(autogen, &root, pass0, NULL); fprintf(autogen, "\n/* pass 1 */\n" - "struct device *last_dev = &%s;\n", lastdev->name); + "ROMSTAGE_CONST struct device * ROMSTAGE_CONST last_dev = &%s;\n", lastdev->name); #ifdef MAINBOARDS_HAVE_CHIP_H - fprintf(autogen, "struct mainboard_config mainboard_info_0;\n"); + fprintf(autogen, "static ROMSTAGE_CONST struct mainboard_config ROMSTAGE_CONST mainboard_info_0;\n"); #endif walk_device_tree(autogen, &root, pass1, NULL);

1 0

Patch set updated for coreboot: 866b519 Make the device tree available in the rom stage
by Stefan Reinauer 03 Aug '12

03 Aug '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1398 -gerrit commit 866b519aa88a4177508d182b4c18a61b919d94c5 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 31 16:47:25 2012 -0700 Make the device tree available in the rom stage We thought about two ways to do this change. The way we decided to try was to 1. drop all ops from devices in romstage 2. constify all devices in romstage (make them read-only) so we can compile static.c into romstage 3. the device tree "devices" can be used to read configuration from the device tree (and nothing else, really) 4. the device tree devices are accessed through struct device * in romstage only. device_t stays the typedef to int in romstage 5. Use the same static.c file in ramstage and romstage We declare structs as follows: ROMSTAGE_CONST struct bus dev_root_links[]; ROMSTAGE_CONST is const in romstage and empty in ramstage; This forces all of the device tree into the text area. So a struct looks like this: static ROMSTAGE_CONST struct device _dev21 = { #ifndef __PRE_RAM__ .ops = 0, #endif .bus = &_dev7_links[0], .path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}}, .enabled = 0, .on_mainboard = 1, .subsystem_vendor = 0x1ae0, .subsystem_device = 0xc000, .link_list = NULL, .sibling = &_dev22, #ifndef __PRE_RAM__ .chip_ops = &southbridge_intel_bd82x6x_ops, #endif .chip_info = &southbridge_intel_bd82x6x_info_10, .next=&_dev22 }; Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727 Signed-off-by: Ronald G. Minnich <rminnich(a)chromium.org> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- Makefile.inc | 5 ++ src/arch/x86/include/stddef.h | 6 ++ src/cpu/amd/agesa/s3_resume.c | 2 + src/devices/Makefile.inc | 2 + src/devices/device_romstage.c | 80 ++++++++++++++++++++++++++ src/include/device/device.h | 35 +++++++---- src/include/device/pci.h | 3 + src/include/device/resource.h | 3 +- util/lint/lint-stable-002-build-dir-handling | 17 ++++-- util/sconfig/main.c | 32 +++++++---- 10 files changed, 154 insertions(+), 31 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index ca1e066..083d423 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -228,6 +228,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/static.c: $(src)/mainboard/$(MAINBOARDDIR)/devi $(objutil)/sconfig/sconfig $(MAINBOARDDIR) $(obj)/mainboard/$(MAINBOARDDIR) ramstage-y+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c +romstage-y+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c $(objutil)/%.o: $(objutil)/%.c @printf " HOSTCC $(subst $(objutil)/,,$(@))\n" @@ -237,6 +238,10 @@ $(obj)/%.ramstage.o $(abspath $(obj))/%.ramstage.o: $(obj)/%.c $(obj)/config.h $ @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD $(CFLAGS) -c -o $@ $< +$(obj)/%.romstage.o $(abspath $(obj))/%.romstage.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -MMD -D__PRE_RAM__ $(CFLAGS) -c -o $@ $< + ####################################################################### # Clean up rules clean-abuild: diff --git a/src/arch/x86/include/stddef.h b/src/arch/x86/include/stddef.h index a6c3fc6..fc89de5 100644 --- a/src/arch/x86/include/stddef.h +++ b/src/arch/x86/include/stddef.h @@ -15,4 +15,10 @@ typedef unsigned int wint_t; #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) +#ifdef __PRE_RAM__ +#define ROMSTAGE_CONST const +#else +#define ROMSTAGE_CONST +#endif + #endif /* I386_STDDEF_H */ diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 6bb053d..0348a9f 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -29,7 +29,9 @@ #endif #include <device/device.h> #include <device/pci.h> +#ifndef __PRE_RAM__ #include <device/pci_ops.h> +#endif #include <arch/io.h> #include <arch/acpi.h> #include <string.h> diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc index 9ffc0bb..9a2f71e 100644 --- a/src/devices/Makefile.inc +++ b/src/devices/Makefile.inc @@ -11,6 +11,8 @@ ramstage-y += pnp_device.c ramstage-y += pci_ops.c ramstage-y += smbus_ops.c +romstage-y+= device_romstage.c + subdirs-y += oprom ifeq ($(CONFIG_PCI_ROM_RUN),y) diff --git a/src/devices/device_romstage.c b/src/devices/device_romstage.c new file mode 100644 index 0000000..475f94a --- /dev/null +++ b/src/devices/device_romstage.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003-2004 Linux Networx + * (Written by Eric Biederman <ebiederman(a)lnxi.com> for Linux Networx) + * Copyright (C) 2003 Greg Watson <jarrah(a)users.sourceforge.net> + * Copyright (C) 2004 Li-Ta Lo <ollie(a)lanl.gov> + * Copyright (C) 2005-2006 Tyan + * (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/path.h> +#include <device/pci.h> +#include <device/resource.h> + +/** Linked list of ALL devices */ +ROMSTAGE_CONST struct device * ROMSTAGE_CONST all_devices = &dev_root; + +/** + * Given a PCI bus and a devfn number, find the device structure. + * + * @param bus The bus number. + * @param devfn A device/function number. + * @return Pointer to the device structure (if found), 0 otherwise. + */ +ROMSTAGE_CONST struct device *dev_find_slot(unsigned int bus, + unsigned int devfn) +{ + ROMSTAGE_CONST struct device *dev, *result; + + result = 0; + for (dev = all_devices; dev; dev = dev->next) { + if ((dev->path.type == DEVICE_PATH_PCI) && + (dev->bus->secondary == bus) && + (dev->path.pci.devfn == devfn)) { + result = dev; + break; + } + } + return result; +} + +/** + * Given an SMBus bus and a device number, find the device structure. + * + * @param bus The bus number. + * @param addr A device number. + * @return Pointer to the device structure (if found), 0 otherwise. + */ +ROMSTAGE_CONST struct device *dev_find_slot_on_smbus(unsigned int bus, + unsigned int addr) +{ + ROMSTAGE_CONST struct device *dev, *result; + + result = 0; + for (dev = all_devices; dev; dev = dev->next) { + if ((dev->path.type == DEVICE_PATH_I2C) && + (dev->bus->secondary == bus) && + (dev->path.i2c.device == addr)) { + result = dev; + break; + } + } + return result; +} + diff --git a/src/include/device/device.h b/src/include/device/device.h index 0b15ac5..b44a551 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -2,11 +2,12 @@ #define DEVICE_H #include <stdint.h> +#include <stddef.h> #include <device/resource.h> #include <device/path.h> - struct device; +#ifndef __PRE_RAM__ typedef struct device * device_t; struct pci_operations; struct pci_bus_operations; @@ -42,12 +43,14 @@ struct device_operations { const struct smbus_bus_operations *ops_smbus_bus; const struct pci_bus_operations *ops_pci_bus; }; +#endif struct bus { - device_t dev; /* This bridge device */ - device_t children; /* devices behind this bridge */ - struct bus *next; /* The next bridge on this device */ + + ROMSTAGE_CONST struct device * dev; /* This bridge device */ + ROMSTAGE_CONST struct device * children; /* devices behind this bridge */ + ROMSTAGE_CONST struct bus *next; /* The next bridge on this device */ unsigned bridge_ctrl; /* Bridge control register */ unsigned char link_num; /* The index of this link */ uint16_t secondary; /* secondary bus number */ @@ -70,10 +73,12 @@ struct pci_irq_info { }; struct device { - struct bus * bus; /* bus this device is on, for bridge + ROMSTAGE_CONST struct bus * bus; /* bus this device is on, for bridge * devices, it is the up stream bus */ - device_t sibling; /* next device on this bus */ - device_t next; /* chain of all devices */ + + ROMSTAGE_CONST struct device * sibling; /* next device on this bus */ + + ROMSTAGE_CONST struct device * next; /* chain of all devices */ struct device_path path; unsigned vendor; @@ -89,23 +94,24 @@ struct device { u8 command; /* Base registers for this device. I/O, MEM and Expansion ROM */ - struct resource *resource_list; + ROMSTAGE_CONST struct resource *resource_list; /* links are (downstream) buses attached to the device, usually a leaf * device with no children has 0 buses attached and a bridge has 1 bus */ - struct bus *link_list; + ROMSTAGE_CONST struct bus *link_list; struct device_operations *ops; const struct chip_operations *chip_ops; - void *chip_info; + ROMSTAGE_CONST void *chip_info; }; /** * This is the root of the device tree. The device tree is defined in the * static.c file and is generated by the config tool at compile time. */ -extern struct device dev_root; +extern ROMSTAGE_CONST struct device dev_root; +#ifndef __PRE_RAM__ extern struct device *all_devices; /* list of all devices */ extern struct resource *free_resources; @@ -195,5 +201,10 @@ void fixed_mem_resource(device_t dev, unsigned long index, void tolm_test(void *gp, struct device *dev, struct resource *new); u32 find_pci_tolm(struct bus *bus); - +#else +ROMSTAGE_CONST struct device * dev_find_slot (unsigned int bus, + unsigned int devfn); +ROMSTAGE_CONST struct device * dev_find_slot_on_smbus (unsigned int bus, + unsigned int addr); +#endif #endif /* DEVICE_H */ diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 51d5283..a215a2a 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -16,9 +16,11 @@ #define PCI_H #include <stdint.h> +#include <stddef.h> #include <device/pci_def.h> #include <device/resource.h> #include <device/device.h> +#ifndef __PRE_RAM__ #include <device/pci_ops.h> #include <device/pci_rom.h> @@ -107,4 +109,5 @@ static inline const struct pci_bus_operations *ops_pci_bus(struct bus *bus) unsigned mainboard_pci_subsystem_vendor_id(struct device *dev); unsigned mainboard_pci_subsystem_device_id(struct device *dev); +#endif #endif /* PCI_H */ diff --git a/src/include/device/resource.h b/src/include/device/resource.h index c28ada5..ddedc2f 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -2,6 +2,7 @@ #define DEVICE_RESOURCE_H #include <stdint.h> +#include <stddef.h> #define IORESOURCE_BITS 0x000000ff /* Bus-specific bits */ @@ -72,7 +73,7 @@ struct resource { resource_t base; /* Base address of the resource */ resource_t size; /* Size of the resource */ resource_t limit; /* Largest valid value base + size -1 */ - struct resource* next; /* Next resource in the list */ + ROMSTAGE_CONST struct resource* next; /* Next resource in the list */ unsigned long flags; /* Descriptions of the kind of resource */ unsigned long index; /* Bus specific per device resource id */ unsigned char align; /* Required alignment (log 2) of the resource */ diff --git a/util/lint/lint-stable-002-build-dir-handling b/util/lint/lint-stable-002-build-dir-handling index c4247b5..d5295d2 100755 --- a/util/lint/lint-stable-002-build-dir-handling +++ b/util/lint/lint-stable-002-build-dir-handling @@ -20,7 +20,7 @@ # $1: command to test for GNU make search_make() { -if [ -n "`$1 --version 2>&1 |grep GNU`" ]; then MAKE=$1; fi +if [ -n "`$1 --version 2>&1 | grep GNU`" ]; then MAKE=$1; fi } # if $1 and $2 differ, exit with failure @@ -33,7 +33,12 @@ fi # $1: object directory run_printall() { -$MAKE CONFIG_USE_BLOBS=n CONFIG_CCACHE=n CONFIG_SCANBUILD_ENABLE=n NOMKDIR=1 DOTCONFIG=$TMPCONFIG obj=$1 printall |sed -e "s,^ *,," -e "s,^ramstage-objs:=,," -e "s,mainboard/[^/]*/[^/]*/,.../," |tr " " "\n"|grep "/static.*\.[co]" |sort |tr '\012\015' ' ' |sed -e "s, *, ,g" -e "s, *$,," +$MAKE CONFIG_USE_BLOBS=n CONFIG_CCACHE=n CONFIG_SCANBUILD_ENABLE=n NOMKDIR=1 \ + DOTCONFIG=$TMPCONFIG obj=$1 printall | \ + sed -e "s,^ *,," -e "s,^r.mstage-objs:=,," \ + -e "s,mainboard/[^/]*/[^/]*/,.../,g" | \ + tr " " "\n" | grep "/static.*\.[co]" | sort | \ + tr '\012\015' ' ' | sed -e "s, *, ,g" -e "s, *$,," } # find GNU make @@ -54,10 +59,10 @@ $MAKE DOTCONFIG=$TMPCONFIG allyesconfig >/dev/null # look up parent directory PARENTDIR=`dirname $PWD` -compare_output "`run_printall build`" "build/.../static.c build/.../static.ramstage.o" -compare_output "`run_printall ../obj`" "$PARENTDIR/obj/.../static.c $PARENTDIR/obj/.../static.ramstage.o" -compare_output "`run_printall /tmp`" "/tmp/.../static.c /tmp/.../static.ramstage.o" -compare_output "`run_printall /../tmp`" "/tmp/.../static.c /tmp/.../static.ramstage.o" +compare_output "`run_printall build`" "build/.../static.c build/.../static.c build/.../static.ramstage.o build/.../static.romstage.o" +compare_output "`run_printall ../obj`" "$PARENTDIR/obj/.../static.c $PARENTDIR/obj/.../static.c $PARENTDIR/obj/.../static.ramstage.o $PARENTDIR/obj/.../static.romstage.o" +compare_output "`run_printall /tmp`" "/tmp/.../static.c /tmp/.../static.c /tmp/.../static.ramstage.o /tmp/.../static.romstage.o" +compare_output "`run_printall /../tmp`" "/tmp/.../static.c /tmp/.../static.c /tmp/.../static.ramstage.o /tmp/.../static.romstage.o" rm -f $TMPCONFIG diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 824bc6c..82a7491 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -366,13 +366,15 @@ void add_ioapic_info(struct device *dev, int apicid, const char *_srcpin, int ir static void pass0(FILE *fil, struct device *ptr) { if (ptr->type == device && ptr->id == 0) - fprintf(fil, "struct bus %s_links[];\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct bus %s_links[];\n", ptr->name); + if ((ptr->type == device) && (ptr->id != 0) && (!ptr->used)) { - fprintf(fil, "static struct device %s;\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST static struct device %s;\n", ptr->name); if (ptr->rescnt > 0) - fprintf(fil, "struct resource %s_res[];\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct resource %s_res[];\n", ptr->name); if (ptr->children || ptr->multidev) - fprintf(fil, "struct bus %s_links[];\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct bus %s_links[];\n", + ptr->name); } } @@ -382,8 +384,10 @@ static void pass1(FILE *fil, struct device *ptr) if (!ptr->used && (ptr->type == device)) { if (ptr->id != 0) fprintf(fil, "static "); - fprintf(fil, "struct device %s = {\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct device %s = {\n", ptr->name); + fprintf(fil, "#ifndef __PRE_RAM__\n"); fprintf(fil, "\t.ops = %s,\n", (ptr->ops)?(ptr->ops):"0"); + fprintf(fil, "#endif\n"); fprintf(fil, "\t.bus = &%s_links[%d],\n", ptr->bus->name, ptr->bus->link); fprintf(fil, "\t.path = {"); fprintf(fil, ptr->path, ptr->path_a, ptr->path_b); @@ -415,7 +419,9 @@ static void pass1(FILE *fil, struct device *ptr) if (ptr->sibling) fprintf(fil, "\t.sibling = &%s,\n", ptr->sibling->name); if (ptr->chip->chiph_exists) { + fprintf(fil, "#ifndef __PRE_RAM__\n"); fprintf(fil, "\t.chip_ops = &%s_ops,\n", ptr->chip->name_underscore); + fprintf(fil, "#endif\n"); fprintf(fil, "\t.chip_info = &%s_info_%d,\n", ptr->chip->name_underscore, ptr->chip->id); } if (ptr->nextdev) @@ -424,7 +430,8 @@ static void pass1(FILE *fil, struct device *ptr) } if (ptr->rescnt > 0) { int i=1; - fprintf(fil, "struct resource %s_res[] = {\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct resource %s_res[] = {\n", + ptr->name); struct resource *r = ptr->res; while (r) { fprintf(fil, "\t\t{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_"); @@ -441,7 +448,7 @@ static void pass1(FILE *fil, struct device *ptr) fprintf(fil, "\t };\n"); } if (!ptr->used && ptr->type == device && (ptr->children || ptr->multidev)) { - fprintf(fil, "struct bus %s_links[] = {\n", ptr->name); + fprintf(fil, "ROMSTAGE_CONST struct bus %s_links[] = {\n", ptr->name); if (ptr->multidev) { struct device *d = ptr; while (d) { @@ -473,8 +480,9 @@ static void pass1(FILE *fil, struct device *ptr) } if ((ptr->type == chip) && (ptr->chiph_exists)) { if (ptr->reg) { - fprintf(fil, "struct %s_config %s_info_%d\t= {\n", - ptr->name_underscore, ptr->name_underscore, ptr->id); + fprintf(fil, "ROMSTAGE_CONST struct %s_config ROMSTAGE_CONST %s_info_%d = {\n", + ptr->name_underscore, ptr->name_underscore, + ptr->id); struct reg *r = ptr->reg; while (r) { fprintf(fil, "\t.%s = %s,\n", r->key, r->value); @@ -482,7 +490,7 @@ static void pass1(FILE *fil, struct device *ptr) } fprintf(fil, "};\n\n"); } else { - fprintf(fil, "struct %s_config %s_info_%d;\n", + fprintf(fil, "ROMSTAGE_CONST struct %s_config ROMSTAGE_CONST %s_info_%d = { };\n", ptr->name_underscore, ptr->name_underscore, ptr->id); } } @@ -617,9 +625,9 @@ int main(int argc, char** argv) { fprintf(autogen, "\n/* pass 0 */\n"); walk_device_tree(autogen, &root, pass0, NULL); fprintf(autogen, "\n/* pass 1 */\n" - "struct device *last_dev = &%s;\n", lastdev->name); + "ROMSTAGE_CONST struct device * ROMSTAGE_CONST last_dev = &%s;\n", lastdev->name); #ifdef MAINBOARDS_HAVE_CHIP_H - fprintf(autogen, "struct mainboard_config mainboard_info_0;\n"); + fprintf(autogen, "static ROMSTAGE_CONST struct mainboard_config ROMSTAGE_CONST mainboard_info_0;\n"); #endif walk_device_tree(autogen, &root, pass1, NULL);

1 0

Patch set updated for coreboot: dd9e9f1 Add a capability for mainboard-specific posting.
by Alexandru Gagniuc 03 Aug '12

03 Aug '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1397 -gerrit commit dd9e9f1786dbdb314ce0c4244dee85357e2ae58a Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Aug 3 13:20:57 2012 -0500 Add a capability for mainboard-specific posting. Some mainboards have really nice capabilities for posting, beyond simple POST cards. Further, some can not use a POST card. This change defines a weak symbol (mainboard_post) that can be overridden by a real mainboard_post function. If, for example, you'd like to do something fancy before the payload starts, you can add this to mainboard.c: void mainboard_post(u8 value) { switch(value){ case POST_TIME_TO_PARTY: some_fancy_lights(); break; } } Maybe the post function should be an entry in the device. We're beginning to over-use weak symbols. BUG=None TEST=Build and boot a google chromebook. Observe that it still works. Use it to drive some pretty lights. Change-Id: I3512d2ec34a66c747287191851c3f68b6a7cc1b2 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/console/post.c | 15 +++++++++++++++ src/include/console/console.h | 2 ++ 2 files changed, 17 insertions(+), 0 deletions(-) diff --git a/src/console/post.c b/src/console/post.c index 08336a2..be2d0e9 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -24,6 +24,20 @@ /* Write POST information */ +/* someday romcc will be gone. */ +#ifndef __ROMCC__ +/* Some mainboards have very nice features beyond just a simple display. + * They can override this function. + */ +void __attribute__((weak)) mainboard_post(uint8_t value) +{ +} + +#else +/* This just keeps the number of #ifs to a minimum */ +#define mainboard_post(x) +#endif + void post_code(uint8_t value) { #if !CONFIG_NO_POST @@ -34,4 +48,5 @@ void post_code(uint8_t value) #endif outb(value, CONFIG_POST_PORT); #endif + mainboard_post(value); } diff --git a/src/include/console/console.h b/src/include/console/console.h index 56e202d..00be96f 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -69,6 +69,8 @@ extern int console_loglevel; #ifndef __ROMCC__ void console_init(void); void post_code(u8 value); +/* this function is weak and can be overridden by a mainboard function. */ +void mainboard_post(u8 value); void __attribute__ ((noreturn)) die(const char *msg); int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));

1 0

Patch merged into coreboot/master: ea09f9b VIA Epia-N: drop add_mainboard_resources()
by gerrit＠coreboot.org 03 Aug '12

03 Aug '12

the following patch was just integrated into master: commit ea09f9b62ad0fe5f0a40e1bf6c76fd411c6794fa Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Aug 2 09:43:48 2012 +0300 VIA Epia-N: drop add_mainboard_resources() The board had HAVE_MAINBOARD_RESOURCES=0 so this was never called. Drop unnecessary includes too. Change-Id: Ia7bddf29a16966c052b5cabbb47029299e6dbd12 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Aug 2 14:23:42 2012, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Fri Aug 3 12:25:51 2012, giving +2 See http://review.coreboot.org/1392 for details. -gerrit

1 0

Patch merged into coreboot/master: 850fd7a Intel CPUs: Fix counting of CPU cores
by gerrit＠coreboot.org 03 Aug '12

03 Aug '12

the following patch was just integrated into master: commit 850fd7a8379c49ec961dda12c8119f405c0d3cec Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jul 4 12:02:58 2012 +0300 Intel CPUs: Fix counting of CPU cores Detection for a hyper-threading CPU was not compatible with multicore CPUs. When using CPUID eax==4, also need to set ecx=0. CAR init tested on real hardware with hyper-threading model_f25 and under qemu 0.15.1 with multicore CPU. Change-Id: I28ac8790f94652e4ba8ff88fe7812c812f967608 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Jul 31 22:27:13 2012, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Fri Aug 3 12:19:31 2012, giving +2 See http://review.coreboot.org/1172 for details. -gerrit

1 0

Patch set updated for coreboot: ab1ad92 AMD S3: Remove the hardcoded volatile position
by Zheng Bao 03 Aug '12

03 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1408 -gerrit commit ab1ad9270161bec43bcee0adcff001fd0f6cd4b8 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Aug 3 19:47:27 2012 +0800 AMD S3: Remove the hardcoded volatile position Change-Id: I4bcf3f3435f0ba487955d14ed1b010fd94b9f625 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.h | 6 +++--- src/southbridge/amd/Kconfig | 5 +++++ src/southbridge/amd/Makefile.inc | 4 ++-- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h index 16ec411..10bc826 100644 --- a/src/cpu/amd/agesa/s3_resume.h +++ b/src/cpu/amd/agesa/s3_resume.h @@ -20,9 +20,9 @@ #ifndef S3_RESUME_H #define S3_RESUME_H -#define S3_DATA_NONVOLATILE_POS 0xFFFF7000 -#define S3_DATA_VOLATILE_POS 0xFFFF0000 -#define S3_DATA_MTRR_POS 0xFFFF6000 +#define S3_DATA_NONVOLATILE_POS (CONFIG_S3_VOLATILE_POS + 0x7000) +#define S3_DATA_VOLATILE_POS CONFIG_S3_VOLATILE_POS +#define S3_DATA_MTRR_POS (CONFIG_S3_VOLATILE_POS + 0x6000) typedef enum { S3DataTypeNonVolatile=0, ///< NonVolatile Data Type diff --git a/src/southbridge/amd/Kconfig b/src/southbridge/amd/Kconfig index 867afca..23f6c06 100644 --- a/src/southbridge/amd/Kconfig +++ b/src/southbridge/amd/Kconfig @@ -14,3 +14,8 @@ source src/southbridge/amd/sb800/Kconfig source src/southbridge/amd/cimx/Kconfig source src/southbridge/amd/agesa/Kconfig source src/southbridge/amd/sr5650/Kconfig + +# This can be overriden by mainboard/Kconfig +config S3_VOLATILE_POS + hex + default 0xFFFF0000 diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index 733a9bc..449745a 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -20,14 +20,14 @@ ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) ifeq ($(CONFIG_CPU_AMD_AGESA), y) $(obj)/s3.rom: - echo " S3 NVRAM 0xffff0000 (S3 storage area)" + echo " S3 NVRAM $(CONFIG_S3_VOLATILE_POS) (S3 storage area)" @ # force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse) LC_ALL=C awk 'BEGIN {for (i=0; i<32768; i++) {printf "%c", 255}}' > $@.tmp mv $@.tmp $@ cbfs-files-y += s3nv s3nv-file := $(obj)/s3.rom -s3nv-position := 0xffff0000 +s3nv-position := $(CONFIG_S3_VOLATILE_POS) s3nv-type := raw endif # CONFIG_CPU_AMD_AGESA == y

1 0

New patch to review for coreboot: bbede2e AMD S3: Remove the hardcoded volatile position
by Zheng Bao 03 Aug '12

03 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1408 -gerrit commit bbede2e244e79735525f838ef20ec9b10a760dee Author: zbao <fishbaozi(a)gmail.com> Date: Fri Aug 3 19:29:18 2012 +0800 AMD S3: Remove the hardcoded volatile position Change-Id: I4bcf3f3435f0ba487955d14ed1b010fd94b9f625 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/southbridge/amd/Kconfig | 5 +++++ src/southbridge/amd/Makefile.inc | 4 ++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/Kconfig b/src/southbridge/amd/Kconfig index 867afca..23f6c06 100644 --- a/src/southbridge/amd/Kconfig +++ b/src/southbridge/amd/Kconfig @@ -14,3 +14,8 @@ source src/southbridge/amd/sb800/Kconfig source src/southbridge/amd/cimx/Kconfig source src/southbridge/amd/agesa/Kconfig source src/southbridge/amd/sr5650/Kconfig + +# This can be overriden by mainboard/Kconfig +config S3_VOLATILE_POS + hex + default 0xFFFF0000 diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index 733a9bc..449745a 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -20,14 +20,14 @@ ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) ifeq ($(CONFIG_CPU_AMD_AGESA), y) $(obj)/s3.rom: - echo " S3 NVRAM 0xffff0000 (S3 storage area)" + echo " S3 NVRAM $(CONFIG_S3_VOLATILE_POS) (S3 storage area)" @ # force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse) LC_ALL=C awk 'BEGIN {for (i=0; i<32768; i++) {printf "%c", 255}}' > $@.tmp mv $@.tmp $@ cbfs-files-y += s3nv s3nv-file := $(obj)/s3.rom -s3nv-position := 0xffff0000 +s3nv-position := $(CONFIG_S3_VOLATILE_POS) s3nv-type := raw endif # CONFIG_CPU_AMD_AGESA == y

1 0

Patch set updated for coreboot: bddf83d AMD northbridge: copy TOP_MEM and TOP_MEM2 for distribution
by Kyösti Mälkki 03 Aug '12

03 Aug '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1387 -gerrit commit bddf83d332384ea13884d481c3f2855a4fcee468 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jul 31 20:51:48 2012 +0300 AMD northbridge: copy TOP_MEM and TOP_MEM2 for distribution Take a copy of BSP CPU's TOP_MEM and TOP_MEM2 MSRs to be distributed to AP CPUs and factor out the debugging info from setup_uma_memory(). Change-Id: I1acb4eaa3fe118aee223df1ebff997289f5d3a56 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/mtrr/amd_mtrr.c | 38 ++++++++++++++++++++ src/include/cpu/amd/mtrr.h | 5 +++ src/northbridge/amd/agesa/family10/northbridge.c | 1 + src/northbridge/amd/agesa/family12/northbridge.c | 23 +++--------- src/northbridge/amd/agesa/family14/northbridge.c | 23 +++--------- src/northbridge/amd/agesa/family15/northbridge.c | 22 +++--------- src/northbridge/amd/agesa/family15tn/northbridge.c | 23 +++--------- src/northbridge/amd/amdfam10/northbridge.c | 22 ++--------- src/northbridge/amd/amdk8/northbridge.c | 21 +++-------- 9 files changed, 74 insertions(+), 104 deletions(-) diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index f639d59..9349ad4 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -116,6 +116,44 @@ static void uma_fb_resource(void *gp, struct device *dev, struct resource *res) } } +/* These will likely move to some device node or cbmem. */ +static uint64_t amd_topmem = 0; +static uint64_t amd_topmem2 = 0; + +uint64_t bsp_topmem(void) +{ + return amd_topmem; +} + +uint64_t bsp_topmem2(void) +{ + return amd_topmem2; +} + +/* Take a copy of BSP CPUs TOP_MEM and TOP_MEM2 registers, + * so they can be distributed to AP CPUs. Not strictly MTRRs, + * but this is not that bad a place to have this code. + */ +void setup_bsp_ramtop(void) +{ + msr_t msr, msr2; + + /* TOP_MEM: the top of DRAM below 4G */ + msr = rdmsr(TOP_MEM); + printk(BIOS_INFO, + "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + __func__, msr.lo, msr.hi); + + /* TOP_MEM2: the top of DRAM above 4G */ + msr2 = rdmsr(TOP_MEM2); + printk(BIOS_INFO, + "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + __func__, msr2.lo, msr2.hi); + + amd_topmem = (uint64_t) msr.hi<<32 | msr.lo; + amd_topmem2 = (uint64_t) msr2.hi<<32 | msr2.lo; +} + void amd_setup_mtrrs(void) { unsigned long address_bits; diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index 3637dd9..aa904e6 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -39,6 +39,11 @@ #if !defined(__PRE_RAM__) && !defined(__ASSEMBLER__) void amd_setup_mtrrs(void); + +/* To distribute topmem MSRs to APs. */ +void setup_bsp_ramtop(void); +uint64_t bsp_topmem(void); +uint64_t bsp_topmem2(void); #endif #endif /* CPU_AMD_MTRR_H */ diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 831aec0..17bcf03 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -923,6 +923,7 @@ static void amdfam10_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); #if CONFIG_GFXUMA #error Northbridge does not set uma_memory_base or uma_memory_size. #endif diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index f3f03a4..9f1b712 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -472,21 +472,9 @@ static void set_resources(device_t dev) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; + uint32_t topmem = (uint32_t) bsp_topmem(); uint32_t sys_mem; - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk - (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - /* refer to UMA Size Consideration in Family12h BKDG. */ /* Please reference MemNGetUmaSizeLN () */ /* @@ -495,19 +483,17 @@ static void setup_uma_memory(void) * >=1G 256M * <1G 64M */ - sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size - if ((msr.hi & 0x0000000F) || (sys_mem >= 0x80000000)) { + sys_mem = topmem + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size + if ((bsp_topmem2()>>32) || (sys_mem >= 0x80000000)) { uma_memory_size = 0x20000000; /* >= 2G memory, 512M recommended UMA */ } else if (sys_mem >= 0x40000000) { uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ } else { uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */ } - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -611,6 +597,7 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index af6dfcc..a5a6be0 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -520,24 +520,12 @@ static void domain_read_resources(device_t dev) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; + uint32_t topmem = (uint32_t) bsp_topmem(); uint32_t sys_mem; - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk - (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - /* refer to UMA Size Consideration in Family14h BKDG. */ - sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() - if ((msr.hi & 0x0000000F) || (sys_mem >= 0x80000000)) { + sys_mem = topmem + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() + if ((bsp_topmem2()>>32) || (sys_mem >= 0x80000000)) { uma_memory_size = 0x18000000; /* >= 2G memory, 384M recommended UMA */ } else { @@ -548,11 +536,9 @@ static void setup_uma_memory(void) } } - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -574,6 +560,7 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index a080293..6ce73cb 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -632,20 +632,9 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; + uint32_t topmem = (uint32_t) bsp_topmem(); uint32_t sys_mem; - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - /* refer to UMA Size Consideration in Family15h BKDG. */ /* Please reference MemNGetUmaSizeOR () */ /* @@ -654,20 +643,18 @@ static void setup_uma_memory(void) * >=1G 256M * <1G 64M */ - sys_mem = msr.lo + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size - if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 * ONE_MB)) { + sys_mem = topmem + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size + if ((bsp_topmem2()>>32) || (sys_mem >= 2048 * ONE_MB)) { uma_memory_size = 512 * ONE_MB; } else if (sys_mem >= 1024 * ONE_MB) { uma_memory_size = 256 * ONE_MB; } else { uma_memory_size = 64 * ONE_MB; } - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -686,6 +673,7 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 7f8650c..ba2e6c0 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -31,6 +31,7 @@ #include <cbmem.h> #include <cpu/x86/lapic.h> +#include <cpu/amd/mtrr.h> #include <Porting.h> #include <AGESA.h> @@ -641,20 +642,9 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; + uint32_t topmem = (uint32_t) bsp_topmem(); uint32_t sys_mem; - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - /* refer to UMA Size Consideration in Family15h BKDG. */ /* Please reference MemNGetUmaSizeOR () */ /* @@ -663,20 +653,18 @@ static void setup_uma_memory(void) * >=1G 256M * <1G 64M */ - sys_mem = msr.lo + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size - if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { + sys_mem = topmem + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size + if ((bsp_topmem2()>>32) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { uma_memory_size = 512 << ONE_MB_SHIFT; } else if (sys_mem >= 1024 << ONE_MB_SHIFT) { uma_memory_size = 256 << ONE_MB_SHIFT; } else { uma_memory_size = 64 << ONE_MB_SHIFT; } - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -696,6 +684,7 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 15b29f6..386a369 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -851,22 +851,9 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; - - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk(BIOS_INFO, - "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk(BIOS_INFO, - "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - + uint32_t topmem = (uint32_t) bsp_topmem(); /* refer to UMA Size Consideration in 780 BDG. */ - switch (msr.lo) { + switch (topmem) { case 0x10000000: /* 256M system memory */ uma_memory_size = 0x4000000; /* 64M recommended UMA */ break; @@ -880,11 +867,9 @@ static void setup_uma_memory(void) break; } - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -903,6 +888,7 @@ static void amdfam10_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index bec02f0..29f4709 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -826,21 +826,11 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - msr_t msr, msr2; - - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk(BIOS_INFO, "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); + uint32_t topmem = (uint32_t) bsp_topmem(); #if !CONFIG_BOARD_ASROCK_939A785GMH && !CONFIG_BOARD_AMD_MAHOGANY - switch (msr.lo) { + switch (topmem) { case 0x10000000: /* 256M system memory */ uma_memory_size = 0x2000000; /* 32M recommended UMA */ break; @@ -859,7 +849,7 @@ static void setup_uma_memory(void) } #else /* refer to UMA Size Consideration in 780 BDG. */ - switch (msr.lo) { + switch (topmem) { case 0x10000000: /* 256M system memory */ uma_memory_size = 0x4000000; /* 64M recommended UMA */ break; @@ -874,11 +864,9 @@ static void setup_uma_memory(void) } #endif - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } @@ -896,6 +884,7 @@ static void amdk8_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif + setup_bsp_ramtop(); setup_uma_memory(); #if 0

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coreboot August 2012