coreboot August 2012

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Patch set updated for coreboot: 403f4d6 AMD Thatcher: Add BIOS callback hook for getting VBIOS Image
by Zheng Bao 04 Aug '12

04 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1407 -gerrit commit 403f4d69942e9d14e381439a8a9a5ad2471568d4 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Aug 3 17:12:45 2012 +0800 AMD Thatcher: Add BIOS callback hook for getting VBIOS Image Apply the change http://review.coreboot.org/1351 to thatcher. Change-Id: I33e7ad0cad2ae06f5934c60939d60a18444aa24e Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/thatcher/BiosCallOuts.c | 12 ++++++++++++ src/mainboard/amd/thatcher/BiosCallOuts.h | 2 ++ 2 files changed, 14 insertions(+), 0 deletions(-) diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index 34936e0..8660e05 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -25,6 +25,7 @@ #include "OptionsIds.h" #include "heapManager.h" #include "FchPlatform.h" +#include "cbfs.h" STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = { @@ -71,6 +72,9 @@ STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, + BiosHookGfxGetVbiosImage + } }; AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) @@ -735,3 +739,11 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) return AGESA_SUCCESS; } + +AGESA_STATUS BiosHookGfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt) +{ + GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt; + pVbiosImageInfo->ImagePtr = cbfs_find_file("pci"CONFIG_VGA_BIOS_ID".rom", CBFS_TYPE_OPTIONROM); + /* printk(BIOS_DEBUG, "IMGptr=%x\n", pVbiosImageInfo->ImagePtr); */ + return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS; +} diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.h b/src/mainboard/amd/thatcher/BiosCallOuts.h index 1993c64..b7b9eaf 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.h +++ b/src/mainboard/amd/thatcher/BiosCallOuts.h @@ -71,6 +71,8 @@ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *Conf AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* FCH OEM Config*/ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); +/* Get Vbios Image */ +AGESA_STATUS BiosHookGfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt); #define SB_GPIO_REG02 2 #define SB_GPIO_REG09 9 #define SB_GPIO_REG10 10

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Patch set updated for coreboot: 1cd3013 AMD SB: Call the rtc update if needed (Propagation)
by Zheng Bao 04 Aug '12

04 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1406 -gerrit commit 1cd30138b5c836448b7c2b63549b0e919655904a Author: zbao <fishbaozi(a)gmail.com> Date: Fri Aug 3 16:58:53 2012 +0800 AMD SB: Call the rtc update if needed (Propagation) Apply the change http://review.coreboot.org/1390 to all the AMD southbridge. Change-Id: I8e94014f8883a0408b68355d9aa33aea4373881f Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/southbridge/amd/cimx/sb700/late.c | 12 +++++++++++- src/southbridge/amd/cimx/sb800/late.c | 12 +++++++++++- src/southbridge/amd/cimx/sb900/late.c | 3 +++ src/southbridge/amd/sb600/lpc.c | 1 + src/southbridge/amd/sb700/lpc.c | 2 ++ src/southbridge/amd/sb800/lpc.c | 2 ++ 6 files changed, 30 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c index 4e51e0a..be2b8cd 100644 --- a/src/southbridge/amd/cimx/sb700/late.c +++ b/src/southbridge/amd/cimx/sb700/late.c @@ -23,6 +23,7 @@ #include <device/pci_ids.h> #include <arch/ioapic.h> #include <device/smbus.h> /* smbus_bus_operations */ +#include <pc80/mc146818rtc.h> #include <console/console.h> /* printk */ #include "lpc.h" /* lpc_read_resources */ #include "Platform.h" /* Platfrom Specific Definitions */ @@ -72,11 +73,20 @@ static void lpc_enable_resources(device_t dev) printk(BIOS_SPEW, "SB700 - Late.c - %s - End.\n", __func__); } +static void lpc_init(device_t dev) +{ + printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - Start.\n"); + + rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); + + printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - End.\n"); +} + static struct device_operations lpc_ops = { .read_resources = lpc_read_resources, .set_resources = lpc_set_resources, .enable_resources = lpc_enable_resources, - .init = 0, + .init = lpc_init, .scan_bus = scan_static_bus, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 0ce82b3..7286a6d 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -23,6 +23,7 @@ #include <device/pci_ids.h> #include <arch/ioapic.h> #include <device/smbus.h> /* smbus_bus_operations */ +#include <pc80/mc146818rtc.h> #include <console/console.h> /* printk */ #include <arch/acpi.h> #include "lpc.h" /* lpc_read_resources */ @@ -120,11 +121,20 @@ static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; +static void lpc_init(device_t dev) +{ + printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n"); + + rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); + + printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n"); +} + static struct device_operations lpc_ops = { .read_resources = lpc_read_resources, .set_resources = lpc_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, + .init = lpc_init, .scan_bus = scan_static_bus, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index 71c65e3..85485ed 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -22,6 +22,7 @@ #include <device/pci.h> /* device_operations */ #include <device/pci_ids.h> #include <device/smbus.h> /* smbus_bus_operations */ +#include <pc80/mc146818rtc.h> #include <console/console.h> /* printk */ #include "lpc.h" /* lpc_read_resources */ #include "SbPlatform.h" /* Platfrom Specific Definitions */ @@ -98,6 +99,8 @@ static void lpc_init(device_t dev) printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - Start.\n"); /* SB Configure HPET base and enable bit */ //- hpetInit(sb_config, &(sb_config->BuildParameters)); + rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); + printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - End.\n"); } diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c index 6f16ea8..22945a7 100644 --- a/src/southbridge/amd/sb600/lpc.c +++ b/src/southbridge/amd/sb600/lpc.c @@ -60,6 +60,7 @@ static void lpc_init(device_t dev) byte &= ~(1 << 1); pci_write_config8(dev, 0x78, byte); + rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); } static void sb600_lpc_read_resources(device_t dev) diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index c968927..be940e3 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -81,6 +81,8 @@ static void lpc_init(device_t dev) printk(BIOS_DEBUG, "SLP_TYP type was %x\n", acpi_slp_type); } #endif + + rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); } void set_cbmem_toc(struct cbmem_entry *toc) diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 4e2031f..3cb0789 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -67,6 +67,8 @@ static void lpc_init(device_t dev) byte = pci_read_config8(dev, 0xBB); byte |= 1 << 0 | 1 << 3; pci_write_config8(dev, 0xBB, byte); + + rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); } static void sb800_lpc_read_resources(device_t dev)

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Patch merged into coreboot/master: 5c663a9 Perform additional programming requirements for SATA
by gerrit＠coreboot.org 04 Aug '12

04 Aug '12

the following patch was just integrated into master: commit 5c663a9caa0c310687919dbaa6299d150ef89742 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 17 16:42:51 2012 -0700 Perform additional programming requirements for SATA In accordance to PCH EDS 14.1.35.1 Change-Id: I2e6cec6d4f49f404e33a171a8fbd6e4880327896 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Sat Aug 4 01:50:26 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sat Aug 4 18:06:37 2012, giving +2 See http://review.coreboot.org/1411 for details. -gerrit

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Patch merged into coreboot/master: 3bf9ed1 Make the device tree available in the rom stage
by gerrit＠coreboot.org 04 Aug '12

04 Aug '12

the following patch was just integrated into master: commit 3bf9ed165efd91cb8d51e42e71528c140b4caf15 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 31 16:47:25 2012 -0700 Make the device tree available in the rom stage We thought about two ways to do this change. The way we decided to try was to 1. drop all ops from devices in romstage 2. constify all devices in romstage (make them read-only) so we can compile static.c into romstage 3. the device tree "devices" can be used to read configuration from the device tree (and nothing else, really) 4. the device tree devices are accessed through struct device * in romstage only. device_t stays the typedef to int in romstage 5. Use the same static.c file in ramstage and romstage We declare structs as follows: ROMSTAGE_CONST struct bus dev_root_links[]; ROMSTAGE_CONST is const in romstage and empty in ramstage; This forces all of the device tree into the text area. So a struct looks like this: static ROMSTAGE_CONST struct device _dev21 = { #ifndef __PRE_RAM__ .ops = 0, #endif .bus = &_dev7_links[0], .path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}}, .enabled = 0, .on_mainboard = 1, .subsystem_vendor = 0x1ae0, .subsystem_device = 0xc000, .link_list = NULL, .sibling = &_dev22, #ifndef __PRE_RAM__ .chip_ops = &southbridge_intel_bd82x6x_ops, #endif .chip_info = &southbridge_intel_bd82x6x_info_10, .next=&_dev22 }; Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727 Signed-off-by: Ronald G. Minnich <rminnich(a)chromium.org> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Sat Aug 4 00:06:15 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sat Aug 4 18:05:34 2012, giving +2 See http://review.coreboot.org/1398 for details. -gerrit

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Patch merged into coreboot/master: 1400723 AMD f15 nb: Remove the misleading 0x100 from the limitk (Propagation)
by gerrit＠coreboot.org 04 Aug '12

04 Aug '12

the following patch was just integrated into master: commit 14007235fe60e386584d75148ae9c65cabcae577 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Aug 3 15:56:21 2012 +0800 AMD f15 nb: Remove the misleading 0x100 from the limitk (Propagation) Apply the change http://review.coreboot.org/1265 to all the AMD northbridge. Change-Id: Idf3994c1e9ec76cd19db9f740d825cf24059884f Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Aug 3 08:44:28 2012, giving +1 See http://review.coreboot.org/1404 for details. -gerrit

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Patch merged into coreboot/master: cbe5a5b AMD NB: Limit the device field to 5 bits. (Propagation)
by gerrit＠coreboot.org 04 Aug '12

04 Aug '12

the following patch was just integrated into master: commit cbe5a5b90010158d78913f83817390e332894eae Author: zbao <fishbaozi(a)gmail.com> Date: Fri Aug 3 15:44:42 2012 +0800 AMD NB: Limit the device field to 5 bits. (Propagation) Apply the change http://review.coreboot.org/1264 to all the AMD northbridge. Change-Id: Ied74d6f579d2c0350288e2619d7810f8d44fa574 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Aug 3 08:28:06 2012, giving +1 See http://review.coreboot.org/1403 for details. -gerrit

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Patch merged into coreboot/master: 8452211 SuperIO LPC47N217: Remove warnings
by gerrit＠coreboot.org 04 Aug '12

04 Aug '12

the following patch was just integrated into master: commit 8452211aaea71a5b01b22708fa606e653f336d11 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Aug 3 15:09:09 2012 +0800 SuperIO LPC47N217: Remove warnings Change-Id: Id5756f1bb748ae7bec0bcdc21804f5338e850baa Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Aug 3 08:12:07 2012, giving +1 See http://review.coreboot.org/1402 for details. -gerrit

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Patch merged into coreboot/master: 6c493d7 AMD Parmer: Remove warning.
by gerrit＠coreboot.org 04 Aug '12

04 Aug '12

the following patch was just integrated into master: commit 6c493d7bf800fa4e295465f28f8813477121f917 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Aug 3 11:47:53 2012 +0800 AMD Parmer: Remove warning. Change-Id: I4ba2d480fa6df5ee741d887d26524b32c1901d73 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Aug 3 04:28:05 2012, giving +1 See http://review.coreboot.org/1399 for details. -gerrit

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New patch to review for coreboot: 26538f0 Sandy/Ivy Bridge and Cougar/Panther Point: Fix names
by Stefan Reinauer 04 Aug '12

04 Aug '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1413 -gerrit commit 26538f0559a2ab70b085029441fc421ea3aec607 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jul 25 16:10:36 2012 -0700 Sandy/Ivy Bridge and Cougar/Panther Point: Fix names The names were set at various times during development, but the way the code works, you might end up with the wrong name being displayed in the logs. Instead of doing magic, just display both names for each component Change-Id: I1f8ce44d156442f5f7d717e1a2b47ed1218d4527 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/northbridge/intel/sandybridge/northbridge.c | 2 +- src/southbridge/intel/bd82x6x/Kconfig | 12 ------------ src/southbridge/intel/bd82x6x/pch.c | 2 +- 3 files changed, 2 insertions(+), 14 deletions(-) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index b447d52..fb0b4cb 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -511,6 +511,6 @@ static void enable_dev(device_t dev) } struct chip_operations northbridge_intel_sandybridge_ops = { - CHIP_NAME("Intel i7 (Sandybridge) integrated Northbridge") + CHIP_NAME("Intel i7 (SandyBridge/IvyBridge) integrated Northbridge") .enable_dev = enable_dev, }; diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 33dfe9d..a7d41dc 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -56,15 +56,3 @@ config SERIRQ_CONTINUOUS_MODE operated in continuous mode. endif - -if SOUTHBRIDGE_INTEL_BD82X6X -config PCH_CHIP_NAME - string - default "Cougar Point" -endif - -if SOUTHBRIDGE_INTEL_C216 -config PCH_CHIP_NAME - string - default "Panther Point" -endif diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 3c448de..d8a919d 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -405,6 +405,6 @@ void pch_enable(device_t dev) } struct chip_operations southbridge_intel_bd82x6x_ops = { - CHIP_NAME("Intel Series 6/7 (" CONFIG_PCH_CHIP_NAME ") Southbridge") + CHIP_NAME("Intel Series 6/7 (Cougar Point/Panther Point) Southbridge") .enable_dev = pch_enable, };

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New patch to review for coreboot: 1829cdf Sandybridge: Fix integer overrun in romstage udelay()
by Stefan Reinauer 04 Aug '12

04 Aug '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1412 -gerrit commit 1829cdfcb84662a78320b1979cb6e3b3ec2f28f6 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jul 25 16:15:25 2012 -0700 Sandybridge: Fix integer overrun in romstage udelay() This was broken, fixing according to related patch for i945 Change-Id: I925cd205ee5beb918181740a7b981a4209688ac6 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/northbridge/intel/sandybridge/udelay.c | 20 ++++++++++++++------ 1 files changed, 14 insertions(+), 6 deletions(-) diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c index 3d8ba96..2e795c7 100644 --- a/src/northbridge/intel/sandybridge/udelay.c +++ b/src/northbridge/intel/sandybridge/udelay.c @@ -23,9 +23,20 @@ #include <cpu/x86/msr.h> /** - * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock + * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz */ +/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ +static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) +{ + tsc->lo = (a & 0xffff) * (b & 0xffff); + tsc->hi = ((tsc->lo >> 16) + + ((a & 0xffff) * (b >> 16)) + + ((b & 0xffff) * (a >> 16))); + tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); + tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); +} + void udelay(u32 us) { u32 dword; @@ -33,15 +44,12 @@ void udelay(u32 us) msr_t msr; u32 fsb = 100, divisor; u32 d; /* ticks per us */ - u32 dn = 0x1000000 / 2; /* how many us before we need to use hi */ msr = rdmsr(0xce); divisor = (msr.lo >> 8) & 0xff; - d = fsb * divisor; - - tscd.hi = us / dn; - tscd.lo = (us - tscd.hi * dn) * d; + d = fsb * divisor; /* On Core/Core2 this is divided by 4 */ + multiply_to_tsc(&tscd, us, d); tsc1 = rdtsc(); dword = tsc1.lo + tscd.lo;

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coreboot August 2012