coreboot August 2012

coreboot@coreboot.org

30 participants
321 discussions

git push by http failed.
by Bao, Zheng 20 Aug '12

20 Aug '12

Hi, All, If I run git push, it says, $ git push Counting objects: 9, done. Delta compression using up to 4 threads. Compressing objects: 100% (5/5), done. Writing objects: 100% (5/5), 499 bytes, done. Total 5 (delta 4), reused 0 (delta 0) error: RPC failed; result=22, HTTP code = 500 fatal: The remote end hung up unexpectedly fatal: The remote end hung up unexpectedly what is the problem? Zheng

2 1

Patch merged into coreboot/master: 0ca02ce Don't write automatic IRQ entries for disabled devices
by gerrit＠coreboot.org 20 Aug '12

20 Aug '12

the following patch was just integrated into master: commit 0ca02ce984d68af3182cca8e520f7e45efe74708 Author: Sven Schnelle <svens(a)stackframe.org> Date: Mon Aug 20 11:17:52 2012 +0200 Don't write automatic IRQ entries for disabled devices Change-Id: Ib3dae4f0957a2e0057c0dffb5eb9904af20dcd40 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Mon Aug 20 12:11:59 2012, giving +1 Reviewed-By: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> at Mon Aug 20 19:40:39 2012, giving +2 See http://review.coreboot.org/1460 for details. -gerrit

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New patch to review for coreboot: 0293ae0 bd82x6x: remove ioapic initialization
by Sven Schnelle 20 Aug '12

20 Aug '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1463 -gerrit commit 0293ae0ceabcf4003400500e7a15ebc02ba712be Author: Sven Schnelle <svens(a)stackframe.org> Date: Mon Aug 20 11:22:37 2012 +0200 bd82x6x: remove ioapic initialization This now done by the generic ioapic driver. Change-Id: Iea648158c429ee5b053c7b3f3cdfcfaecb4eb4c3 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/southbridge/intel/bd82x6x/lpc.c | 49 ++----------------------------------- 1 file changed, 2 insertions(+), 47 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 592f5de..3a6140f 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -26,7 +26,6 @@ #include <pc80/isa-dma.h> #include <pc80/i8259.h> #include <arch/io.h> -#include <arch/ioapic.h> #include <arch/acpi.h> #include <cpu/cpu.h> #include <elog.h> @@ -39,45 +38,6 @@ typedef struct southbridge_intel_bd82x6x_config config_t; -static void pch_enable_apic(struct device *dev) -{ - int i; - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ - pci_write_config8(dev, ACPI_CNTL, 0x80); - - *ioapic_index = 0; - *ioapic_data = (1 << 25); - - /* affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - *ioapic_index = 1; - *ioapic_data = reg32; - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } - - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ -} - static void pch_enable_serial_irqs(struct device *dev) { /* Set packet length and toggle silent mode bit for one frame. */ @@ -537,8 +497,8 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); - /* IO APIC initialization. */ - pch_enable_apic(dev); + /* enable ACPI */ + pci_write_config8(dev, ACPI_CNTL, 0x80); pch_enable_serial_irqs(dev); @@ -612,11 +572,6 @@ static void pch_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - /* Set PCH IO decode ranges if required.*/ if ((config->gen1_dec & 0xFFFC) > 0x1000) { res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));

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Patch set updated for coreboot: 81dd2fa LUMPY: Add information to generate MPTABLE from devicetree.cb
by Sven Schnelle 20 Aug '12

20 Aug '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1462 -gerrit commit 81dd2fa439e2937021343829b5dd9d4342d39e8e Author: Sven Schnelle <svens(a)stackframe.org> Date: Mon Aug 20 11:21:00 2012 +0200 LUMPY: Add information to generate MPTABLE from devicetree.cb Change-Id: If68888e87c5197328c59dafce1301eefe000e28e Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/samsung/lumpy/Kconfig | 2 ++ src/mainboard/samsung/lumpy/devicetree.cb | 37 ++++++++++++++++++++++++++----- 2 files changed, 33 insertions(+), 6 deletions(-) diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 86cb31b..5bc3a3e 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -12,12 +12,14 @@ config BOARD_SPECIFIC_OPTIONS # dummy select GFXUMA select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select HAVE_MP_TABLE select HAVE_OPTION_TABLE select HAVE_SMI_HANDLER select MMCONF_SUPPORT select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_SMSC_MEC1308 + select DRIVERS_GENERIC_IOAPIC config MAINBOARD_DIR string diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 3e93df4..7a2ee6c 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -33,6 +33,10 @@ chip northbridge/intel/sandybridge end device pci_domain 0 on + ioapic_irq 4 INTA 0x10 + ioapic_irq 4 INTB 0x11 + ioapic_irq 4 INTC 0x12 + ioapic_irq 4 INTD 0x13 subsystemid 0x1ae0 0xc000 inherit device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller @@ -68,19 +72,28 @@ chip northbridge/intel/sandybridge device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio + device pci 1a.0 on # USB2 EHCI #2 + ioapic_irq 4 INTA 0x11 + end + device pci 1b.0 on # High Definition Audio + ioapic_irq 4 INTA 0x16 + end device pci 1c.0 on end # PCIe Port #1 (WLAN) device pci 1c.1 off end # PCIe Port #2 device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 (LAN) + device pci 1c.3 on # PCIe Port #4 (LAN) + # ioapic_irq 4 INTA 0x13 + end device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 device pci 1c.6 off end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 + device pci 1d.0 on # USB2 EHCI #1 + ioapic_irq 4 INTA 0x13 + end device pci 1e.0 off end # PCI bridge device pci 1f.0 on # LPC bridge + ioapic_irq 4 INTA 0x10 chip superio/smsc/mec1308 device pnp 2e.1 on # PM1 io 0x60 = 0xb00 @@ -102,9 +115,21 @@ chip northbridge/intel/sandybridge register "mailbox_port" = "0xa00" device pnp ff.1 off end end + + chip drivers/generic/ioapic + register "have_isa_interrupts" = "1" + register "irq_on_fsb" = "1" + register "enable_virtual_wire" = "1" + register "base" = "0xfec00000" + device ioapic 4 on end + end + end + device pci 1f.2 on # SATA Controller 1 + ioapic_irq 4 INTA 0x10 + end + device pci 1f.3 on # SMBus + ioapic_irq 4 INTC 0x17 end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus device pci 1f.5 off end # SATA Controller 2 device pci 1f.6 on end # Thermal end

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New patch to review for coreboot: 95240d0 LUMPY: Add information to generate MPTABLE from devicetree.cb
by Sven Schnelle 20 Aug '12

20 Aug '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1462 -gerrit commit 95240d0c3a22d3323112941f24c8e381126daa94 Author: Sven Schnelle <svens(a)stackframe.org> Date: Mon Aug 20 11:21:00 2012 +0200 LUMPY: Add information to generate MPTABLE from devicetree.cb Change-Id: If68888e87c5197328c59dafce1301eefe000e28e Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/samsung/lumpy/devicetree.cb | 37 ++++++++++++++++++++++++++----- 1 file changed, 31 insertions(+), 6 deletions(-) diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 3e93df4..7a2ee6c 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -33,6 +33,10 @@ chip northbridge/intel/sandybridge end device pci_domain 0 on + ioapic_irq 4 INTA 0x10 + ioapic_irq 4 INTB 0x11 + ioapic_irq 4 INTC 0x12 + ioapic_irq 4 INTD 0x13 subsystemid 0x1ae0 0xc000 inherit device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller @@ -68,19 +72,28 @@ chip northbridge/intel/sandybridge device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio + device pci 1a.0 on # USB2 EHCI #2 + ioapic_irq 4 INTA 0x11 + end + device pci 1b.0 on # High Definition Audio + ioapic_irq 4 INTA 0x16 + end device pci 1c.0 on end # PCIe Port #1 (WLAN) device pci 1c.1 off end # PCIe Port #2 device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 (LAN) + device pci 1c.3 on # PCIe Port #4 (LAN) + # ioapic_irq 4 INTA 0x13 + end device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 device pci 1c.6 off end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 + device pci 1d.0 on # USB2 EHCI #1 + ioapic_irq 4 INTA 0x13 + end device pci 1e.0 off end # PCI bridge device pci 1f.0 on # LPC bridge + ioapic_irq 4 INTA 0x10 chip superio/smsc/mec1308 device pnp 2e.1 on # PM1 io 0x60 = 0xb00 @@ -102,9 +115,21 @@ chip northbridge/intel/sandybridge register "mailbox_port" = "0xa00" device pnp ff.1 off end end + + chip drivers/generic/ioapic + register "have_isa_interrupts" = "1" + register "irq_on_fsb" = "1" + register "enable_virtual_wire" = "1" + register "base" = "0xfec00000" + device ioapic 4 on end + end + end + device pci 1f.2 on # SATA Controller 1 + ioapic_irq 4 INTA 0x10 + end + device pci 1f.3 on # SMBus + ioapic_irq 4 INTC 0x17 end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus device pci 1f.5 off end # SATA Controller 2 device pci 1f.6 on end # Thermal end

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New patch to review for coreboot: f15b669 MPTABLE: check for fixed IRQ entries on all pins
by Sven Schnelle 20 Aug '12

20 Aug '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1461 -gerrit commit f15b66959c5b42857e710cb20130c50003975cfa Author: Sven Schnelle <svens(a)stackframe.org> Date: Mon Aug 20 11:19:00 2012 +0200 MPTABLE: check for fixed IRQ entries on all pins Don't derive the IRQ pin from the function number. Especially onboard chipset devices don't follow that rule. Instead check and add all fixed IRQ entries. Change-Id: I46c88bad39104c1d9b4154f180f8b3c42df28262 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/arch/x86/boot/mpspec.c | 89 ++++++++++++++++++++++++---------------------- 1 file changed, 47 insertions(+), 42 deletions(-) diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c index 010bca1..1f583fd 100644 --- a/src/arch/x86/boot/mpspec.c +++ b/src/arch/x86/boot/mpspec.c @@ -419,7 +419,7 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) int isa_bus, pin, parentpin; device_t dev, parent, oldparent; void *tmp, *v; - int isaioapic = -1; + int isaioapic = -1, have_fixed_entries; v = smp_write_floating_table(addr, 0); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -461,48 +461,53 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) if (dev->path.type != DEVICE_PATH_PCI || !dev->enabled) continue; - pin = (dev->path.pci.devfn & 7) % 4; - - if (dev->pci_irq_info[pin].ioapic_dst_id) { - printk(BIOS_DEBUG, "fixed IRQ entry for: %s: INT%c# -> IOAPIC %d PIN %d\n", dev_path(dev), - pin + 'A', - dev->pci_irq_info[pin].ioapic_dst_id, - dev->pci_irq_info[pin].ioapic_irq_pin); - smp_write_intsrc(mc, mp_INT, - dev->pci_irq_info[pin].ioapic_flags, - dev->bus->secondary, - ((dev->path.pci.devfn & 0xf8) >> 1) | pin, - dev->pci_irq_info[pin].ioapic_dst_id, - dev->pci_irq_info[pin].ioapic_irq_pin); - } else { - oldparent = parent = dev; - while((parent = parent->bus->dev)) { - parentpin = (oldparent->path.pci.devfn >> 3) + (oldparent->path.pci.devfn & 7); - parentpin += dev->path.pci.devfn & 7; - parentpin += dev->path.pci.devfn >> 3; - parentpin %= 4; - - if (parent->pci_irq_info[parentpin].ioapic_dst_id) { - printk(BIOS_DEBUG, "automatic IRQ entry for %s: INT%c# -> IOAPIC %d PIN %d\n", - dev_path(dev), pin + 'A', - parent->pci_irq_info[parentpin].ioapic_dst_id, - parent->pci_irq_info[parentpin].ioapic_irq_pin); - smp_write_intsrc(mc, mp_INT, - parent->pci_irq_info[parentpin].ioapic_flags, - dev->bus->secondary, - ((dev->path.pci.devfn & 0xf8) >> 1) | pin, - parent->pci_irq_info[parentpin].ioapic_dst_id, - parent->pci_irq_info[parentpin].ioapic_irq_pin); - - break; - } - - if (parent->path.type == DEVICE_PATH_PCI_DOMAIN) { - printk(BIOS_WARNING, "no IRQ found for %s\n", dev_path(dev)); - break; - } - oldparent = parent; + have_fixed_entries = 0; + for (pin = 0; pin < 4; pin++) { + if (dev->pci_irq_info[pin].ioapic_dst_id) { + printk(BIOS_DEBUG, "fixed IRQ entry for: %s: INT%c# -> IOAPIC %d PIN %d\n", dev_path(dev), + pin + 'A', + dev->pci_irq_info[pin].ioapic_dst_id, + dev->pci_irq_info[pin].ioapic_irq_pin); + smp_write_intsrc(mc, mp_INT, + dev->pci_irq_info[pin].ioapic_flags, + dev->bus->secondary, + ((dev->path.pci.devfn & 0xf8) >> 1) | pin, + dev->pci_irq_info[pin].ioapic_dst_id, + dev->pci_irq_info[pin].ioapic_irq_pin); + have_fixed_entries = 1; + } + } + + if (!have_fixed_entries) { + pin = (dev->path.pci.devfn & 7) % 4; + oldparent = parent = dev; + while((parent = parent->bus->dev)) { + parentpin = (oldparent->path.pci.devfn >> 3) + (oldparent->path.pci.devfn & 7); + parentpin += dev->path.pci.devfn & 7; + parentpin += dev->path.pci.devfn >> 3; + parentpin %= 4; + + if (parent->pci_irq_info[parentpin].ioapic_dst_id) { + printk(BIOS_DEBUG, "automatic IRQ entry for %s: INT%c# -> IOAPIC %d PIN %d\n", + dev_path(dev), pin + 'A', + parent->pci_irq_info[parentpin].ioapic_dst_id, + parent->pci_irq_info[parentpin].ioapic_irq_pin); + smp_write_intsrc(mc, mp_INT, + parent->pci_irq_info[parentpin].ioapic_flags, + dev->bus->secondary, + ((dev->path.pci.devfn & 0xf8) >> 1) | pin, + parent->pci_irq_info[parentpin].ioapic_dst_id, + parent->pci_irq_info[parentpin].ioapic_irq_pin); + + break; } + + if (parent->path.type == DEVICE_PATH_PCI_DOMAIN) { + printk(BIOS_WARNING, "no IRQ found for %s\n", dev_path(dev)); + break; + } + oldparent = parent; + } } }

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Patch set updated for coreboot: 0ca02ce Don't write automatic IRQ entries for disabled devices
by Sven Schnelle 20 Aug '12

20 Aug '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1460 -gerrit commit 0ca02ce984d68af3182cca8e520f7e45efe74708 Author: Sven Schnelle <svens(a)stackframe.org> Date: Mon Aug 20 11:17:52 2012 +0200 Don't write automatic IRQ entries for disabled devices Change-Id: Ib3dae4f0957a2e0057c0dffb5eb9904af20dcd40 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/arch/x86/boot/mpspec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c index 44236f1..010bca1 100644 --- a/src/arch/x86/boot/mpspec.c +++ b/src/arch/x86/boot/mpspec.c @@ -458,7 +458,7 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) for(dev = all_devices; dev; dev = dev->next) { - if (dev->path.type != DEVICE_PATH_PCI) + if (dev->path.type != DEVICE_PATH_PCI || !dev->enabled) continue; pin = (dev->path.pci.devfn & 7) % 4;

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New patch to review for coreboot: 59107b0 Don't write automatic IRQ entries for disabled devices
by Sven Schnelle 20 Aug '12

20 Aug '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1460 -gerrit commit 59107b09138a8fe003835edcdd6aca5d9b422ae9 Author: Sven Schnelle <svens(a)stackframe.org> Date: Mon Aug 20 11:12:27 2012 +0200 Don't write automatic IRQ entries for disabled devices Change-Id: Ib3dae4f0957a2e0057c0dffb5eb9904af20dcd40 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/arch/x86/boot/mpspec.c | 91 ++++++++++++++++++++++++---------------------- 1 file changed, 48 insertions(+), 43 deletions(-) diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c index 44236f1..1f583fd 100644 --- a/src/arch/x86/boot/mpspec.c +++ b/src/arch/x86/boot/mpspec.c @@ -419,7 +419,7 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) int isa_bus, pin, parentpin; device_t dev, parent, oldparent; void *tmp, *v; - int isaioapic = -1; + int isaioapic = -1, have_fixed_entries; v = smp_write_floating_table(addr, 0); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -458,51 +458,56 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) for(dev = all_devices; dev; dev = dev->next) { - if (dev->path.type != DEVICE_PATH_PCI) + if (dev->path.type != DEVICE_PATH_PCI || !dev->enabled) continue; - pin = (dev->path.pci.devfn & 7) % 4; - - if (dev->pci_irq_info[pin].ioapic_dst_id) { - printk(BIOS_DEBUG, "fixed IRQ entry for: %s: INT%c# -> IOAPIC %d PIN %d\n", dev_path(dev), - pin + 'A', - dev->pci_irq_info[pin].ioapic_dst_id, - dev->pci_irq_info[pin].ioapic_irq_pin); - smp_write_intsrc(mc, mp_INT, - dev->pci_irq_info[pin].ioapic_flags, - dev->bus->secondary, - ((dev->path.pci.devfn & 0xf8) >> 1) | pin, - dev->pci_irq_info[pin].ioapic_dst_id, - dev->pci_irq_info[pin].ioapic_irq_pin); - } else { - oldparent = parent = dev; - while((parent = parent->bus->dev)) { - parentpin = (oldparent->path.pci.devfn >> 3) + (oldparent->path.pci.devfn & 7); - parentpin += dev->path.pci.devfn & 7; - parentpin += dev->path.pci.devfn >> 3; - parentpin %= 4; - - if (parent->pci_irq_info[parentpin].ioapic_dst_id) { - printk(BIOS_DEBUG, "automatic IRQ entry for %s: INT%c# -> IOAPIC %d PIN %d\n", - dev_path(dev), pin + 'A', - parent->pci_irq_info[parentpin].ioapic_dst_id, - parent->pci_irq_info[parentpin].ioapic_irq_pin); - smp_write_intsrc(mc, mp_INT, - parent->pci_irq_info[parentpin].ioapic_flags, - dev->bus->secondary, - ((dev->path.pci.devfn & 0xf8) >> 1) | pin, - parent->pci_irq_info[parentpin].ioapic_dst_id, - parent->pci_irq_info[parentpin].ioapic_irq_pin); - - break; - } - - if (parent->path.type == DEVICE_PATH_PCI_DOMAIN) { - printk(BIOS_WARNING, "no IRQ found for %s\n", dev_path(dev)); - break; - } - oldparent = parent; + have_fixed_entries = 0; + for (pin = 0; pin < 4; pin++) { + if (dev->pci_irq_info[pin].ioapic_dst_id) { + printk(BIOS_DEBUG, "fixed IRQ entry for: %s: INT%c# -> IOAPIC %d PIN %d\n", dev_path(dev), + pin + 'A', + dev->pci_irq_info[pin].ioapic_dst_id, + dev->pci_irq_info[pin].ioapic_irq_pin); + smp_write_intsrc(mc, mp_INT, + dev->pci_irq_info[pin].ioapic_flags, + dev->bus->secondary, + ((dev->path.pci.devfn & 0xf8) >> 1) | pin, + dev->pci_irq_info[pin].ioapic_dst_id, + dev->pci_irq_info[pin].ioapic_irq_pin); + have_fixed_entries = 1; + } + } + + if (!have_fixed_entries) { + pin = (dev->path.pci.devfn & 7) % 4; + oldparent = parent = dev; + while((parent = parent->bus->dev)) { + parentpin = (oldparent->path.pci.devfn >> 3) + (oldparent->path.pci.devfn & 7); + parentpin += dev->path.pci.devfn & 7; + parentpin += dev->path.pci.devfn >> 3; + parentpin %= 4; + + if (parent->pci_irq_info[parentpin].ioapic_dst_id) { + printk(BIOS_DEBUG, "automatic IRQ entry for %s: INT%c# -> IOAPIC %d PIN %d\n", + dev_path(dev), pin + 'A', + parent->pci_irq_info[parentpin].ioapic_dst_id, + parent->pci_irq_info[parentpin].ioapic_irq_pin); + smp_write_intsrc(mc, mp_INT, + parent->pci_irq_info[parentpin].ioapic_flags, + dev->bus->secondary, + ((dev->path.pci.devfn & 0xf8) >> 1) | pin, + parent->pci_irq_info[parentpin].ioapic_dst_id, + parent->pci_irq_info[parentpin].ioapic_irq_pin); + + break; } + + if (parent->path.type == DEVICE_PATH_PCI_DOMAIN) { + printk(BIOS_WARNING, "no IRQ found for %s\n", dev_path(dev)); + break; + } + oldparent = parent; + } } }

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Patch set updated for coreboot: f150a15 AMD Hudson: Move the combining firmware from Python to sh.
by Zheng Bao 17 Aug '12

17 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1417 -gerrit commit f150a1500a3919eef7cf33df9a0f61cf889cd86a Author: zbao <fishbaozi(a)gmail.com> Date: Fri Aug 17 18:21:37 2012 +0800 AMD Hudson: Move the combining firmware from Python to sh. Maybe sooner or later python is not a default tools to build coreboot. Most of the work is done by awk now. GNU extension of gawk is not used, isn't? printf, cat, awk, test, mv are the external tools. If XHCI, IMC or GEC firmware is not available and not defined, this script can skip integrating them. Change-Id: I9944b22b0b755672a46d472c355d138abafd6393 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/southbridge/amd/agesa/hudson/Makefile.inc | 7 ++- src/southbridge/amd/agesa/hudson/hudson_fwm.py | 64 ---------------------- src/southbridge/amd/agesa/hudson/hudson_fwm.sh | 74 ++++++++++++++++++++++++++ 3 files changed, 79 insertions(+), 66 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 19ffae1..1642ba2 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -14,8 +14,11 @@ romstage-y += early_setup.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c -$(obj)/hudson.bin: - python $(src)/southbridge/amd/agesa/hudson/hudson_fwm.py $(CONFIG_HUDSON_FWM_POSITION) $@ $(CONFIG_HUDSON_XHCI_FWM_FILE) $(CONFIG_HUDSON_IMC_FWM_FILE) "" +$(obj)/hudson.bin: $(top)/$(strip $(patsubst "%", %, $(CONFIG_HUDSON_XHCI_FWM_FILE))) \ + $(top)/$(strip $(patsubst "%", %, $(CONFIG_HUDSON_IMC_FWM_FILE))) \ + $(top)/$(strip $(patsubst "%", %, $(CONFIG_HUDSON_GEC_FWM_FILE))) + echo " Hudson FW $@" + $(src)/southbridge/amd/agesa/hudson/hudson_fwm.sh $(CONFIG_HUDSON_FWM_POSITION) $@ $(CONFIG_HUDSON_XHCI_FWM_FILE) $(CONFIG_HUDSON_IMC_FWM_FILE) $(CONFIG_HUDSON_GEC_FWM_FILE) ifeq ($(CONFIG_HUDSON_FWM), y) cbfs-files-y += hudson/fwm diff --git a/src/southbridge/amd/agesa/hudson/hudson_fwm.py b/src/southbridge/amd/agesa/hudson/hudson_fwm.py deleted file mode 100644 index ad60b3b..0000000 --- a/src/southbridge/amd/agesa/hudson/hudson_fwm.py +++ /dev/null @@ -1,64 +0,0 @@ -import sys, os, re -import struct -from Queue import Queue - -def main(start_addr, file_name, xhci_name, imc_name, gec_name): - fwm_sig = 0x55AA55AA # Hudson-2/3/4 firmware signature - fwm_header_len = 0x10 # 55AA55AA, imc_off, gec_off, xhci_off - - if not os.path.exists(xhci_name): - print "XHCI firmware %s does not exist\n" % xhci_name - sys.exit(1) - if not os.path.exists(imc_name): - print "IMC firmware %s does not exist\n" % imc_name - sys.exit(1) - - f = open(file_name, "w") - print "write to file " + file_name - - imc_offset = 0x10000 # 64K Bytes offset, hardcoded - imc_addr = start_addr + imc_offset; #startaddr + 0x10000 - gec_offset = 0 #TODO - gec_addr = 0 #TODO - xhci_addr = start_addr + fwm_header_len #ROMSIG take 0x10 bytes - - format="I" # one unsigned integer - data=struct.pack(format, fwm_sig) - f.write(data) - data=struct.pack(format, imc_addr) - f.write(data) - data=struct.pack(format, gec_addr) - f.write(data) - data=struct.pack(format, xhci_addr) - f.write(data) - - fwm_content = open(xhci_name).read() - f.write(fwm_content) - - imc_content = open(imc_name).read() - f.seek(0) - f.seek(imc_offset) - f.write(imc_content) -# if os.path.exists(gec_name): -# gec_conent = open(gec_name).read() -# f.seek(0) -# f.seek(gec_offset) -# f.write(gec_content) - - f.close() - print "done\n" - - -if __name__ == '__main__': - if (len(sys.argv) < 6): - print "\nUsage: %s <rom_addr> <rom_file> <xhci_rom> <imc_rom> <gec_rom>\n" % sys.argv[0] - print "Example: %s 0xFFF20000 hudson.bin xhci.bin imc.bin gec.bin\n" % sys.argv[0] - sys.exit(1) - rom_addr = int(sys.argv[1], 16) - rom_file = sys.argv[2] - xhci_file = sys.argv[3] - imc_file = sys.argv[4] - gec_file = sys.argv[5] - print "%x %s %s %s %s" % (rom_addr, rom_file, xhci_file, imc_file, gec_file) - - main(rom_addr, rom_file, xhci_file, imc_file, gec_file) diff --git a/src/southbridge/amd/agesa/hudson/hudson_fwm.sh b/src/southbridge/amd/agesa/hudson/hudson_fwm.sh new file mode 100755 index 0000000..72e8756 --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/hudson_fwm.sh @@ -0,0 +1,74 @@ +#!/bin/sh + +filesize() +{ + fwm="$1" + if [ -z $fwm ]; then + size=0 + else + [ -r $fwm ] || { echo "$$fwm not found"; exit 1; }; + size=`ls -l $fwm | awk '{print $5}'`; + fi +} + +# ROMSIG At ROMBASE + 0x20000: +# +-----------+---------------+----------------+------------+ +# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | +# +-----------+---------------+----------------+------------+ +# In our coreboot implementation, we concatenate the ROM images +# next to the ROMSIG. EC ROM should be 64K aligned. +# Final hudson.bin: +# +-----------+---------------+----------------+------------+ +# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | +# +-----------+---------------+----------------+------------+ +# | USB3 ROM | +# +---------------------------------------------------------+ +# | GEC ROM | +# +---------------------------------------------------------+ +# | EC ROM | +# +---------------------------------------------------------+ +# +print_romsig() +{ + echo $1 $2 $3 $4 | + LC_ALL=C awk ' + function print_raw_dword(number) + { + #printf ("%x\n", number) + printf ("%c%c%c%c", number % 0x100, number/0x100 % 0x100, number/0x10000 % 0x100, number/0x1000000); + } + { # $1=ROMSIG address, $2=EC_ROM_size, $3=GEC_ROM_size, $4=USB3_ROM_size + print_raw_dword(0x55AA55AA); + imc_offset = $1 + 16 + $3 + 65535; + imc_offset = imc_offset - (imc_offset) % 65536; #align 64K + if ($2) print_raw_dword(imc_offset); else print_raw_dword(0); + if ($3) print_raw_dword($1 + 16 + $3); else print_raw_dword(0); + if ($4) print_raw_dword($1 + 16); else print_raw_dword(0); + } ' +} + +#main +#param: +# $1=$(CONFIG_HUDSON_FWM_POSITION) +# $2=$obj +# $3=$(CONFIG_HUDSON_XHCI_FWM_FILE) +# $4=$(CONFIG_HUDSON_IMC_FWM_FILE) +# $5=$(CONFIG_HUDSON_GEC_FWM_FILE) +base=`printf %d $1` + +filesize $3 +xhci_size=$size +filesize $4 +imc_size=$size +filesize $5 +gec_size=$size + +print_romsig $base $imc_size $gec_size $xhci_size > $2.tmp +[ -z $3 ] || cat $3 >> $2.tmp +[ -z $5 ] || cat $5 >> $2.tmp +if [ ! -z $4 ]; then + ls -l $2.tmp | awk '{ print $5 }' | LC_ALL=C awk '{for (i=$1; i<($1+65535) - ($1+65535)%65536; i++) {printf "%c", 255}}' >> $2.tmp # align 64K + cat $4 >> $2.tmp +fi + +mv $2.tmp $2

1 0

Patch set updated for coreboot: 92e2a6a VIA Nano: Add support for VIA Nano CPUs
by Alexandru Gagniuc 16 Aug '12

16 Aug '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1257 -gerrit commit 92e2a6ad986f819c0562072770145b22dfc0393e Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Aug 7 19:38:32 2012 -0500 VIA Nano: Add support for VIA Nano CPUs Add code to do the following for the VIA Nano CPUs - Update microcode - Set maximum frequency - Initialize power states - Set up cache Attempting to change the voltage or frequency of the CPU without applying the microcode update will hang the CPU, so we only do transitions if we can verify the microcode has been updated. The microcode is updated directly from CBFS. No microcode is included in ramstage. The microcode is not included in this commit. To get the microcode, run bios_extract on the manufacturer supplied BIOS, and look for the file marked "P6 Microcode". Include this file in CBFS. You can have the build system include this file automatically by selecting Expert Mode, then look under 'Chipset' -> 'Include CPU microcode in CBFS' -> Include external microcode file (check) 'Path and filename of CPU microcode' should contain the location of the microcode file previously extracted. Change-Id: I586aaca5715e047b42ef901d66772ace0e6b655e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/via/Kconfig | 1 + src/cpu/via/Makefile.inc | 6 +- src/cpu/via/nano/Kconfig | 41 ++++++++ src/cpu/via/nano/Makefile.inc | 33 +++++++ src/cpu/via/nano/nano_init.c | 204 ++++++++++++++++++++++++++++++++++++++++ src/cpu/via/nano/update_ucode.c | 150 +++++++++++++++++++++++++++++ src/cpu/via/nano/update_ucode.h | 73 ++++++++++++++ 7 files changed, 505 insertions(+), 3 deletions(-) diff --git a/src/cpu/via/Kconfig b/src/cpu/via/Kconfig index 570d408..5c38c91 100644 --- a/src/cpu/via/Kconfig +++ b/src/cpu/via/Kconfig @@ -1,2 +1,3 @@ source src/cpu/via/c3/Kconfig source src/cpu/via/c7/Kconfig +source src/cpu/via/nano/Kconfig diff --git a/src/cpu/via/Makefile.inc b/src/cpu/via/Makefile.inc index 2616111..f1e198d 100644 --- a/src/cpu/via/Makefile.inc +++ b/src/cpu/via/Makefile.inc @@ -1,3 +1,3 @@ -subdirs-$(CONFIG_CPU_VIA_C7) += c7 -subdirs-$(CONFIG_CPU_VIA_C3) += c3 - +subdirs-$(CONFIG_CPU_VIA_C7) += c7 +subdirs-$(CONFIG_CPU_VIA_C3) += c3 +subdirs-$(CONFIG_CPU_VIA_NANO) += nano diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig new file mode 100644 index 0000000..3b1c213 --- /dev/null +++ b/src/cpu/via/nano/Kconfig @@ -0,0 +1,41 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see <http://www.gnu.org/licenses/>. +## + +config CPU_VIA_NANO + bool + +if CPU_VIA_NANO + +config CPU_SPECIFIC_OPTIONS + def_bool y + select UDELAY_TSC + select MMX + select SSE2 + select CACHE_AS_RAM + select CPU_MICROCODE_IN_CBFS + +config DCACHE_RAM_BASE + hex + default 0xffe00000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +endif # CPU_VIA_NANO diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc new file mode 100644 index 0000000..6b0c1e9 --- /dev/null +++ b/src/cpu/via/nano/Makefile.inc @@ -0,0 +1,33 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see <http://www.gnu.org/licenses/>. +## + +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm + +driver-y += nano_init.c +ramstage-y += update_ucode.c + +# We need to hear from VIA to get permission to include this file in the +# official coreboot repository. Until then, we leave this commented out +# cpu-microcode-y += nano_ucode_blob.c + +cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c new file mode 100644 index 0000000..417119f --- /dev/null +++ b/src/cpu/via/nano/nano_init.c @@ -0,0 +1,204 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "update_ucode.h" +#include <console/console.h> +#include <device/device.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/cache.h> +#include <delay.h> + +#define MODEL_NANO 0x2 +#define MODEL_NANO_3000_B0 0x8 +#define MODEL_NANO_3000_B2 0xa + +#define MSR_IA32_PERF_STATUS 0x00000198 +#define MSR_IA32_PERF_CTL 0x00000199 +#define MSR_IA32_MISC_ENABLE 0x000001a0 +#define NANO_MYSTERIOUS_MSR 0x120e + +static void nano_finish_fid_vid_transition(void) +{ + + msr_t msr; + /* Wait until the power transition ends */ + int cnt = 0; + do { + udelay(16); + msr = rdmsr(MSR_IA32_PERF_STATUS); + cnt++; + if (cnt > 128) { + printk(BIOS_WARNING, + "Error while updating multiplier and voltage\n"); + break; + } + } while (msr.lo & ((1 << 16) | (1 << 17))); + + /* Print the new FID and Voltage */ + u8 cur_vid = (msr.lo >> 0) & 0xff; + u8 cur_fid = (msr.lo >> 8) & 0xff; + printk(BIOS_INFO, "New CPU multiplier: %dx\n", cur_fid); + printk(BIOS_INFO, "New Voltage ID : %dx\n", cur_vid); +} + +static void nano_set_max_fid_vid(void) +{ + msr_t msr; + /* Get voltage and frequency info */ + msr = rdmsr(MSR_IA32_PERF_STATUS); + u8 min_fid = (msr.hi >> 24); + u8 max_fid = (msr.hi >> 8) & 0xff; + u8 min_vid = (msr.hi >> 16) & 0xff; + u8 max_vid = (msr.hi >> 0) & 0xff; + u8 cur_vid = (msr.lo >> 0) & 0xff; + u8 cur_fid = (msr.lo >> 8) & 0xff; + + printk(BIOS_INFO, "CPU multiplier: %dx (min %dx; max %dx)\n", + cur_fid, min_fid, max_fid); + printk(BIOS_INFO, "Voltage ID : %dx (min %dx; max %dx)\n", + cur_vid, min_vid, max_vid); + + if( (cur_fid != max_fid) || (cur_vid != max_vid) ) { + /* Set highest frequency and VID */ + msr.lo = msr.hi; + msr.hi = 0; + wrmsr(MSR_IA32_PERF_CTL, msr); + /* Wait for the transition to complete, otherwise, the CPU + * might reset itself repeatedly */ + nano_finish_fid_vid_transition(); + } + /* As a side note, if we didn't update the microcode by this point, the + * second PLL will not lock correctly. The clock will still be provided + * by the first PLL, and execution will continue normally, ___until___ + * the CPU switches PLL. Once that happens we will no longer have a + * working clock source, and the CPU will hang + * Moral of the story: update the microcode, or don't change FID + * This check is handled before calling nano_power() */ +} + +static void nano_power(void) +{ + msr_t msr; + /* Enable Powersaver */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= (1 << 16); + wrmsr(MSR_IA32_MISC_ENABLE, msr); + + /* Enable 6 bit or 7-bit VRM support + * This MSR is not documented by VIA docs, other than setting these + * bits */ + msr = rdmsr(NANO_MYSTERIOUS_MSR); + msr.lo |= ( (1<<7) | (1<<4) ); + /* FIXME: Do we have a 6-bit or 7-bit VRM? + * set bit [5] for 7-bit, or don't set it for 6 bit VRM + * This will probably require a Kconfig option + * My board has a 7-bit VRM, so I can't test the 6-bit VRM stuff */ + msr.lo |= (1<<5); + wrmsr(NANO_MYSTERIOUS_MSR, msr); + + /* Set the maximum frequency and voltage */ + nano_set_max_fid_vid(); + + /* Enable TM3 */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= ( (1<<3) | (1<<13) ); + wrmsr(MSR_IA32_MISC_ENABLE, msr); + + u8 stepping = ( cpuid_eax(0x1) ) &0xf; + if(stepping >= MODEL_NANO_3000_B0) { + /* Hello Nano 3000. The Terminator needs a CPU upgrade */ + /* Enable C1e, C2e, C3e, and C4e states */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= ( (1<<25) | (1<<26) | (1<<31)); /* C1e, C2e, C3e */ + msr.hi |= (1<<0); /* C4e */ + wrmsr(MSR_IA32_MISC_ENABLE, msr); + } + + /* Lock on Powersaver */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= (1<<20); + wrmsr(MSR_IA32_MISC_ENABLE, msr); +} + +static void nano_init(device_t dev) +{ + struct cpuinfo_x86 c; + + get_fms(&c, dev->device); + + /* We didn't test this on the Nano 1000/2000 series, so warn the user */ + if(c.x86_mask < MODEL_NANO_3000_B0) { + printk(BIOS_EMERG, "WARNING: This CPU has not been tested. " + "Please report any issues encountered. \n"); + } + switch (c.x86_mask) { + case MODEL_NANO: + printk(BIOS_INFO, "VIA Nano"); + break; + case MODEL_NANO_3000_B0: + printk(BIOS_INFO, "VIA Nano 3000 rev B0"); + break; + case MODEL_NANO_3000_B2: + printk(BIOS_INFO, "VIA Nano 3000 rev B2"); + break; + default: + printk(BIOS_EMERG, "Stepping not recognized: %x\n", c.x86_mask); + } + printk(BIOS_INFO, "\n"); + + /* We only read microcode from CBFS. If we don't have any microcode in + * CBFS, we'll just get back with 0 updates. User choice FTW. */ + unsigned int n_updates = nano_update_ucode(); + + if(n_updates != 0){ + nano_power(); + } else { + /* Changing the frequency or voltage without first updating the + * microcode will hang the CPU, so just don't do it */ + printk(BIOS_EMERG, "WARNING: CPU Microcode not updated.\n" + " Will not change frequency, as this may hang the CPU.\n"); + } + + /* Turn on cache */ + x86_enable_cache(); + /* Set up Memory Type Range Registers */ + x86_setup_mtrrs(); + x86_mtrr_check(); + /* Enable the local cpu apics */ + setup_lapic(); +} + +static struct device_operations cpu_dev_ops = { + .init = nano_init, +}; + +static struct cpu_device_id cpu_table[] = { + {X86_VENDOR_CENTAUR, 0x06f2}, // VIA NANO 1000/2000 Series + {X86_VENDOR_CENTAUR, 0x06f8}, // VIA NANO 3000 rev B0 + {X86_VENDOR_CENTAUR, 0x06fa}, // VIA NANO 3000 rev B2 + {0, 0}, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c new file mode 100644 index 0000000..8f7ee22 --- /dev/null +++ b/src/cpu/via/nano/update_ucode.c @@ -0,0 +1,150 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "update_ucode.h" +#include <cpu/x86/msr.h> +#include <console/console.h> +#include <stddef.h> +#include <cpu/cpu.h> +#include <arch/cpu.h> +#include <cbfs.h> + +static ucode_update_status nano_apply_ucode(const nano_ucode_header *ucode) +{ + printk(BIOS_SPEW, "Attempting to apply microcode update\n"); + + msr_t msr; + /* Address of ucode block goes in msr.lo for 32-bit mode + * Now remember, we need to pass the address of the actual microcode, + * not the header. The header is just there to help us. */ + msr.lo = (unsigned int)(&(ucode->ucode_start)); + msr.hi = 0; + wrmsr(MSR_IA32_BIOS_UPDT_TRIG, msr); + + /* Let's see if we updated succesfully */ + msr = rdmsr(MSR_UCODE_UPDATE_STATUS); + + return msr.lo & 0x07; +} + +static void nano_print_ucode_info(const nano_ucode_header *ucode) +{ + printk(BIOS_SPEW, "Microcode update information:\n"); + printk(BIOS_SPEW, "Name: %8s\n", ucode->name ); + printk(BIOS_SPEW, "Date: %u/%u/%u\n", ucode->month, + ucode->day, ucode->year ); +} + +static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode) +{ + /* We must have a valid signature */ + if(ucode->signature != NANO_UCODE_SIGNATURE) + return NANO_UCODE_SIGNATURE_ERROR; + /* The size of the head must be exactly 12 double words */ + if( (ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE) + return NANO_UCODE_WRONG_SIZE; + + /* How about a checksum ? Checksum must be 0 + * Two's complement done over the entire file, including the header */ + int i; + u32 check = 0; + u32 *raw = (void*) ucode; + for(i = 0 ; i < ((ucode->total_size) >> 2); i++) { + check += raw[i]; + } + if(check != 0) + return NANO_UCODE_CHECKSUM_FAIL; + /* Made it here huh? Then it looks valid to us. + * If there's anything else wrong, the CPU will reject the update */ + return NANO_UCODE_VALID; +} + +static void nano_print_ucode_status(ucode_update_status stat) +{ + switch(stat) + { + case UCODE_UPDATE_SUCCESS: + printk(BIOS_INFO, "Microcode update succesful.\n"); + break; + case UCODE_UPDATE_FAIL: + printk(BIOS_ALERT, "Microcode update failed, bad environment." + "Update was not applied.\n"); + break; + case UCODE_UPDATE_WRONG_CPU: + printk(BIOS_ALERT, "Update not applicable to this CPU.\n"); + break; + case UCODE_INVALID_UPDATE_BLOCK: + printk(BIOS_ALERT, "Microcode block invalid." + "Update was not applied.\n"); + break; + default: + printk(BIOS_ALERT, "Unknown status. No update applied.\n"); + } +} + +unsigned int nano_update_ucode(void) +{ + size_t i; + unsigned int n_updates = 0; + const struct cbfs_file *cbfs_ucode; + u32 fms = cpuid_eax(0x1); + + cbfs_ucode = cbfs_find("cpu_microcode_blob.bin"); + /* Oops, did you forget to include the microcode ? */ + if(cbfs_ucode == NULL) { + printk(BIOS_ALERT, "WARNING: No microcode file found in CBFS. " + "Aborting microcode updates\n"); + return 0; + } + + /* Considering we are running with eXecute-In-Place (XIP), there's no + * need to worry that accessing data from ROM will slow us down. + * Microcode data should be aligned to a 4-byte boundary, but CBFS + * already does that for us (Do you, CBFS?) */ + const u32 *ucode_data = CBFS_SUBHEADER(cbfs_ucode); + const u32 ucode_len = ntohl(cbfs_ucode->len); + + /* We might do a lot of loops searching for the microcode updates, but + * keep in mind, nano_ucode_is_valid searches for the signature before + * doing anything else. */ + for( i = 0; i < (ucode_len >> 2); /* don't increment i here */ ) + { + ucode_update_status stat; + const nano_ucode_header * ucode = (void *)(&ucode_data[i]); + if(nano_ucode_is_valid(ucode) != NANO_UCODE_VALID) { + i++; + continue; + } + /* Since we have a valid microcode, there's no need to search + * in this region, so we restart our search at the end of this + * microcode */ + i += (ucode->total_size >> 2); + /* Is the microcode compatible with our CPU? */ + if(ucode->applicable_fms != fms) continue; + /* For our most curious users */ + nano_print_ucode_info(ucode); + /* The meat of the pie */ + stat = nano_apply_ucode(ucode); + /* The user might want to know how the update went */ + nano_print_ucode_status(stat); + if(stat == UCODE_UPDATE_SUCCESS) n_updates++; + } + + return n_updates; +} diff --git a/src/cpu/via/nano/update_ucode.h b/src/cpu/via/nano/update_ucode.h new file mode 100644 index 0000000..6a22d18 --- /dev/null +++ b/src/cpu/via/nano/update_ucode.h @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#ifndef __UPDATE_UCODE_H +#define __UPDATE_UCODE_H + +#include <console/console.h> +#include <cpu/cpu.h> + +#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079 +#define MSR_IA32_BIOS_SIGN_ID 0x0000008b +#define MSR_UCODE_UPDATE_STATUS 0x00001205 + +#define NANO_UCODE_SIGNATURE 0x53415252 +#define NANO_UCODE_HEADER_SIZE 0x30 + +/* These are values returned by the CPU after we attempt microcode updates. + * We care what these values are exactly, so we define them to be sure */ +typedef enum { + UCODE_UPDATE_NOT_ATTEMPTED = 0x0, + UCODE_UPDATE_SUCCESS = 0x1, + UCODE_UPDATE_FAIL = 0x2, + UCODE_UPDATE_WRONG_CPU = 0x3, + UCODE_INVALID_UPDATE_BLOCK = 0x4, +} ucode_update_status; + + +typedef enum { + NANO_UCODE_VALID = 0, /* We only care that valid == 0 */ + NANO_UCODE_SIGNATURE_ERROR, + NANO_UCODE_WRONG_SIZE, + NANO_UCODE_CHECKSUM_FAIL, +} ucode_validity; + +typedef struct { + u32 signature; /* NANO_UCODE_SIGNATURE */ + u32 update_revision; /* Revision of the update header */ + u16 year; /* Year of patch release */ + u8 day; /* Day of patch release */ + u8 month; /* Month of patch release */ + u32 applicable_fms; /* Fam/model/stepping to which ucode applies */ + u32 checksum; /* Two's complement checksum of ucode+header */ + u32 loader_revision; /* Revision of hardware ucode update loader*/ + u32 rfu_1; /* Reservod for future use */ + u32 payload_size; /* Size of the ucode payload only */ + u32 total_size; /* Size of the ucode, including header */ + char name[8]; /* ASCII string of ucode filename */ + u32 rfu_2; /* Reservod for future use */ + /* First double-word of the ucode payload + * Its address represents the beginning of the ucode update we need to + * send to the CPU */ + u32 ucode_start; + +} nano_ucode_header; + +unsigned int nano_update_ucode(void); + +#endif /* __UPDATE_UCODE_H */

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coreboot August 2012