coreboot August 2012

coreboot@coreboot.org

30 participants
321 discussions

New patch to review for coreboot: e0cb055 Add possibility to patch VGA oprom
by Christian Gmeiner 22 Aug '12

22 Aug '12

Christian Gmeiner (christian.gmeiner(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1478 -gerrit commit e0cb05598872e866d6b8afee2eed3db9a0bff624 Author: Christian Gmeiner <christian.gmeiner(a)gmail.com> Date: Wed Aug 22 16:10:46 2012 +0200 Add possibility to patch VGA oprom In some rare cases it could be usefull to patch a VGA oprom in order to fix some stuff. In later patches this will be used to add EDID information to SeaVIDEOBIOS in oder to support some flat panels. Change-Id: Ic1005053265505a65b6fd99bc3c6c9cfcbffee43 Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- src/devices/pci_rom.c | 7 +++++++ src/include/device/pci_rom.h | 3 +++ 2 files changed, 10 insertions(+) diff --git a/src/devices/pci_rom.c b/src/devices/pci_rom.c index fe67515..b001ee3 100644 --- a/src/devices/pci_rom.c +++ b/src/devices/pci_rom.c @@ -162,6 +162,13 @@ struct rom_header *pci_rom_load(struct device *dev, memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header, rom_size); } + + /* In some cases it is usefull to patch an pci vga oprom. A good example + * is adding/changing some EDID information stored in the VGA option rom. + */ + if (pci_vga_rom_patch) + pci_vga_rom_patch(rom_data, (void *)PCI_VGA_RAM_IMAGE_START); + return (struct rom_header *) (PCI_VGA_RAM_IMAGE_START); } diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index fe77276..690e304 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -37,4 +37,7 @@ struct rom_header *pci_rom_probe(struct device *dev); struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header); u32 __attribute__((weak)) map_oprom_vendev(u32 vendev); +void __attribute__((weak)) +pci_vga_rom_patch(struct pci_data *rom_data, void *pci_vga_ram_image_start); + #endif

1 0

Patch set updated for coreboot: f256bc2 MPTABLE: cleanup code
by Sven Schnelle 22 Aug '12

22 Aug '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1477 -gerrit commit f256bc25e3df054abc00d3d55f4243ac7c6f42fd Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Aug 22 10:07:09 2012 +0200 MPTABLE: cleanup code Split the mptable autogen code into functions to make it more readable. Change-Id: I9a09945ea415c68cd79c5abfcdf4788141eb035a Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/arch/x86/boot/mpspec.c | 130 +++++++++++++++++++++++++++------------------ 1 file changed, 78 insertions(+), 52 deletions(-) diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c index cf346a5..bf84579 100644 --- a/src/arch/x86/boot/mpspec.c +++ b/src/arch/x86/boot/mpspec.c @@ -412,14 +412,80 @@ void *mptable_finalize(struct mp_config_table *mc) return smp_next_mpe_entry(mc); } + +static int write_fixed_entry(struct mp_config_table *mc, device_t dev) +{ + int have_fixed_entries, pin; + struct pci_irq_info *irq; + + have_fixed_entries = 0; + + for (pin = 0; pin < 4; pin++) { + irq = dev->pci_irq_info + pin; + + if (!irq->ioapic_dst_id) + continue; + + + printk(BIOS_DEBUG, "fixed IRQ entry for: %s: " + "INT%c# -> IOAPIC %d PIN %d\n", dev_path(dev), + pin + 'A', + irq->ioapic_dst_id, + irq->ioapic_irq_pin); + smp_write_intsrc(mc, mp_INT, irq->ioapic_flags, + dev->bus->secondary, + ((dev->path.pci.devfn & 0xf8) >> 1) | pin, + irq->ioapic_dst_id, irq->ioapic_irq_pin); + have_fixed_entries = 1; + } + return have_fixed_entries; +} + +static void write_automatic_entry(struct mp_config_table *mc, device_t dev) +{ + int parentpin, pin; + device_t parent, oldparent; + struct pci_irq_info *irq; + + pin = (dev->path.pci.devfn & 7) % 4; + oldparent = parent = dev; + + while((parent = parent->bus->dev)) { + parentpin = (oldparent->path.pci.devfn >> 3) + (oldparent->path.pci.devfn & 7); + parentpin += dev->path.pci.devfn & 7; + parentpin += dev->path.pci.devfn >> 3; + parentpin %= 4; + + irq = parent->pci_irq_info + parentpin; + if (irq->ioapic_dst_id) { + printk(BIOS_DEBUG, "automatic IRQ entry for %s: " + "INT%c# -> IOAPIC %d PIN %d\n", + dev_path(dev), pin + 'A', + irq->ioapic_dst_id, irq->ioapic_irq_pin); + smp_write_intsrc(mc, mp_INT, + irq->ioapic_flags, dev->bus->secondary, + ((dev->path.pci.devfn & 0xf8) >> 1) | pin, + irq->ioapic_dst_id, irq->ioapic_irq_pin); + + break; + } + + if (parent->path.type == DEVICE_PATH_PCI_DOMAIN) { + printk(BIOS_WARNING, "no IRQ found for %s\n", dev_path(dev)); + break; + } + oldparent = parent; + } +} + unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) { struct drivers_generic_ioapic_config *ioapic_config; struct mp_config_table *mc; - int isa_bus, pin, parentpin; - device_t dev, parent, oldparent; + int isa_bus; + device_t dev; void *tmp, *v; - int isaioapic = -1, have_fixed_entries; + int isaioapic = -1; v = smp_write_floating_table(addr, 0); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -435,16 +501,19 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) continue; if (!(ioapic_config = dev->chip_info)) { - printk(BIOS_ERR, "%s has no config, ignoring\n", dev_path(dev)); + printk(BIOS_ERR, "%s has no config, ignoring\n", + dev_path(dev)); continue; } + smp_write_ioapic(mc, dev->path.ioapic.ioapic_id, ioapic_config->version, ioapic_config->base); if (ioapic_config->have_isa_interrupts) { if (isaioapic >= 0) - printk(BIOS_ERR, "More than one IOAPIC with ISA interrupts?\n"); + printk(BIOS_ERR, "More than one IOAPIC " + "with ISA interrupts?\n"); else isaioapic = dev->path.ioapic.ioapic_id; } @@ -461,58 +530,15 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) if (dev->path.type != DEVICE_PATH_PCI || !dev->enabled) continue; - have_fixed_entries = 0; - for (pin = 0; pin < 4; pin++) { - if (dev->pci_irq_info[pin].ioapic_dst_id) { - printk(BIOS_DEBUG, "fixed IRQ entry for: %s: INT%c# -> IOAPIC %d PIN %d\n", dev_path(dev), - pin + 'A', - dev->pci_irq_info[pin].ioapic_dst_id, - dev->pci_irq_info[pin].ioapic_irq_pin); - smp_write_intsrc(mc, mp_INT, - dev->pci_irq_info[pin].ioapic_flags, - dev->bus->secondary, - ((dev->path.pci.devfn & 0xf8) >> 1) | pin, - dev->pci_irq_info[pin].ioapic_dst_id, - dev->pci_irq_info[pin].ioapic_irq_pin); - have_fixed_entries = 1; - } - } + if (!write_fixed_entry(mc, dev)) { + write_automatic_entry(mc, dev); - if (!have_fixed_entries) { - pin = (dev->path.pci.devfn & 7) % 4; - oldparent = parent = dev; - while((parent = parent->bus->dev)) { - parentpin = (oldparent->path.pci.devfn >> 3) + (oldparent->path.pci.devfn & 7); - parentpin += dev->path.pci.devfn & 7; - parentpin += dev->path.pci.devfn >> 3; - parentpin %= 4; - - if (parent->pci_irq_info[parentpin].ioapic_dst_id) { - printk(BIOS_DEBUG, "automatic IRQ entry for %s: INT%c# -> IOAPIC %d PIN %d\n", - dev_path(dev), pin + 'A', - parent->pci_irq_info[parentpin].ioapic_dst_id, - parent->pci_irq_info[parentpin].ioapic_irq_pin); - smp_write_intsrc(mc, mp_INT, - parent->pci_irq_info[parentpin].ioapic_flags, - dev->bus->secondary, - ((dev->path.pci.devfn & 0xf8) >> 1) | pin, - parent->pci_irq_info[parentpin].ioapic_dst_id, - parent->pci_irq_info[parentpin].ioapic_irq_pin); - - break; - } - - if (parent->path.type == DEVICE_PATH_PCI_DOMAIN) { - printk(BIOS_WARNING, "no IRQ found for %s\n", dev_path(dev)); - break; - } - oldparent = parent; - } } } mptable_lintsrc(mc, isa_bus); tmp = mptable_finalize(mc); - printk(BIOS_INFO, "MPTABLE len: %d\n", (unsigned int)tmp - (unsigned int)v); + printk(BIOS_INFO, "MPTABLE len: %d\n", + (unsigned int)tmp - (unsigned int)v); return (unsigned long)tmp; }

1 0

Patch set updated for coreboot: e2063bc bd82x6x: remove ioapic initialization
by Sven Schnelle 22 Aug '12

22 Aug '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1463 -gerrit commit e2063bce3f0accc9d8d2d4d9441cb00d48931ec0 Author: Sven Schnelle <svens(a)stackframe.org> Date: Mon Aug 20 11:22:37 2012 +0200 bd82x6x: remove ioapic initialization This now done by the generic ioapic driver. Change-Id: Iea648158c429ee5b053c7b3f3cdfcfaecb4eb4c3 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/southbridge/intel/bd82x6x/lpc.c | 49 ++----------------------------------- 1 file changed, 2 insertions(+), 47 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 592f5de..3a6140f 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -26,7 +26,6 @@ #include <pc80/isa-dma.h> #include <pc80/i8259.h> #include <arch/io.h> -#include <arch/ioapic.h> #include <arch/acpi.h> #include <cpu/cpu.h> #include <elog.h> @@ -39,45 +38,6 @@ typedef struct southbridge_intel_bd82x6x_config config_t; -static void pch_enable_apic(struct device *dev) -{ - int i; - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ - pci_write_config8(dev, ACPI_CNTL, 0x80); - - *ioapic_index = 0; - *ioapic_data = (1 << 25); - - /* affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - *ioapic_index = 1; - *ioapic_data = reg32; - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } - - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ -} - static void pch_enable_serial_irqs(struct device *dev) { /* Set packet length and toggle silent mode bit for one frame. */ @@ -537,8 +497,8 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); - /* IO APIC initialization. */ - pch_enable_apic(dev); + /* enable ACPI */ + pci_write_config8(dev, ACPI_CNTL, 0x80); pch_enable_serial_irqs(dev); @@ -612,11 +572,6 @@ static void pch_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - /* Set PCH IO decode ranges if required.*/ if ((config->gen1_dec & 0xFFFC) > 0x1000) { res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));

1 0

New patch to review for coreboot: bafa2e9 IOAPIC: cleanup code
by Sven Schnelle 22 Aug '12

22 Aug '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1477 -gerrit commit bafa2e93915536fa70c7d1fb90f97868bdb03dae Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Aug 22 10:07:09 2012 +0200 IOAPIC: cleanup code Split the code up into functions to make it more readable. Change-Id: I9a09945ea415c68cd79c5abfcdf4788141eb035a Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/arch/x86/boot/mpspec.c | 130 +++++++++++++++++++++++++++------------------ 1 file changed, 78 insertions(+), 52 deletions(-) diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c index cf346a5..bf84579 100644 --- a/src/arch/x86/boot/mpspec.c +++ b/src/arch/x86/boot/mpspec.c @@ -412,14 +412,80 @@ void *mptable_finalize(struct mp_config_table *mc) return smp_next_mpe_entry(mc); } + +static int write_fixed_entry(struct mp_config_table *mc, device_t dev) +{ + int have_fixed_entries, pin; + struct pci_irq_info *irq; + + have_fixed_entries = 0; + + for (pin = 0; pin < 4; pin++) { + irq = dev->pci_irq_info + pin; + + if (!irq->ioapic_dst_id) + continue; + + + printk(BIOS_DEBUG, "fixed IRQ entry for: %s: " + "INT%c# -> IOAPIC %d PIN %d\n", dev_path(dev), + pin + 'A', + irq->ioapic_dst_id, + irq->ioapic_irq_pin); + smp_write_intsrc(mc, mp_INT, irq->ioapic_flags, + dev->bus->secondary, + ((dev->path.pci.devfn & 0xf8) >> 1) | pin, + irq->ioapic_dst_id, irq->ioapic_irq_pin); + have_fixed_entries = 1; + } + return have_fixed_entries; +} + +static void write_automatic_entry(struct mp_config_table *mc, device_t dev) +{ + int parentpin, pin; + device_t parent, oldparent; + struct pci_irq_info *irq; + + pin = (dev->path.pci.devfn & 7) % 4; + oldparent = parent = dev; + + while((parent = parent->bus->dev)) { + parentpin = (oldparent->path.pci.devfn >> 3) + (oldparent->path.pci.devfn & 7); + parentpin += dev->path.pci.devfn & 7; + parentpin += dev->path.pci.devfn >> 3; + parentpin %= 4; + + irq = parent->pci_irq_info + parentpin; + if (irq->ioapic_dst_id) { + printk(BIOS_DEBUG, "automatic IRQ entry for %s: " + "INT%c# -> IOAPIC %d PIN %d\n", + dev_path(dev), pin + 'A', + irq->ioapic_dst_id, irq->ioapic_irq_pin); + smp_write_intsrc(mc, mp_INT, + irq->ioapic_flags, dev->bus->secondary, + ((dev->path.pci.devfn & 0xf8) >> 1) | pin, + irq->ioapic_dst_id, irq->ioapic_irq_pin); + + break; + } + + if (parent->path.type == DEVICE_PATH_PCI_DOMAIN) { + printk(BIOS_WARNING, "no IRQ found for %s\n", dev_path(dev)); + break; + } + oldparent = parent; + } +} + unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) { struct drivers_generic_ioapic_config *ioapic_config; struct mp_config_table *mc; - int isa_bus, pin, parentpin; - device_t dev, parent, oldparent; + int isa_bus; + device_t dev; void *tmp, *v; - int isaioapic = -1, have_fixed_entries; + int isaioapic = -1; v = smp_write_floating_table(addr, 0); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -435,16 +501,19 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) continue; if (!(ioapic_config = dev->chip_info)) { - printk(BIOS_ERR, "%s has no config, ignoring\n", dev_path(dev)); + printk(BIOS_ERR, "%s has no config, ignoring\n", + dev_path(dev)); continue; } + smp_write_ioapic(mc, dev->path.ioapic.ioapic_id, ioapic_config->version, ioapic_config->base); if (ioapic_config->have_isa_interrupts) { if (isaioapic >= 0) - printk(BIOS_ERR, "More than one IOAPIC with ISA interrupts?\n"); + printk(BIOS_ERR, "More than one IOAPIC " + "with ISA interrupts?\n"); else isaioapic = dev->path.ioapic.ioapic_id; } @@ -461,58 +530,15 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) if (dev->path.type != DEVICE_PATH_PCI || !dev->enabled) continue; - have_fixed_entries = 0; - for (pin = 0; pin < 4; pin++) { - if (dev->pci_irq_info[pin].ioapic_dst_id) { - printk(BIOS_DEBUG, "fixed IRQ entry for: %s: INT%c# -> IOAPIC %d PIN %d\n", dev_path(dev), - pin + 'A', - dev->pci_irq_info[pin].ioapic_dst_id, - dev->pci_irq_info[pin].ioapic_irq_pin); - smp_write_intsrc(mc, mp_INT, - dev->pci_irq_info[pin].ioapic_flags, - dev->bus->secondary, - ((dev->path.pci.devfn & 0xf8) >> 1) | pin, - dev->pci_irq_info[pin].ioapic_dst_id, - dev->pci_irq_info[pin].ioapic_irq_pin); - have_fixed_entries = 1; - } - } + if (!write_fixed_entry(mc, dev)) { + write_automatic_entry(mc, dev); - if (!have_fixed_entries) { - pin = (dev->path.pci.devfn & 7) % 4; - oldparent = parent = dev; - while((parent = parent->bus->dev)) { - parentpin = (oldparent->path.pci.devfn >> 3) + (oldparent->path.pci.devfn & 7); - parentpin += dev->path.pci.devfn & 7; - parentpin += dev->path.pci.devfn >> 3; - parentpin %= 4; - - if (parent->pci_irq_info[parentpin].ioapic_dst_id) { - printk(BIOS_DEBUG, "automatic IRQ entry for %s: INT%c# -> IOAPIC %d PIN %d\n", - dev_path(dev), pin + 'A', - parent->pci_irq_info[parentpin].ioapic_dst_id, - parent->pci_irq_info[parentpin].ioapic_irq_pin); - smp_write_intsrc(mc, mp_INT, - parent->pci_irq_info[parentpin].ioapic_flags, - dev->bus->secondary, - ((dev->path.pci.devfn & 0xf8) >> 1) | pin, - parent->pci_irq_info[parentpin].ioapic_dst_id, - parent->pci_irq_info[parentpin].ioapic_irq_pin); - - break; - } - - if (parent->path.type == DEVICE_PATH_PCI_DOMAIN) { - printk(BIOS_WARNING, "no IRQ found for %s\n", dev_path(dev)); - break; - } - oldparent = parent; - } } } mptable_lintsrc(mc, isa_bus); tmp = mptable_finalize(mc); - printk(BIOS_INFO, "MPTABLE len: %d\n", (unsigned int)tmp - (unsigned int)v); + printk(BIOS_INFO, "MPTABLE len: %d\n", + (unsigned int)tmp - (unsigned int)v); return (unsigned long)tmp; }

1 0

Patch set updated for coreboot: 5efc015 MPTABLE: check for fixed IRQ entries on all pins
by Sven Schnelle 22 Aug '12

22 Aug '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1461 -gerrit commit 5efc015626acc7a65bf012164d9f1ca6fcc97529 Author: Sven Schnelle <svens(a)stackframe.org> Date: Mon Aug 20 11:19:00 2012 +0200 MPTABLE: check for fixed IRQ entries on all pins Don't derive the IRQ pin from the function number. Especially onboard chipset devices don't follow that rule. Instead check and add all fixed IRQ entries. Change-Id: I46c88bad39104c1d9b4154f180f8b3c42df28262 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/arch/x86/boot/mpspec.c | 89 ++++++++++++++++++++++++---------------------- 1 file changed, 47 insertions(+), 42 deletions(-) diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c index 78996c7..cf346a5 100644 --- a/src/arch/x86/boot/mpspec.c +++ b/src/arch/x86/boot/mpspec.c @@ -419,7 +419,7 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) int isa_bus, pin, parentpin; device_t dev, parent, oldparent; void *tmp, *v; - int isaioapic = -1; + int isaioapic = -1, have_fixed_entries; v = smp_write_floating_table(addr, 0); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -461,48 +461,53 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) if (dev->path.type != DEVICE_PATH_PCI || !dev->enabled) continue; - pin = (dev->path.pci.devfn & 7) % 4; - - if (dev->pci_irq_info[pin].ioapic_dst_id) { - printk(BIOS_DEBUG, "fixed IRQ entry for: %s: INT%c# -> IOAPIC %d PIN %d\n", dev_path(dev), - pin + 'A', - dev->pci_irq_info[pin].ioapic_dst_id, - dev->pci_irq_info[pin].ioapic_irq_pin); - smp_write_intsrc(mc, mp_INT, - dev->pci_irq_info[pin].ioapic_flags, - dev->bus->secondary, - ((dev->path.pci.devfn & 0xf8) >> 1) | pin, - dev->pci_irq_info[pin].ioapic_dst_id, - dev->pci_irq_info[pin].ioapic_irq_pin); - } else { - oldparent = parent = dev; - while((parent = parent->bus->dev)) { - parentpin = (oldparent->path.pci.devfn >> 3) + (oldparent->path.pci.devfn & 7); - parentpin += dev->path.pci.devfn & 7; - parentpin += dev->path.pci.devfn >> 3; - parentpin %= 4; - - if (parent->pci_irq_info[parentpin].ioapic_dst_id) { - printk(BIOS_DEBUG, "automatic IRQ entry for %s: INT%c# -> IOAPIC %d PIN %d\n", - dev_path(dev), pin + 'A', - parent->pci_irq_info[parentpin].ioapic_dst_id, - parent->pci_irq_info[parentpin].ioapic_irq_pin); - smp_write_intsrc(mc, mp_INT, - parent->pci_irq_info[parentpin].ioapic_flags, - dev->bus->secondary, - ((dev->path.pci.devfn & 0xf8) >> 1) | pin, - parent->pci_irq_info[parentpin].ioapic_dst_id, - parent->pci_irq_info[parentpin].ioapic_irq_pin); - - break; - } - - if (parent->path.type == DEVICE_PATH_PCI_DOMAIN) { - printk(BIOS_WARNING, "no IRQ found for %s\n", dev_path(dev)); - break; - } - oldparent = parent; + have_fixed_entries = 0; + for (pin = 0; pin < 4; pin++) { + if (dev->pci_irq_info[pin].ioapic_dst_id) { + printk(BIOS_DEBUG, "fixed IRQ entry for: %s: INT%c# -> IOAPIC %d PIN %d\n", dev_path(dev), + pin + 'A', + dev->pci_irq_info[pin].ioapic_dst_id, + dev->pci_irq_info[pin].ioapic_irq_pin); + smp_write_intsrc(mc, mp_INT, + dev->pci_irq_info[pin].ioapic_flags, + dev->bus->secondary, + ((dev->path.pci.devfn & 0xf8) >> 1) | pin, + dev->pci_irq_info[pin].ioapic_dst_id, + dev->pci_irq_info[pin].ioapic_irq_pin); + have_fixed_entries = 1; + } + } + + if (!have_fixed_entries) { + pin = (dev->path.pci.devfn & 7) % 4; + oldparent = parent = dev; + while((parent = parent->bus->dev)) { + parentpin = (oldparent->path.pci.devfn >> 3) + (oldparent->path.pci.devfn & 7); + parentpin += dev->path.pci.devfn & 7; + parentpin += dev->path.pci.devfn >> 3; + parentpin %= 4; + + if (parent->pci_irq_info[parentpin].ioapic_dst_id) { + printk(BIOS_DEBUG, "automatic IRQ entry for %s: INT%c# -> IOAPIC %d PIN %d\n", + dev_path(dev), pin + 'A', + parent->pci_irq_info[parentpin].ioapic_dst_id, + parent->pci_irq_info[parentpin].ioapic_irq_pin); + smp_write_intsrc(mc, mp_INT, + parent->pci_irq_info[parentpin].ioapic_flags, + dev->bus->secondary, + ((dev->path.pci.devfn & 0xf8) >> 1) | pin, + parent->pci_irq_info[parentpin].ioapic_dst_id, + parent->pci_irq_info[parentpin].ioapic_irq_pin); + + break; } + + if (parent->path.type == DEVICE_PATH_PCI_DOMAIN) { + printk(BIOS_WARNING, "no IRQ found for %s\n", dev_path(dev)); + break; + } + oldparent = parent; + } } }

1 0

Patch merged into coreboot/master: 81dd2fa LUMPY: Add information to generate MPTABLE from devicetree.cb
by gerrit＠coreboot.org 22 Aug '12

22 Aug '12

the following patch was just integrated into master: commit 81dd2fa439e2937021343829b5dd9d4342d39e8e Author: Sven Schnelle <svens(a)stackframe.org> Date: Mon Aug 20 11:21:00 2012 +0200 LUMPY: Add information to generate MPTABLE from devicetree.cb Change-Id: If68888e87c5197328c59dafce1301eefe000e28e Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Mon Aug 20 13:10:09 2012, giving +1 See http://review.coreboot.org/1462 for details. -gerrit

1 0

Patch set updated for coreboot: c4d202a AMD Hudson: Move the combining firmware from Python to sh.
by Zheng Bao 22 Aug '12

22 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1417 -gerrit commit c4d202a8da739ec8e21ad68b155f498f631ec0dd Author: zbao <fishbaozi(a)gmail.com> Date: Wed Aug 22 17:06:29 2012 +0800 AMD Hudson: Move the combining firmware from Python to sh. Maybe sooner or later python is not a default tools to build coreboot. Most of the work is done by awk now. GNU extension of gawk is not used, isn't? echo, expr, printf, cat, awk, test, mv are the external tools. If XHCI, IMC or GEC firmware is not available and not defined, this script can skip integrating them. Change-Id: I9944b22b0b755672a46d472c355d138abafd6393 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/southbridge/amd/agesa/hudson/Makefile.inc | 68 ++++++++++++++++++++++++-- src/southbridge/amd/agesa/hudson/hudson_fwm.py | 64 ------------------------ 2 files changed, 64 insertions(+), 68 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 19ffae1..fc31d8c 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -14,16 +14,76 @@ romstage-y += early_setup.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c -$(obj)/hudson.bin: - python $(src)/southbridge/amd/agesa/hudson/hudson_fwm.py $(CONFIG_HUDSON_FWM_POSITION) $@ $(CONFIG_HUDSON_XHCI_FWM_FILE) $(CONFIG_HUDSON_IMC_FWM_FILE) "" +# ROMSIG At ROMBASE + 0x20000: +# +-----------+---------------+----------------+------------+ +# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | +# +-----------+---------------+----------------+------------+ +# EC ROM should be 64K aligned. +HUDSON_FWM_POSITION=$(shell printf %d $(CONFIG_HUDSON_FWM_POSITION)) + +ifeq ($(CONFIG_HUDSON_XHCI_FWM), y) +HUDSON_XHCI_POSITION=$(shell expr $(HUDSON_FWM_POSITION) + 128) +XHCI_FWM_SIZE=$(word 5,$(shell ls -l $(CONFIG_HUDSON_XHCI_FWM_FILE))) +else +HUDSON_XHCI_POSITION=0 +XHCI_FWM_SIZE=0 +endif + +ifeq ($(CONFIG_HUDSON_GEC_FWM), y) +HUDSON_GEC_POSITION=$(shell expr $(HUDSON_FWM_POSITION) + 128 + $(XHCI_FWM_SIZE)) +GEC_FWM_SIZE=$(word 5,$(shell ls -l $(CONFIG_HUDSON_GEC_FWM_FILE))) +else +HUDSON_GEC_POSITION=0 +GEC_FWM_SIZE=0 +endif + +ifeq ($(CONFIG_HUDSON_IMC_FWM), y) +HUDSON_IMC_POSITION_UNALIGN=$(shell expr $(HUDSON_FWM_POSITION) + 256 + $(XHCI_FWM_SIZE) + $(GEC_FWM_SIZE) + 65535) +HUDSON_IMC_POSITION=$(shell expr $(HUDSON_IMC_POSITION_UNALIGN) - $(HUDSON_IMC_POSITION_UNALIGN) % 65536) +else +HUDSON_IMC_POSITION=0 +endif + +$(obj)/hudson_romsig.bin: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ + $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ + $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) \ + $(obj)/config.h + echo " Hudson FW $@" + for fwm in 1437226410 \ + $(HUDSON_IMC_POSITION) \ + $(HUDSON_GEC_POSITION) \ + $(HUDSON_XHCI_POSITION) ; do \ + echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 0x100, $$1/0x100 % 0x100, $$1/0x10000 % 0x100, $$1/0x1000000);}'; \ + done > $@ ifeq ($(CONFIG_HUDSON_FWM), y) cbfs-files-y += hudson/fwm -hudson/fwm-file := $(obj)/hudson.bin -hudson/fwm-position := $(CONFIG_HUDSON_FWM_POSITION) +hudson/fwm-file := $(obj)/hudson_romsig.bin +hudson/fwm-position := $(HUDSON_FWM_POSITION) hudson/fwm-type := raw endif +ifeq ($(CONFIG_HUDSON_XHCI_FWM), y) +cbfs-files-y += hudson/xhci +hudson/xhci-file := $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) +hudson/xhci-position := $(HUDSON_XHCI_POSITION) +hudson/xhci-type := raw +endif + +ifeq ($(CONFIG_HUDSON_IMC_FWM), y) +cbfs-files-y += hudson/imc +hudson/imc-file := $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) +hudson/imc-position := $(HUDSON_IMC_POSITION) +hudson/imc-type := raw +endif + +ifeq ($(CONFIG_HUDSON_GEC_FWM), y) +cbfs-files-y += hudson/gec +hudson/gec-file := $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) +hudson/gec-position := $(HUDSON_GEC_POSITION) +hudson/gec-type := raw +endif + #ifeq ($(CONFIG_HUDSON_SATA_AHCI), y) ifdef CONFIG_HUDSON_AHCI_ROM stripped_ahci_rom_id = $(call strip_quotes,$(CONFIG_AHCI_ROM_ID)) diff --git a/src/southbridge/amd/agesa/hudson/hudson_fwm.py b/src/southbridge/amd/agesa/hudson/hudson_fwm.py deleted file mode 100644 index ad60b3b..0000000 --- a/src/southbridge/amd/agesa/hudson/hudson_fwm.py +++ /dev/null @@ -1,64 +0,0 @@ -import sys, os, re -import struct -from Queue import Queue - -def main(start_addr, file_name, xhci_name, imc_name, gec_name): - fwm_sig = 0x55AA55AA # Hudson-2/3/4 firmware signature - fwm_header_len = 0x10 # 55AA55AA, imc_off, gec_off, xhci_off - - if not os.path.exists(xhci_name): - print "XHCI firmware %s does not exist\n" % xhci_name - sys.exit(1) - if not os.path.exists(imc_name): - print "IMC firmware %s does not exist\n" % imc_name - sys.exit(1) - - f = open(file_name, "w") - print "write to file " + file_name - - imc_offset = 0x10000 # 64K Bytes offset, hardcoded - imc_addr = start_addr + imc_offset; #startaddr + 0x10000 - gec_offset = 0 #TODO - gec_addr = 0 #TODO - xhci_addr = start_addr + fwm_header_len #ROMSIG take 0x10 bytes - - format="I" # one unsigned integer - data=struct.pack(format, fwm_sig) - f.write(data) - data=struct.pack(format, imc_addr) - f.write(data) - data=struct.pack(format, gec_addr) - f.write(data) - data=struct.pack(format, xhci_addr) - f.write(data) - - fwm_content = open(xhci_name).read() - f.write(fwm_content) - - imc_content = open(imc_name).read() - f.seek(0) - f.seek(imc_offset) - f.write(imc_content) -# if os.path.exists(gec_name): -# gec_conent = open(gec_name).read() -# f.seek(0) -# f.seek(gec_offset) -# f.write(gec_content) - - f.close() - print "done\n" - - -if __name__ == '__main__': - if (len(sys.argv) < 6): - print "\nUsage: %s <rom_addr> <rom_file> <xhci_rom> <imc_rom> <gec_rom>\n" % sys.argv[0] - print "Example: %s 0xFFF20000 hudson.bin xhci.bin imc.bin gec.bin\n" % sys.argv[0] - sys.exit(1) - rom_addr = int(sys.argv[1], 16) - rom_file = sys.argv[2] - xhci_file = sys.argv[3] - imc_file = sys.argv[4] - gec_file = sys.argv[5] - print "%x %s %s %s %s" % (rom_addr, rom_file, xhci_file, imc_file, gec_file) - - main(rom_addr, rom_file, xhci_file, imc_file, gec_file)

1 0

Patch set updated for coreboot: 5e27a97 AMD Hudson: Move the combining firmware from Python to sh.
by Zheng Bao 22 Aug '12

22 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1417 -gerrit commit 5e27a9767607e32a2f3d6368226df2a97fd87887 Author: zbao <fishbaozi(a)gmail.com> Date: Wed Aug 22 16:25:09 2012 +0800 AMD Hudson: Move the combining firmware from Python to sh. Maybe sooner or later python is not a default tools to build coreboot. Most of the work is done by awk now. GNU extension of gawk is not used, isn't? echo, expr, printf, cat, awk, test, mv are the external tools. If XHCI, IMC or GEC firmware is not available and not defined, this script can skip integrating them. Change-Id: I9944b22b0b755672a46d472c355d138abafd6393 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/southbridge/amd/agesa/hudson/Makefile.inc | 67 ++++++++++++++++++++++++-- src/southbridge/amd/agesa/hudson/hudson_fwm.py | 64 ------------------------ 2 files changed, 63 insertions(+), 68 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 19ffae1..33275a5 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -14,16 +14,75 @@ romstage-y += early_setup.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c -$(obj)/hudson.bin: - python $(src)/southbridge/amd/agesa/hudson/hudson_fwm.py $(CONFIG_HUDSON_FWM_POSITION) $@ $(CONFIG_HUDSON_XHCI_FWM_FILE) $(CONFIG_HUDSON_IMC_FWM_FILE) "" +# ROMSIG At ROMBASE + 0x20000: +# +-----------+---------------+----------------+------------+ +# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | +# +-----------+---------------+----------------+------------+ +# EC ROM should be 64K aligned. +HUDSON_FWM_POSITION=$(shell printf %d $(CONFIG_HUDSON_FWM_POSITION)) + +ifeq ($(CONFIG_HUDSON_XHCI_FWM), y) +HUDSON_XHCI_POSITION=$(shell expr $(HUDSON_FWM_POSITION) + 128) +XHCI_FWM_SIZE=$(word 5,$(shell ls -l $(CONFIG_HUDSON_XHCI_FWM_FILE))) +else +HUDSON_XHCI_POSITION=0 +XHCI_FWM_SIZE=0 +endif + +ifeq ($(CONFIG_HUDSON_GEC_FWM), y) +HUDSON_GEC_POSITION=$(shell expr $(HUDSON_FWM_POSITION) + 128 + $(XHCI_FWM_SIZE)) +GEC_FWM_SIZE=$(word 5,$(shell ls -l $(CONFIG_HUDSON_GEC_FWM_FILE))) +else +HUDSON_GEC_POSITION=0 +GEC_FWM_SIZE=0 +endif + +ifeq ($(CONFIG_HUDSON_IMC_FWM), y) +HUDSON_IMC_POSITION_UNALIGN=$(shell expr $(HUDSON_FWM_POSITION) + 256 + $(XHCI_FWM_SIZE) + $(GEC_FWM_SIZE) + 65535) +HUDSON_IMC_POSITION=$(shell expr $(HUDSON_IMC_POSITION_UNALIGN) - $(HUDSON_IMC_POSITION_UNALIGN) % 65536) +else +HUDSON_IMC_POSITION=0 +endif + +$(obj)/hudson_romsig.bin: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ + $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ + $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) + echo " Hudson FW $@" + for fwm in 1437226410 \ + $(HUDSON_IMC_POSITION) \ + $(HUDSON_GEC_POSITION) \ + $(HUDSON_XHCI_POSITION) ; do \ + echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 0x100, $$1/0x100 % 0x100, $$1/0x10000 % 0x100, $$1/0x1000000);}'; \ + done > $@ ifeq ($(CONFIG_HUDSON_FWM), y) cbfs-files-y += hudson/fwm -hudson/fwm-file := $(obj)/hudson.bin -hudson/fwm-position := $(CONFIG_HUDSON_FWM_POSITION) +hudson/fwm-file := $(obj)/hudson_romsig.bin +hudson/fwm-position := $(HUDSON_FWM_POSITION) hudson/fwm-type := raw endif +ifeq ($(CONFIG_HUDSON_XHCI_FWM), y) +cbfs-files-y += hudson/xhci +hudson/xhci-file := $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) +hudson/xhci-position := $(HUDSON_XHCI_POSITION) +hudson/xhci-type := raw +endif + +ifeq ($(CONFIG_HUDSON_IMC_FWM), y) +cbfs-files-y += hudson/imc +hudson/imc-file := $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) +hudson/imc-position := $(HUDSON_IMC_POSITION) +hudson/imc-type := raw +endif + +ifeq ($(CONFIG_HUDSON_GEC_FWM), y) +cbfs-files-y += hudson/gec +hudson/gec-file := $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) +hudson/gec-position := $(HUDSON_GEC_POSITION) +hudson/gec-type := raw +endif + #ifeq ($(CONFIG_HUDSON_SATA_AHCI), y) ifdef CONFIG_HUDSON_AHCI_ROM stripped_ahci_rom_id = $(call strip_quotes,$(CONFIG_AHCI_ROM_ID)) diff --git a/src/southbridge/amd/agesa/hudson/hudson_fwm.py b/src/southbridge/amd/agesa/hudson/hudson_fwm.py deleted file mode 100644 index ad60b3b..0000000 --- a/src/southbridge/amd/agesa/hudson/hudson_fwm.py +++ /dev/null @@ -1,64 +0,0 @@ -import sys, os, re -import struct -from Queue import Queue - -def main(start_addr, file_name, xhci_name, imc_name, gec_name): - fwm_sig = 0x55AA55AA # Hudson-2/3/4 firmware signature - fwm_header_len = 0x10 # 55AA55AA, imc_off, gec_off, xhci_off - - if not os.path.exists(xhci_name): - print "XHCI firmware %s does not exist\n" % xhci_name - sys.exit(1) - if not os.path.exists(imc_name): - print "IMC firmware %s does not exist\n" % imc_name - sys.exit(1) - - f = open(file_name, "w") - print "write to file " + file_name - - imc_offset = 0x10000 # 64K Bytes offset, hardcoded - imc_addr = start_addr + imc_offset; #startaddr + 0x10000 - gec_offset = 0 #TODO - gec_addr = 0 #TODO - xhci_addr = start_addr + fwm_header_len #ROMSIG take 0x10 bytes - - format="I" # one unsigned integer - data=struct.pack(format, fwm_sig) - f.write(data) - data=struct.pack(format, imc_addr) - f.write(data) - data=struct.pack(format, gec_addr) - f.write(data) - data=struct.pack(format, xhci_addr) - f.write(data) - - fwm_content = open(xhci_name).read() - f.write(fwm_content) - - imc_content = open(imc_name).read() - f.seek(0) - f.seek(imc_offset) - f.write(imc_content) -# if os.path.exists(gec_name): -# gec_conent = open(gec_name).read() -# f.seek(0) -# f.seek(gec_offset) -# f.write(gec_content) - - f.close() - print "done\n" - - -if __name__ == '__main__': - if (len(sys.argv) < 6): - print "\nUsage: %s <rom_addr> <rom_file> <xhci_rom> <imc_rom> <gec_rom>\n" % sys.argv[0] - print "Example: %s 0xFFF20000 hudson.bin xhci.bin imc.bin gec.bin\n" % sys.argv[0] - sys.exit(1) - rom_addr = int(sys.argv[1], 16) - rom_file = sys.argv[2] - xhci_file = sys.argv[3] - imc_file = sys.argv[4] - gec_file = sys.argv[5] - print "%x %s %s %s %s" % (rom_addr, rom_file, xhci_file, imc_file, gec_file) - - main(rom_addr, rom_file, xhci_file, imc_file, gec_file)

1 0

Patch set updated for coreboot: e697043 AMD Hudson: Move the combining firmware from Python to sh.
by Zheng Bao 22 Aug '12

22 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1417 -gerrit commit e697043651a8ad40132df51dfccabb49bc091798 Author: zbao <fishbaozi(a)gmail.com> Date: Wed Aug 22 14:18:01 2012 +0800 AMD Hudson: Move the combining firmware from Python to sh. Maybe sooner or later python is not a default tools to build coreboot. Most of the work is done by awk now. GNU extension of gawk is not used, isn't? echo, expr, printf, cat, awk, test, mv are the external tools. If XHCI, IMC or GEC firmware is not available and not defined, this script can skip integrating them. Change-Id: I9944b22b0b755672a46d472c355d138abafd6393 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/southbridge/amd/agesa/hudson/Makefile.inc | 67 ++++++++++++++++++++++++-- src/southbridge/amd/agesa/hudson/hudson_fwm.py | 64 ------------------------ 2 files changed, 63 insertions(+), 68 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 19ffae1..db72acf 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -14,16 +14,75 @@ romstage-y += early_setup.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c -$(obj)/hudson.bin: - python $(src)/southbridge/amd/agesa/hudson/hudson_fwm.py $(CONFIG_HUDSON_FWM_POSITION) $@ $(CONFIG_HUDSON_XHCI_FWM_FILE) $(CONFIG_HUDSON_IMC_FWM_FILE) "" +# ROMSIG At ROMBASE + 0x20000: +# +-----------+---------------+----------------+------------+ +# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | +# +-----------+---------------+----------------+------------+ +# EC ROM should be 64K aligned. +HUDSON_FWM_POSITION=$(shell printf %d $(CONFIG_HUDSON_FWM_POSITION)) + +ifeq ($(CONFIG_HUDSON_XHCI_FWM), y) +HUDSON_XHCI_POSITION=$(shell expr $(HUDSON_FWM_POSITION) + 128) +XHCI_FWM_SIZE=$(word 5,$(shell ls -l $(CONFIG_HUDSON_XHCI_FWM_FILE))) +else +HUDSON_XHCI_POSITION=0 +XHCI_FWM_SIZE=0 +endif + +ifeq ($(CONFIG_HUDSON_GEC_FWM), y) +HUDSON_GEC_POSITION=$(shell expr $(HUDSON_FWM_POSITION) + 128 + $(XHCI_FWM_SIZE)) +GEC_FWM_SIZE=$(word 5,$(shell ls -l $(CONFIG_HUDSON_GEC_FWM_FILE))) +else +HUDSON_GEC_POSITION=0 +GEC_FWM_SIZE=0 +endif + +ifeq ($(CONFIG_HUDSON_IMC_FWM), y) +HUDSON_IMC_POSITION_UNALIGN=$(shell expr $(HUDSON_FWM_POSITION) + 256 + $(XHCI_FWM_SIZE) + $(GEC_FWM_SIZE) + 65535) +HUDSON_IMC_POSITION=$(shell expr $(HUDSON_IMC_POSITION_UNALIGN) - $(HUDSON_IMC_POSITION_UNALIGN) % 65536) +else +HUDSON_IMC_POSITION=0 +endif + +$(obj)/hudson_romsig.bin: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ + $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ + $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) + echo " Hudson FW $@" + for fwm in 1437226410 \ + $(HUDSON_IMC_POSITION) \ + $(HUDSON_GEC_POSITION) \ + $(HUDSON_XHCI_POSITION) ; do \ + echo $$fwm | awk '{printf ("%c%c%c%c", $$1 % 0x100, $$1/0x100 % 0x100, $$1/0x10000 % 0x100, $$1/0x1000000);}'; \ + done > $@ ifeq ($(CONFIG_HUDSON_FWM), y) cbfs-files-y += hudson/fwm -hudson/fwm-file := $(obj)/hudson.bin -hudson/fwm-position := $(CONFIG_HUDSON_FWM_POSITION) +hudson/fwm-file := $(obj)/hudson_romsig.bin +hudson/fwm-position := $(HUDSON_FWM_POSITION) hudson/fwm-type := raw endif +ifeq ($(CONFIG_HUDSON_XHCI_FWM), y) +cbfs-files-y += hudson/xhci +hudson/xhci-file := $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) +hudson/xhci-position := $(HUDSON_XHCI_POSITION) +hudson/xhci-type := raw +endif + +ifeq ($(CONFIG_HUDSON_IMC_FWM), y) +cbfs-files-y += hudson/imc +hudson/imc-file := $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) +hudson/imc-position := $(HUDSON_IMC_POSITION) +hudson/imc-type := raw +endif + +ifeq ($(CONFIG_HUDSON_GEC_FWM), y) +cbfs-files-y += hudson/gec +hudson/gec-file := $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) +hudson/gec-position := $(HUDSON_GEC_POSITION) +hudson/gec-type := raw +endif + #ifeq ($(CONFIG_HUDSON_SATA_AHCI), y) ifdef CONFIG_HUDSON_AHCI_ROM stripped_ahci_rom_id = $(call strip_quotes,$(CONFIG_AHCI_ROM_ID)) diff --git a/src/southbridge/amd/agesa/hudson/hudson_fwm.py b/src/southbridge/amd/agesa/hudson/hudson_fwm.py deleted file mode 100644 index ad60b3b..0000000 --- a/src/southbridge/amd/agesa/hudson/hudson_fwm.py +++ /dev/null @@ -1,64 +0,0 @@ -import sys, os, re -import struct -from Queue import Queue - -def main(start_addr, file_name, xhci_name, imc_name, gec_name): - fwm_sig = 0x55AA55AA # Hudson-2/3/4 firmware signature - fwm_header_len = 0x10 # 55AA55AA, imc_off, gec_off, xhci_off - - if not os.path.exists(xhci_name): - print "XHCI firmware %s does not exist\n" % xhci_name - sys.exit(1) - if not os.path.exists(imc_name): - print "IMC firmware %s does not exist\n" % imc_name - sys.exit(1) - - f = open(file_name, "w") - print "write to file " + file_name - - imc_offset = 0x10000 # 64K Bytes offset, hardcoded - imc_addr = start_addr + imc_offset; #startaddr + 0x10000 - gec_offset = 0 #TODO - gec_addr = 0 #TODO - xhci_addr = start_addr + fwm_header_len #ROMSIG take 0x10 bytes - - format="I" # one unsigned integer - data=struct.pack(format, fwm_sig) - f.write(data) - data=struct.pack(format, imc_addr) - f.write(data) - data=struct.pack(format, gec_addr) - f.write(data) - data=struct.pack(format, xhci_addr) - f.write(data) - - fwm_content = open(xhci_name).read() - f.write(fwm_content) - - imc_content = open(imc_name).read() - f.seek(0) - f.seek(imc_offset) - f.write(imc_content) -# if os.path.exists(gec_name): -# gec_conent = open(gec_name).read() -# f.seek(0) -# f.seek(gec_offset) -# f.write(gec_content) - - f.close() - print "done\n" - - -if __name__ == '__main__': - if (len(sys.argv) < 6): - print "\nUsage: %s <rom_addr> <rom_file> <xhci_rom> <imc_rom> <gec_rom>\n" % sys.argv[0] - print "Example: %s 0xFFF20000 hudson.bin xhci.bin imc.bin gec.bin\n" % sys.argv[0] - sys.exit(1) - rom_addr = int(sys.argv[1], 16) - rom_file = sys.argv[2] - xhci_file = sys.argv[3] - imc_file = sys.argv[4] - gec_file = sys.argv[5] - print "%x %s %s %s %s" % (rom_addr, rom_file, xhci_file, imc_file, gec_file) - - main(rom_addr, rom_file, xhci_file, imc_file, gec_file)

1 0

Patch merged into coreboot/master: 6b35914 Auto-declare chip_operations
by gerrit＠coreboot.org 22 Aug '12

22 Aug '12

the following patch was just integrated into master: commit 6b359140bea8ac94fdfdfe4b8d8dc1757350fe5e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Aug 21 11:37:11 2012 +0300 Auto-declare chip_operations The name is derived directly from the device path. Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Aug 21 11:08:41 2012, giving +1 Build-Tested: build bot (Jenkins) at Tue Aug 21 11:00:03 2012, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Wed Aug 22 05:06:41 2012, giving +2 See http://review.coreboot.org/1471 for details. -gerrit

1 0

← Newer
1
...
7
8
9
10
11
12
13
...
33
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot August 2012