coreboot August 2012

coreboot@coreboot.org

30 participants
321 discussions

Re: [coreboot] User interface on coreboot
by ron minnich 14 Aug '12

14 Aug '12

The plan, long ago, when it was still linuxbios, was that linux would be the basis of interaction. Back then we were booting linux out of flash faster than any known bios would put up a screen. We had tools (rdcmos etc.) to manipulate cmos. We even had commands to control overclocking from linux. So the interaction path was the linux shell. Then the bloat monster hit and the idea of linux as the firmware died. ron

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New patch to review for coreboot: eb39fd2 Support use of the compression option when adding payloads to cbfs.
by Dave Frodin 14 Aug '12

14 Aug '12

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1452 -gerrit commit eb39fd223f11259c12c6e44629b8f34de4312a77 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Tue Aug 14 11:01:53 2012 -0600 Support use of the compression option when adding payloads to cbfs. Change-Id: Ie77e8e1628d34f1a9e7a57e994bf2882c5e55e25 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- Makefile.inc | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 4c2bb4c..adc41bf 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -128,9 +128,10 @@ cbfs-files-handler= \ $(eval tmp-old-cbfs-file:=$(tmp-cbfs-file)) \ $(eval tmp-cbfs-file:=$(shell mktemp $(obj)/mainboard/$(MAINBOARDDIR)/cbfs-file.XXXXXX).out) \ $(call cbfs-files-processor-$(tmp-cbfs-method),$(tmp-old-cbfs-file),$(tmp-cbfs-file))) \ - $(eval cbfs-files += $(tmp-cbfs-file)|$(2)|$($(2)-type)|$($(2)-position)) \ + $(eval cbfs-files += $(tmp-cbfs-file)|$(2)|$($(2)-type)|$($(2)-compression)|$($(2)-position)) \ $(eval $(2)-name:=) \ $(eval $(2)-type:=) \ + $(eval $(2)-compression:=) \ $(eval $(2)-position:=) #######################################################################

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New patch to review for coreboot: 3cc2c6d Change to allow coreboot to use "add-payload" instead of "add" for payload images.
by Dave Frodin 14 Aug '12

14 Aug '12

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1451 -gerrit commit 3cc2c6d9b2afb8e0489b521252946b3a6a84e6bf Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Tue Aug 14 10:59:17 2012 -0600 Change to allow coreboot to use "add-payload" instead of "add" for payload images. The current code does some argument manipulation to detect when a stage is being added to cbfs. This same manipulation needs to be done when adding a payload. Change-Id: Ief4c4a81446c9437923cbbb1ce3fa90729317587 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/arch/x86/Makefile.inc | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 306f239..71d359f 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -61,8 +61,10 @@ extract_nth=$(word $(1), $(subst |, ,$(2))) ifneq ($(CONFIG_UPDATE_IMAGE),y) prebuild-files = \ $(foreach file,$(cbfs-files), \ - $(CBFSTOOL) $@.tmp add$(if $(filter stage,$(call extract_nth,3,$(file))),-stage) $(call extract_nth,1,$(file)) \ - $(call extract_nth,2,$(file)) $(if $(filter-out stage,$(call extract_nth,3,$(file))),$(call extract_nth,3,$(file))) \ + $(CBFSTOOL) $@.tmp \ + add$(if $(filter stage,$(call extract_nth,3,$(file))),-stage)$(if $(filter payload,$(call extract_nth,3,$(file))),-payload) \ + $(call extract_nth,1,$(file)) \ + $(call extract_nth,2,$(file)) $(if $(filter-out stage payload,$(call extract_nth,3,$(file))),$(call extract_nth,3,$(file))) \ $(call extract_nth,4,$(file)) &&) prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))

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Regarding How-To for new board support
by Andrey Gursky 14 Aug '12

14 Aug '12

Dear coreboot comunity, Anton encourages the russian speaking part of linux users to write to the list to get help of supporting a new mainboard. Did somebody write in the past? Maybe there are not a lot of people ready to try coreboot, because of: "Make changes to the board configuration, ACPI or IRQ routing etc etc until you find the proper settings. This can take from an hour of time to a few months based upon your coding skills and hardware issues." And this is the citation for "a new board with the *same* cpu family, chipset and superIO". Would you please be more precise, writing How-To? I own a Gigabyte ga-990xa-ud3 board [1], based on Northbridge: AMD 990X Southbridge: AMD SB950 SuperIO: ITE IT8720F BIOS: Macronix flash chip "MX25L3205" Link to the latest original BIOS-image: [2] I've attached the required... oh, the forum moderator has already removed this part of the conversation, where Anton said about what tools output is required. By the way, what can be read from the original BIOS image? Are there any tools for this? I've thought also of a following approach: would it be possible for author added support for a AMD 8xx/9xx based board to publish the output of tools, mentioned by Anton (flashrom, lspci -vv..., superiotool), so that one could compare this input with the ready code to see, what data is still missing and be able to ask for it? Kindly regards, Andrey [1] http://www.gigabyte.com/products/product-page.aspx?pid=3901 [2] http://download.gigabyte.eu/FileList/BIOS/mb_bios_ga-990xa-ud3_f12.exe P.S. I'll send superiotool output later.

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Patch merged into coreboot/master: fd32524 buildgcc: Update the toolchain patches version
by gerrit＠coreboot.org 14 Aug '12

14 Aug '12

the following patch was just integrated into master: commit fd325249a6d95c638fa9a0c0c4259cd4043d7422 Author: zbao <fishbaozi(a)gmail.com> Date: Wed Aug 8 18:45:07 2012 +0800 buildgcc: Update the toolchain patches version acpica 20120420, acpica-unix-20110922_no_unused_variables.patch is not used anymore. binutils 2.22. Change-Id: I58459bd2eba2ad752fc033e51ee0892e2e069a02 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Aug 8 11:17:32 2012, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Tue Aug 14 15:44:19 2012, giving +2 See http://review.coreboot.org/1424 for details. -gerrit

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Re: [coreboot] User interface on coreboot
by Alex G. 14 Aug '12

14 Aug '12

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 08/10/2012 03:09 AM, Lap Ngo Doan wrote: > Hi all, As you may know, when we enter to BIOS, we can use the > keyboard to change some settings such as : enable/disable > something, change boot devices priority ....It is kind of user > interface on BIOS. In the coreboot website, they said "*coreboot* > is a Free Software project aimed at *replacing the > proprietary**BIOS* This statement is unfortunately misleading. It's not our fault really. It comes from the tendency to name the firmware "BIOS", which is in fact hardware initialization, then the actual BIOS. Coreboot is the hardware initialization part. > If we want to add some interactions with hardware like BIOS > firmware provided us (use keyboard to enable/disable some > options....), how could we do it with coreboot? Keep those settings in NVRAM, and write a payload to read and modify NVRAM. libpayload is there for the taking; the biggest hurdle may be figuring out how to parse NVRAM (different hardware stores different settings in different places). You might also need to modify parts of coreboot to make it use NVRAM for settings. Some to most boards have a cmos.layout file. You can find a way to make that available to your payload. You have a bunch of options to play with. Then SeaBIOS can boot from CBFS, and you'd just have to use its boot menu to load your payload. For all others, there's debit bayou. This sounds like a cool project, and a nice way to get your hands dirty with coreboot, learn your way around. Alex -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQIcBAEBAgAGBQJQKDDgAAoJEL0kPHNPXJJKSdMP/jIJ5NMpaDSHydv1SVPOXmPt D4uuUogV+8sDk+dqaSoTfwpXlW9UMSaAXjFbMfoF+zA0iIU9uyNyVfzuVtabNRoO TsvhF7VM+UfIHsGoNBDdwAfdAqswdvx8gQ9RlpsUv9jTI9uC00iX/FWB30NKI5Sf oic4kxqTkU5+Akhz3htk0Hn71ZozmdaNy/xS50X1bMeeiYRSEZMsCVNX9KR2rmHX P2fTA697xXkpv1ZtnwvhTAZ4cbpPMsYaEBKOw41uF441XA0TmvV9qbHpG5NFOODz 1YueHPgieFXQzvV3gsFF/vBWcBe60CSId9WwlIJuWnMakBULXfVJWCAx3LCRpq5m /iiS188ENXQ24dSkKjmOcf4Hxdfbat+szZRW4dBFdx9/LKl6XaVsvVRDmcjsrqKu YbLxyJGRCWSXViE99Cf4/jcSB20w8+wLwWgfqVSagj0A2RGD6V1l6j/YyK0vj02j BVko7oKial4NQczBT7JzExhw20+HmYNE4b0VZtTwRGqjI3aVn02Y+bk8c+sAx0th p5r5FLAsq01Z7TyoKnPVMUenTWFP2FsV9uEFEHqx1fAXAkBp/G9xaHVaQGhcQW+y Gp1p0whgVIOJHvqvH7YVrXwjTf01FY3unwTnZhZnEFsZ8I+yvz7zKnOHDgCfFv0s twX/0lgHUW2HDSZ1NwcD =Dftw -----END PGP SIGNATURE-----

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Documenting the process of Timestamp collection during romstage
by Alex G. 14 Aug '12

14 Aug '12

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 The idea of collecting timestamps during romstage is awesome. the only problem is that the code that does that is completely undocumented. Some stuff you figure out by looking at the code. Then there's timestamp_init(tsc_t), whose argument is read by the mainboard from some mysterious registers. Then there's also: build/lib/timestamp.romstage.o: In function `timestamp_init': /home/mrnuke/Sources/coreboot/src/lib/timestamp.c:40: undefined reference to `cbmem_add' build/lib/timestamp.romstage.o: In function `timestamp_add': /home/mrnuke/Sources/coreboot/src/lib/timestamp.c:58: undefined reference to `cbmem_find' Can someone please explain the proper procedure of getting timestamp collection running. I'll even sacrifice myself and add doxygen-style documentation for the next poor fella trying to implement this. Alex -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQIcBAEBAgAGBQJQKd/IAAoJEL0kPHNPXJJKwQkP/jcz93TZXyCkg9vJMixk5vQB CGifXjPcJGyAE0IfFZZivTk4mKDt6KWuFYDRHmtK4zcEaW/u3j8JBgTq2/QSbsS9 7z93BuRg4ei3HeTvxq5mEmRu/F3cikdHew17pZcLaX+4uuCli76ZnUVNachpIpwo f6j5imnoLGGAmc5xdUhivZ+AGtpgFLPBWyksikpiXdmdPJAV8WT5j6G8sIMMy7Ji RStOR+/zYEvpadGk76+RJ1uumpmhPWWS6eeSjabJ2wn65zaOzqmejRjR1tVHDeJm v2pgciqNxr8c8Ch4YKwFjkJGanhe7EoI3GmW82WnzvzeVLatEBrVEtc1WaxcMx47 JNRCuJGG7TiaWnANYBlKEdWv6QQ1ZzaVvUfanzls8m9SDDlGElJFEGEBlp/4SpGR PaCAzGRikf+bPFQ43tS2vl0kY7BIIdT0huvC/mrWNFkx+ubvRUeatp1nTLwoZhXX 73BLNw7Vp7yXU/ngknSlQ8XlZBoCIiM+MAec2BLnpvUDI7JAj2XuiJYaVplC92Gw UzzkC+HtcAFIdUuKU3iEYs+0rjm3LSNGBA7AgPe/O+TMeRAehLIjW8+WXIDMItXZ t2jljDpR8va0vKeEuXbedhds+raCJyvxmesbmQpUlK1yplSlJMlHdHFL6Mj9EoZn 67D/FNswHk/xLqWh8QuU =LP+r -----END PGP SIGNATURE-----

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Patch merged into coreboot/master: b0062a0 AMD Hudson: Enable HD audio
by gerrit＠coreboot.org 13 Aug '12

13 Aug '12

the following patch was just integrated into master: commit b0062a0d262b1a443bbe9dd7b4e124b2b6cb0344 Author: zbao <fishbaozi(a)gmail.com> Date: Thu Aug 9 15:08:20 2012 +0800 AMD Hudson: Enable HD audio Something about HD audio was scrubbed. Take it back. Change-Id: I0be96fd103f3ebd4e8c7ef09a184b71aa34ee3fd Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Aug 9 07:42:10 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Mon Aug 13 18:57:01 2012, giving +2 See http://review.coreboot.org/1427 for details. -gerrit

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Trac reminder: list of new ticket(s)
by coreboot tracker 13 Aug '12

13 Aug '12

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Re: [coreboot] [SeaBIOS] Compiling SeaBIOS for coreboot has problems with its ACPI code
by Michael S. Tsirkin 12 Aug '12

12 Aug '12

On Thu, Aug 09, 2012 at 02:59:45AM +0000, Moore, Robert wrote: > > > >-----Original Message----- > >From: Kevin O'Connor [mailto:kevin@koconnor.net] > >Sent: Wednesday, August 08, 2012 7:23 PM > >To: Moore, Robert > >Cc: Michael S. Tsirkin; Idwer Vollering; seabios(a)seabios.org; Tang, Feng; > >coreboot(a)coreboot.org > >Subject: Re: [SeaBIOS] Compiling SeaBIOS for coreboot has problems with its > >ACPI code > > > >On Tue, Aug 07, 2012 at 07:34:37PM +0000, Moore, Robert wrote: > >> This is very interesting. If I understand correctly, you are using a > >> utility plus various directives to generate tables of AML offsets -- > >> presumably in order to dynamically change AML values, correct? > > > >Yes - exactly. We started off completely generating the SSDT > >dynamically, but that got awkward when we needed to generate Processor > >objects dynamically. So, we compiled an SSDT as template and then > >patched it. It was fragile to hard-code the offsets, so a tool was > >written to parse the IASL output and generate the offsets > >automatically. > > > >I'm CC'ing the coreboot list - they have also been doing SSDT runtime > >generation. > > > >> I have to say that I have not seen anything like this, from any BIOS > >vendor. > >> > >> > By the way, is there interest in adding some of the functionality that > >> > we get by parsing the listing to iasl directly? > >> > >> We are always interested in adding features to make the compiler > >> more useful. What would you suggest? > > > >The tool currently generates offsets and can rename the Amlcode[] > >variable to something more unique. I'm sure additional features could > >be thought up. > > > >-Kevin > > > Here are additional thoughts and questions that I sent out earlier today: > > > > > >From what we have seen, standard BIOS code often modifies the AML on the fly (before the OS gets the ACPI tables) to handle the various setup options and other things. Some vendors do this better than others (we've seen checksum errors because of this, as well as package length issues because, for example, a byte constant is replaced by a dword constant but there is no room for the 32-bit value.) > > Obviously, the iASL compiler knows the offset of not only the start of every ASL statement, but also the start of every argument of every ASL statement. > > What we would be willing to provide is a new type of output file that provides arrays of offsets for you to use when modifying the AML. Something like this should be useful for your project, as well as standard BIOS code that needs this information as well. > > The -sc option for iASL already provides a limited version of this, but only at the statement level with offsets within a trailing comment field: > > /* > * 10....{ > * 11.... Method (MAIN, 0, NotSerialized) > */ > unsigned char DSDT_Template_MAIN [] = > { > 0x14,0x08,0x4D,0x41,0x49,0x4E,0x00, /* 00000023 "..MAIN." */ > > /* > * 12.... { > * 13.... Return (Zero) > */ > 0xA4,0x00, /* 00000025 ".." */ > > A new type of output file could instead create arrays of offsets, one offset per ASL term (statement or argument). The format could be something like one array per ASL statement or one array per method. You could then pick and choose which of these arrays you want to use/include into your BIOS code. > > Does this sound like it would solve your issues? > > Thanks, > Bob Hmm. How would C code know which of the statements it needs? For example, we could have many Return(Zero) statements but only want to patch some of them. Would it be possible to allow some tags in the AML code that specifies which offsets to extract, and how to name the arrays? It would also be useful to specify the array names for the AML code, to avoid dependencies between C code and makefiles. For example, code could look like this: /* Pull in required macros, also allows iasl to figure out it is not in compatibility mode. */ #include <acpi-extract.h> /* Put all code in this definition block in AmlCode array */ ACPI_EXTRACT_CODE(AmlCode) DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPCIHP", 0x1) Name (_S4, /* Put offset of next argument in acpi_s4_pkg array */ ACPI_EXTRACT_OFFSET(acpi_s4_pkg) Package (0x04) { 0x2, /* PM1a_CNT.SLP_TYP */ 0x2, /* PM1b_CNT.SLP_TYP */ Zero, /* reserved */ Zero /* reserved */ }) One other thing to note about our scripts is that offsets are often small, our scripts make the array the correct type (char,short,int,long) to make it fit, to avoid wasting memory. You might want to do the same. -- MST

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coreboot August 2012