coreboot August 2012

coreboot@coreboot.org

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New patch to review for coreboot: 009934f coreinfo: fix build error (TRIVIAL)
by Alexandru Gagniuc 15 Aug '12

15 Aug '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1453 -gerrit commit 009934f7822fa6eefeb0f2e74aaee29bc4048348 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Aug 15 06:36:00 2012 -0500 coreinfo: fix build error (TRIVIAL) Changes to libpayload, and lack of maintenance to coreinfo, and it no longer builds. Fix that. Change-Id: I03497880671f42b5aeb6db08ddf6ce2acd243a18 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- payloads/coreinfo/coreboot_module.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c index 77a4bb2..e5ba50f 100644 --- a/payloads/coreinfo/coreboot_module.c +++ b/payloads/coreinfo/coreboot_module.c @@ -142,7 +142,7 @@ static void parse_mainboard(unsigned char *ptr) { struct cb_mainboard *mb = (struct cb_mainboard *)ptr; - strncpy(cb_info.vendor, cb_mb_vendor_part(mb), sizeof(cb_info.vendor) - 1); + strncpy(cb_info.vendor, cb_mb_vendor_string(mb), sizeof(cb_info.vendor) - 1); strncpy(cb_info.part, cb_mb_part_string(mb), sizeof(cb_info.part) - 1); }

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Patch set updated for coreboot: fd5a9cd AMD Hudson: Move the combining firmware from Python to Makefile
by Zheng Bao 15 Aug '12

15 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1417 -gerrit commit fd5a9cdb5e6d4d08f44f36a402e0f258e00ff56e Author: zbao <fishbaozi(a)gmail.com> Date: Wed Aug 15 19:59:35 2012 +0800 AMD Hudson: Move the combining firmware from Python to Makefile Maybe sooner or later python is not a default tools to build coreboot. Most of the work is done by awk now. GNU extension of gawk is not used, isn't? cat, awk, test, mv are the external tools. If XHCI or IMC firmware is not available and not defined, this script can skip integrating them. Change-Id: I9944b22b0b755672a46d472c355d138abafd6393 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/southbridge/amd/agesa/hudson/Makefile.inc | 67 +++++++++++++++++++++++++- src/southbridge/amd/agesa/hudson/hudson_fwm.py | 64 ------------------------ 2 files changed, 65 insertions(+), 66 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 19ffae1..f51cd8b 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -14,8 +14,71 @@ romstage-y += early_setup.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c -$(obj)/hudson.bin: - python $(src)/southbridge/amd/agesa/hudson/hudson_fwm.py $(CONFIG_HUDSON_FWM_POSITION) $@ $(CONFIG_HUDSON_XHCI_FWM_FILE) $(CONFIG_HUDSON_IMC_FWM_FILE) "" +# ROMSIG At ROMBASE + 0x20000: +# +-----------+---------------+----------------+------------+ +# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | +# +-----------+---------------+----------------+------------+ +# In our coreboot implementation, we concatenate the ROM images +# next to the ROMSIG. EC ROM should be 64K aligned. +# Final hudson.bin: +# +-----------+---------------+----------------+------------+ +# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | +# +-----------+---------------+----------------+------------+ +# | USB3 ROM | +# +---------------------------------------------------------+ +# | GEC ROM | +# +---------------------------------------------------------+ +# | EC ROM | +# +---------------------------------------------------------+ +# +$(obj)/hudson.bin: $(top)/$(strip $(patsubst "%", %, $(CONFIG_HUDSON_XHCI_FWM_FILE))) \ + $(top)/$(strip $(patsubst "%", %, $(CONFIG_HUDSON_IMC_FWM_FILE))) + echo " Hudson FW $@" + ( \ + echo $(CONFIG_HUDSON_FWM_POSITION) | LC_ALL=C awk ' \ + function cbstrtonum(str, n,ret,i,c,k) \ + { \ + str = substr(str, 3); \ + n = length(str); \ + ret = 0; \ + for (i = 1; i <= n; i++) { \ + c = substr(str, i, 1); \ + c = tolower(c); \ + k = index("123456789abcdef", c); \ + ret = ret * 16 + k; \ + } \ + return ret; \ + } \ + { \ + printf ("%d ", cbstrtonum($$1)); \ + } ' ; \ + for fwm in "$(CONFIG_HUDSON_IMC_FWM_FILE)" "$(CONFIG_HUDSON_GEC_FWM_FILE)" "$(CONFIG_HUDSON_XHCI_FWM_FILE)" ; do \ + if [ -z $$fwm ]; then \ + awk 'BEGIN {printf ("0 ");}'; \ + else \ + [ -r $$fwm ] || { echo "$$fwm not found"; exit 1; }; \ + ls -l $$fwm | awk '{printf("%d ", $$5);}'; \ + fi \ + done ) | \ + LC_ALL=C awk ' \ + function print_raw_dword(number) \ + { \ + printf ("%c%c%c%c", number % 0x100, number/0x100 % 0x100, number/0x10000 % 0x100, number/0x1000000); \ + } \ + { # $$1=ROMSIG address, $$2=EC_ROM_size, $$3=GEC_ROM_size, $$4=USB3_ROM_size \ + print_raw_dword(0x55AA55AA); \ + imc_offset = $$1 + 16 + $$3 + 65535; \ + imc_offset = imc_offset - (imc_offset) % 65536; #align 64K \ + if ($$2) print_raw_dword(imc_offset); else print_raw_dword(0); \ + if ($$3) print_raw_dword($$1 + 16 + $$3); else print_raw_dword(0); \ + if ($$4) print_raw_dword($$1 + 16); else print_raw_dword(0); \ + } ' > $@.tmp + [ -z $(CONFIG_HUDSON_XHCI_FWM_FILE) ] || cat $(CONFIG_HUDSON_XHCI_FWM_FILE) >> $@.tmp + [ -z $(CONFIG_HUDSON_GEC_FWM_FILE) ] || cat $(CONFIG_HUDSON_GEC_FWM_FILE) >> $@.tmp + [ -z $(CONFIG_HUDSON_IMC_FWM_FILE) ] || \ + { ls -l $@.tmp | awk '{ print $$5 }' | LC_ALL=C awk '{for (i=$$1; i<($$1+65535) - ($$1+65535)%65536; i++) {printf "%c", 255}}' >> $@.tmp ; \ + cat $(CONFIG_HUDSON_IMC_FWM_FILE) >> $@.tmp; } + mv -f $@.tmp $@ ifeq ($(CONFIG_HUDSON_FWM), y) cbfs-files-y += hudson/fwm diff --git a/src/southbridge/amd/agesa/hudson/hudson_fwm.py b/src/southbridge/amd/agesa/hudson/hudson_fwm.py deleted file mode 100644 index ad60b3b..0000000 --- a/src/southbridge/amd/agesa/hudson/hudson_fwm.py +++ /dev/null @@ -1,64 +0,0 @@ -import sys, os, re -import struct -from Queue import Queue - -def main(start_addr, file_name, xhci_name, imc_name, gec_name): - fwm_sig = 0x55AA55AA # Hudson-2/3/4 firmware signature - fwm_header_len = 0x10 # 55AA55AA, imc_off, gec_off, xhci_off - - if not os.path.exists(xhci_name): - print "XHCI firmware %s does not exist\n" % xhci_name - sys.exit(1) - if not os.path.exists(imc_name): - print "IMC firmware %s does not exist\n" % imc_name - sys.exit(1) - - f = open(file_name, "w") - print "write to file " + file_name - - imc_offset = 0x10000 # 64K Bytes offset, hardcoded - imc_addr = start_addr + imc_offset; #startaddr + 0x10000 - gec_offset = 0 #TODO - gec_addr = 0 #TODO - xhci_addr = start_addr + fwm_header_len #ROMSIG take 0x10 bytes - - format="I" # one unsigned integer - data=struct.pack(format, fwm_sig) - f.write(data) - data=struct.pack(format, imc_addr) - f.write(data) - data=struct.pack(format, gec_addr) - f.write(data) - data=struct.pack(format, xhci_addr) - f.write(data) - - fwm_content = open(xhci_name).read() - f.write(fwm_content) - - imc_content = open(imc_name).read() - f.seek(0) - f.seek(imc_offset) - f.write(imc_content) -# if os.path.exists(gec_name): -# gec_conent = open(gec_name).read() -# f.seek(0) -# f.seek(gec_offset) -# f.write(gec_content) - - f.close() - print "done\n" - - -if __name__ == '__main__': - if (len(sys.argv) < 6): - print "\nUsage: %s <rom_addr> <rom_file> <xhci_rom> <imc_rom> <gec_rom>\n" % sys.argv[0] - print "Example: %s 0xFFF20000 hudson.bin xhci.bin imc.bin gec.bin\n" % sys.argv[0] - sys.exit(1) - rom_addr = int(sys.argv[1], 16) - rom_file = sys.argv[2] - xhci_file = sys.argv[3] - imc_file = sys.argv[4] - gec_file = sys.argv[5] - print "%x %s %s %s %s" % (rom_addr, rom_file, xhci_file, imc_file, gec_file) - - main(rom_addr, rom_file, xhci_file, imc_file, gec_file)

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Patch set updated for coreboot: 2e4837d AMD Hudson: Move the combining firmware from Python to Makefile
by Zheng Bao 15 Aug '12

15 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1417 -gerrit commit 2e4837d931edb073ab3a439d860b7228b9c3a4b8 Author: zbao <fishbaozi(a)gmail.com> Date: Wed Aug 15 18:54:46 2012 +0800 AMD Hudson: Move the combining firmware from Python to Makefile Maybe sooner or later python is not a default tools to build coreboot. Most of the work is done by awk now. GNU extension of gawk is not used, isn't? cat, awk, test, mv are the external tools. If XHCI or IMC firmware is not available and not defined, this script can skip integrating them. Change-Id: I9944b22b0b755672a46d472c355d138abafd6393 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/southbridge/amd/agesa/hudson/Makefile.inc | 66 +++++++++++++++++++++++++- src/southbridge/amd/agesa/hudson/hudson_fwm.py | 64 ------------------------- 2 files changed, 64 insertions(+), 66 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 19ffae1..393c929 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -14,8 +14,70 @@ romstage-y += early_setup.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c -$(obj)/hudson.bin: - python $(src)/southbridge/amd/agesa/hudson/hudson_fwm.py $(CONFIG_HUDSON_FWM_POSITION) $@ $(CONFIG_HUDSON_XHCI_FWM_FILE) $(CONFIG_HUDSON_IMC_FWM_FILE) "" +# ROMSIG At ROMBASE + 0x20000: +# +-----------+---------------+----------------+------------+ +# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | +# +-----------+---------------+----------------+------------+ +# In our coreboot implementation, we concatenate the ROM images +# next to the ROMSIG. EC ROM should be 64K aligned. +# Final hudson.bin: +# +-----------+---------------+----------------+------------+ +# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | +# +-----------+---------------+----------------+------------+ +# | USB3 ROM | +# +---------------------------------------------------------+ +# | GEC ROM | +# +---------------------------------------------------------+ +# | EC ROM | +# +---------------------------------------------------------+ +# +$(obj)/hudson.bin: $(top)/$(strip $(patsubst "%", %, $(CONFIG_HUDSON_XHCI_FWM_FILE))) \ + $(top)/$(strip $(patsubst "%", %, $(CONFIG_HUDSON_IMC_FWM_FILE))) + echo " Hudson FW $@" + ( \ + echo $(CONFIG_HUDSON_FWM_POSITION) | LC_ALL=C awk ' \ + function cbstrtonum(str, n,ret,i,c,k) \ + { \ + str = substr(str, 3); \ + n = length(str); \ + ret = 0; \ + for (i = 1; i <= n; i++) { \ + c = substr(str, i, 1); \ + c = tolower(c); \ + k = index("123456789abcdef", c); \ + ret = ret * 16 + k; \ + } \ + return ret; \ + } \ + { \ + printf ("%d ", cbstrtonum($$1)); \ + } ' ; \ + for fwm in "$(CONFIG_HUDSON_IMC_FWM_FILE)" "$(CONFIG_HUDSON_GEC_FWM_FILE)" "$(CONFIG_HUDSON_XHCI_FWM_FILE)" ; do \ + if [ -z $$fwm ]; then \ + awk 'BEGIN {printf ("0 ");}'; \ + else \ + [ -r $$fwm ] || { echo "$$fwm not found"; exit 1; }; \ + ls -l $$fwm | awk '{printf("%d ", $$5);}'; \ + fi \ + done ) | \ + LC_ALL=C awk ' \ + function print_raw_dword(number) \ + { \ + printf ("%c%c%c%c", number % 0x100, number/0x100 % 0x100, number/0x10000 % 0x100, number/0x1000000); \ + } \ + { # $$1=ROMSIG address, $$2=EC_ROM_size, $$3=GEC_ROM_size, $$4=USB3_ROM_size \ + print_raw_dword(0x55AA55AA); \ + imc_offset = $$1 + 16 + $$3 + 65535; \ + imc_offset = imc_offset - (imc_offset) % 65536; #align 64K \ + if ($$2) print_raw_dword(imc_offset); else print_raw_dword(0); \ + if ($$3) print_raw_dword($$1 + 16 + $$3); else print_raw_dword(0); \ + if ($$4) print_raw_dword($$1 + 16); else print_raw_dword(0); \ + } ' > $@.tmp + [ -z $(CONFIG_HUDSON_XHCI_FWM_FILE) ] || cat $(CONFIG_HUDSON_XHCI_FWM_FILE) >> $@.tmp + [ -z $(CONFIG_HUDSON_GEC_FWM_FILE) ] || cat $(CONFIG_HUDSON_GEC_FWM_FILE) >> $@.tmp + ls -l $@.tmp | awk '{ print $$5 }' | LC_ALL=C awk '{for (i=$$1; i<($$1+65535) - ($$1+65535)%65536; i++) {printf "%c", 255}}' >> $@.tmp # fill stub to make EC ROM aligned. + [ -z $(CONFIG_HUDSON_IMC_FWM_FILE) ] || cat $(CONFIG_HUDSON_IMC_FWM_FILE) >> $@.tmp + mv -f $@.tmp $@ ifeq ($(CONFIG_HUDSON_FWM), y) cbfs-files-y += hudson/fwm diff --git a/src/southbridge/amd/agesa/hudson/hudson_fwm.py b/src/southbridge/amd/agesa/hudson/hudson_fwm.py deleted file mode 100644 index ad60b3b..0000000 --- a/src/southbridge/amd/agesa/hudson/hudson_fwm.py +++ /dev/null @@ -1,64 +0,0 @@ -import sys, os, re -import struct -from Queue import Queue - -def main(start_addr, file_name, xhci_name, imc_name, gec_name): - fwm_sig = 0x55AA55AA # Hudson-2/3/4 firmware signature - fwm_header_len = 0x10 # 55AA55AA, imc_off, gec_off, xhci_off - - if not os.path.exists(xhci_name): - print "XHCI firmware %s does not exist\n" % xhci_name - sys.exit(1) - if not os.path.exists(imc_name): - print "IMC firmware %s does not exist\n" % imc_name - sys.exit(1) - - f = open(file_name, "w") - print "write to file " + file_name - - imc_offset = 0x10000 # 64K Bytes offset, hardcoded - imc_addr = start_addr + imc_offset; #startaddr + 0x10000 - gec_offset = 0 #TODO - gec_addr = 0 #TODO - xhci_addr = start_addr + fwm_header_len #ROMSIG take 0x10 bytes - - format="I" # one unsigned integer - data=struct.pack(format, fwm_sig) - f.write(data) - data=struct.pack(format, imc_addr) - f.write(data) - data=struct.pack(format, gec_addr) - f.write(data) - data=struct.pack(format, xhci_addr) - f.write(data) - - fwm_content = open(xhci_name).read() - f.write(fwm_content) - - imc_content = open(imc_name).read() - f.seek(0) - f.seek(imc_offset) - f.write(imc_content) -# if os.path.exists(gec_name): -# gec_conent = open(gec_name).read() -# f.seek(0) -# f.seek(gec_offset) -# f.write(gec_content) - - f.close() - print "done\n" - - -if __name__ == '__main__': - if (len(sys.argv) < 6): - print "\nUsage: %s <rom_addr> <rom_file> <xhci_rom> <imc_rom> <gec_rom>\n" % sys.argv[0] - print "Example: %s 0xFFF20000 hudson.bin xhci.bin imc.bin gec.bin\n" % sys.argv[0] - sys.exit(1) - rom_addr = int(sys.argv[1], 16) - rom_file = sys.argv[2] - xhci_file = sys.argv[3] - imc_file = sys.argv[4] - gec_file = sys.argv[5] - print "%x %s %s %s %s" % (rom_addr, rom_file, xhci_file, imc_file, gec_file) - - main(rom_addr, rom_file, xhci_file, imc_file, gec_file)

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Patch set updated for coreboot: d4f8903 AMD Hudson: Move the combining firmware from Python to Makefile
by Zheng Bao 15 Aug '12

15 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1417 -gerrit commit d4f89036ff7bf3ee18d7ea697c3d8e15ccab31b4 Author: zbao <fishbaozi(a)gmail.com> Date: Wed Aug 15 18:15:58 2012 +0800 AMD Hudson: Move the combining firmware from Python to Makefile Maybe sooner or later python is not a default tools to build coreboot. Most of the work is done by awk now. GNU extension of gawk is not used, isn't? cat, awk, test, mv are the external tools. If XHCI or IMC firmware is not available and not defined, this script can skip integrating them. Change-Id: I9944b22b0b755672a46d472c355d138abafd6393 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/southbridge/amd/agesa/hudson/Makefile.inc | 66 +++++++++++++++++++++++++- src/southbridge/amd/agesa/hudson/hudson_fwm.py | 64 ------------------------- 2 files changed, 64 insertions(+), 66 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 19ffae1..3a690ce 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -14,8 +14,70 @@ romstage-y += early_setup.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c -$(obj)/hudson.bin: - python $(src)/southbridge/amd/agesa/hudson/hudson_fwm.py $(CONFIG_HUDSON_FWM_POSITION) $@ $(CONFIG_HUDSON_XHCI_FWM_FILE) $(CONFIG_HUDSON_IMC_FWM_FILE) "" +# ROMSIG At ROMBASE + 0x20000: +# +-----------+---------------+----------------+------------+ +# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | +# +-----------+---------------+----------------+------------+ +# In our coreboot implementation, we concatenate the ROM images +# next to the ROMSIG. EC ROM should be 64K aligned. +# Final hudson.bin: +# +-----------+---------------+----------------+------------+ +# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | +# +-----------+---------------+----------------+------------+ +# | USB3 ROM | +# +---------------------------------------------------------+ +# | GEC ROM | +# +---------------------------------------------------------+ +# | EC ROM | +# +---------------------------------------------------------+ +# +$(obj)/hudson.bin: $(top)/$(strip $(patsubst "%", %, $(CONFIG_HUDSON_XHCI_FWM_FILE))) \ + $(top)/$(strip $(patsubst "%", %, $(CONFIG_HUDSON_IMC_FWM_FILE))) + echo " Hudson FW $@" + ( \ + echo $(CONFIG_HUDSON_FWM_POSITION) | LC_ALL=C awk ' \ + function cbstrtonum(str, n,ret,i,c,k) \ + { \ + str = substr(str, 3); \ + n = length(str); \ + ret = 0; \ + for (i = 1; i <= n; i++) { \ + c = substr(str, i, 1); \ + c = tolower(c); \ + k = index("123456789abcdef", c); \ + ret = ret * 16 + k; \ + } \ + return ret; \ + } \ + { \ + printf ("%d ", cbstrtonum($$1)); \ + } ' ; \ + for fwm in "$(CONFIG_HUDSON_IMC_FWM_FILE)" "$(CONFIG_HUDSON_GEC_FWM_FILE)" "$(CONFIG_HUDSON_XHCI_FWM_FILE)" ; do \ + if [ -z $$fwm ]; then \ + awk 'BEGIN {printf ("0 ");}'; \ + else \ + [ -r $$fwm ] || { echo "$$fwm not found"; exit 1; }; \ + ls -l $$fwm | awk '{printf("%d ", $$5);}'; \ + fi \ + done ) | \ + awk ' \ + function print_raw_dword(number) \ + { \ + printf ("%c%c%c%c", number % 0x100, number/0x100 % 0x100, number/0x10000 % 0x100, number/0x1000000); \ + } \ + { # $$1=ROMSIG address, $$2=EC_ROM_size, $$3=GEC_ROM_size, $$4=USB3_ROM_size \ + print_raw_dword(0x55AA55AA); \ + imc_offset = $$1 + 16 + $$3 + 65535; \ + imc_offset = imc_offset - (imc_offset) % 65536; #align 64K \ + if ($$2) print_raw_dword(imc_offset); else print_raw_dword(0); \ + if ($$3) print_raw_dword($$1 + 16 + $$3); else print_raw_dword(0); \ + if ($$4) print_raw_dword($$1 + 16); else print_raw_dword(0); \ + } ' > $@.tmp + [ -z $(CONFIG_HUDSON_XHCI_FWM_FILE) ] || cat $(CONFIG_HUDSON_XHCI_FWM_FILE) >> $@.tmp + [ -z $(CONFIG_HUDSON_GEC_FWM_FILE) ] || cat $(CONFIG_HUDSON_GEC_FWM_FILE) >> $@.tmp + ls -l $@.tmp | awk '{ print $$5 }' | LC_ALL=C awk '{for (i=$$1; i<($$1+65535) - ($$1+65535)%65536; i++) {printf "%c", 255}}' >> $@.tmp # fill stub to make EC ROM aligned. + [ -z $(CONFIG_HUDSON_IMC_FWM_FILE) ] || cat $(CONFIG_HUDSON_IMC_FWM_FILE) >> $@.tmp + mv -f $@.tmp $@ ifeq ($(CONFIG_HUDSON_FWM), y) cbfs-files-y += hudson/fwm diff --git a/src/southbridge/amd/agesa/hudson/hudson_fwm.py b/src/southbridge/amd/agesa/hudson/hudson_fwm.py deleted file mode 100644 index ad60b3b..0000000 --- a/src/southbridge/amd/agesa/hudson/hudson_fwm.py +++ /dev/null @@ -1,64 +0,0 @@ -import sys, os, re -import struct -from Queue import Queue - -def main(start_addr, file_name, xhci_name, imc_name, gec_name): - fwm_sig = 0x55AA55AA # Hudson-2/3/4 firmware signature - fwm_header_len = 0x10 # 55AA55AA, imc_off, gec_off, xhci_off - - if not os.path.exists(xhci_name): - print "XHCI firmware %s does not exist\n" % xhci_name - sys.exit(1) - if not os.path.exists(imc_name): - print "IMC firmware %s does not exist\n" % imc_name - sys.exit(1) - - f = open(file_name, "w") - print "write to file " + file_name - - imc_offset = 0x10000 # 64K Bytes offset, hardcoded - imc_addr = start_addr + imc_offset; #startaddr + 0x10000 - gec_offset = 0 #TODO - gec_addr = 0 #TODO - xhci_addr = start_addr + fwm_header_len #ROMSIG take 0x10 bytes - - format="I" # one unsigned integer - data=struct.pack(format, fwm_sig) - f.write(data) - data=struct.pack(format, imc_addr) - f.write(data) - data=struct.pack(format, gec_addr) - f.write(data) - data=struct.pack(format, xhci_addr) - f.write(data) - - fwm_content = open(xhci_name).read() - f.write(fwm_content) - - imc_content = open(imc_name).read() - f.seek(0) - f.seek(imc_offset) - f.write(imc_content) -# if os.path.exists(gec_name): -# gec_conent = open(gec_name).read() -# f.seek(0) -# f.seek(gec_offset) -# f.write(gec_content) - - f.close() - print "done\n" - - -if __name__ == '__main__': - if (len(sys.argv) < 6): - print "\nUsage: %s <rom_addr> <rom_file> <xhci_rom> <imc_rom> <gec_rom>\n" % sys.argv[0] - print "Example: %s 0xFFF20000 hudson.bin xhci.bin imc.bin gec.bin\n" % sys.argv[0] - sys.exit(1) - rom_addr = int(sys.argv[1], 16) - rom_file = sys.argv[2] - xhci_file = sys.argv[3] - imc_file = sys.argv[4] - gec_file = sys.argv[5] - print "%x %s %s %s %s" % (rom_addr, rom_file, xhci_file, imc_file, gec_file) - - main(rom_addr, rom_file, xhci_file, imc_file, gec_file)

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Patch set updated for coreboot: a7a0eb4 AMD S3: Add a document about S3 on AMD platform
by Zheng Bao 15 Aug '12

15 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1400 -gerrit commit a7a0eb4a4817a34da3c8b9132079fab45b557529 Author: zbao <fishbaozi(a)gmail.com> Date: Wed Aug 15 18:15:37 2012 +0800 AMD S3: Add a document about S3 on AMD platform See the document. Need review. Everything should be in Authentic English. Change-Id: Idc528b8c6b0d5afe08fc4f4387b7bff30698f677 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- documentation/AMD-S3.txt | 128 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 128 insertions(+) diff --git a/documentation/AMD-S3.txt b/documentation/AMD-S3.txt new file mode 100644 index 0000000..1ef87c0 --- /dev/null +++ b/documentation/AMD-S3.txt @@ -0,0 +1,128 @@ + _____ ____ _____ ______ ____ ____ ____ _______ + / ____/ __ \| __ \| ____| _ \ / __ \ / __ \__ __| + | | | | | | |__) | |__ | |_) | | | | | | | | | + | | | | | | _ /| __| | _ <| | | | | | | | | + | |___| |__| | | \ \| |____| |_) | |__| | |__| | | | + \_____\____/|_| \_\______|____/ \____/ \____/ |_| + + __ __ _____ _____ ____ + /\ | \/ | __ \ / ____| |___ \ + / \ | \ / | | | | | (___ __) | + / /\ \ | |\/| | | | | \___ \ |__ < + / ____ \| | | | |__| | ____) | ___) | + /_/ \_\_| |_|_____/ |_____/ |____/ + + + S3 in Coreboot (V 1.1) +---------------------------------------- + Zheng Bao + <zheng.bao(a)amd.com> + <fishbaozi(a)gmail.com> + +Introduction +============ +This document is about how the feature S3 is implemented on coreboot, +specificly on AMD platform. This topic deals with ACPI spec, hardware, +BIOS, OS. We try to help coreboot users to realize their own S3. + +S3 in a nutshell +================ +The S3 sleeping state is a low wake latency sleeping state where all +system context is lost except system memory. [1]. S3 is a ACPI +definition. +To enter S3, write 3 in SLP_TYPx and set the SLP_EN bit (See ACPI +registers). But if you do that, board can not resume at where it +sleeps, because you don't save the context. More often than not, we +make the board go into S3 by the tools which OSes provide. For +windows, click Start->sleep. For linux, some distribution provide a +tools called pm-suspend, which can make the system goto S3. If +pm-suspend is not available, we can run "echo mem > /sys/power/state", +but this way may not save all the needed context. +In S3 state, the power is off. So when the power button is pressed, +BIOS runs as it does in cold boot. If BIOS didn't detect whether +board boots or resumes, it would go the same way as boot. It is not +what we expect. BIOS detects the SLP_TYPx. If it is 3, it means BIOS +are waking up. +BIOS is responsible for restore the machine state as it is before +sleep. It needs restore the memory controller, not overwriting memory +which is not marked as reserved. For the peripheral which loses its +registers, BIOS needs to write the original value. +When everything is done, BIOS needs to find out the wakeup vector +provided by OSes and jump there. OSes also have work to do. We can go +to linux kernel or some other open source projects to find out how they +handle S3 resume. + +ACPI registers +============== +ACPI specification defines a group of registers. OSes handle all these +registers to read and write status to all the platform. +On AMD platform, these registers are provided by southbridge. For +example, Hudson uses PMIO 60:6F to define ACPI registers. +OSes don't have any specific driver to know where these registers +are. BIOS has the responsibility to allocated the IO resources and +write all these address to FADT, a ACPI defined table. + +Memory Layout +============= +Restoring memory is the most important job done by BIOS. When the +power is off, the memory is maintained by standby power. BIOS need to +make sure that when flow goes to OS, everything in memory should be +the same as it was. + +The chip vendor will provide a way, or code, to wake up the memory +from sleeping. In AGESA 2008 arch, it is called AmdInitResume. + +The BIOS itself needs some memory to run. Either, BIOS marks the erea +as reserved in e820, or BIOS saves the content into reserved space. + +Here is the address Map for S3 Resume. Assumingly the total memory is 1GB. +00000000 --- 00100000 BIOS Reserved area. +00100000 --- 00200000 Free +00200000 --- 01000000 Coreboot ramstage area. +01000000 --- 2e160000 Free +2e160000 --- 2e170000 ACPI table +2e170000 --- 2ef70000 OSRAM +2ef70000 --- 2efe0000 Stack in highmem +2efe0000 --- 2f000000 heap in highmem +2f000000 TOM + +AMD requirements in S3 +====================== +Chip vendor like AMD will provide bunch of routines to restore the +board.[2] + * AmdS3Save: It is called in cold boot, save required register into + non-volatile storage. Currently, we use SPI flash to store the data. + * AmdInitResume: Restore the memory controller. + * AmdS3LateRestore: Called after AmdInitResume, restore other + register that memory. + * (SouthBridge)InitS3EarlyRestore, (SouthBridge)InitS3LateRestore: + Provided by Southbridge vendor code. Early is called before PCI + enumeration, and Late is called after that. + +Lifecycle of booting, sleeping and waking Coreboot and Ubuntu +============================================================= +1. Cold boot. +For a system with S3 feature, the BIOS needs to save some data to +non-volitile storage at cold boot stage. What data need to be save are +provided by AmdS3Save. After the wrapper calls the AmdS3Save, it gets +the VolatileStorage and NvStorage, which are where the data are +located. It is the wrappers's responsibility to save the data.[3][4] +Currently, the wrappers allocate a CBFS modules in BIOS image. Todo +that, the wrapper needs to have the ability to write flash chips. It +is not as comprehensive as flashrom. But for the SST chip on Parmer, +MX chip on Thather, coreboot works well.[5] + +2. OS goes in S3. + +3. BIOS detect S3 wakeup + +4. OS resumes. + + +Reference +========= +[1] ACPI40a, http://www.acpi.info/spec40a.htm +[2] Coreboot Vendorcode, {top}/src/vendorcode/amd/agesa/{family}/Proc/Common/ +[3] Coreboot AGESA wrapper, {top}/src/mainboard/amd/parmer/agesawrapper.c +[4] Coreboot AGESA wrapper, {top}/src/cpu/amd/agesa/s3_resume.c +[5] Coreboot Southbridge, {top}/src/southbridge/amd/agesa/hudson/spi.c

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Patch merged into coreboot/master: 52fb5c4 buildgcc: Remove the warning options unsupported by cygwin
by gerrit＠coreboot.org 15 Aug '12

15 Aug '12

the following patch was just integrated into master: commit 52fb5c40890ac7bf4abba38564c483c748c915aa Author: zbao <fishbaozi(a)gmail.com> Date: Wed Aug 8 19:25:04 2012 +0800 buildgcc: Remove the warning options unsupported by cygwin My cygwin hostcc doesn't support -Wempty-body -Waddress -Wmissing-field-initializers Change-Id: I879e05f3bd396b36b327f204252e820552b6e12e Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Aug 8 12:35:06 2012, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Wed Aug 15 08:09:57 2012, giving +2 See http://review.coreboot.org/1426 for details. -gerrit

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Re: [coreboot] User interface on coreboot
by Stefan Reinauer 15 Aug '12

15 Aug '12

* ron minnich <rminnich(a)gmail.com> [120814 19:09]: > The plan, long ago, when it was still linuxbios, was that linux would > be the basis of interaction. Back then we were booting linux out of > flash faster than any known bios would put up a screen. We had tools > (rdcmos etc.) to manipulate cmos. We even had commands to control > overclocking from linux. There is one utility in the coreboot tree to do this: nvramtool

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Re: [coreboot] Regarding How-To for new board support
by Nils 14 Aug '12

14 Aug '12

Hi Peter, You wrote: >There is nearly zero correlation between the output of those tools >and coreboot support. Please don't waste time on sending the output, >and please try to update any and every resource that you find which >requests such output, to explain the situation more intelligently. This keeps popping up regularly. To prevent people wasting there and your time in the future maybe someone with wiki write rights (you?) could edit the "Will coreboot work on my machine?" alinea in the coreboot FAQ: http://www.coreboot.org/FAQ Greetings, Nils.

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Re: [coreboot] User interface on coreboot
by Peter Stuge 14 Aug '12

14 Aug '12

ron minnich wrote: > Then the bloat monster hit and the idea of linux as the firmware died. By now flash has bloated too, so Linux is again very viable. //Peter

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Re: [coreboot] Regarding How-To for new board support
by Peter Stuge 14 Aug '12

14 Aug '12

Andrey Gursky wrote: > Anton encourages the russian speaking part of linux users to write to > the list to get help of supporting a new mainboard. Did somebody write > in the past? Not many AFAIR. > Maybe there are not a lot of people ready to try coreboot, because of: > "Make changes to the board configuration, ACPI or IRQ routing etc etc > until you find the proper settings. This can take from an hour of time > to a few months based upon your coding skills and hardware issues." > And this is the citation for "a new board with the *same* cpu family, > chipset and superIO". Would you please be more precise, writing > How-To? That's not really possible. The effort required varies vastly depending on many factors, and how long it takes varies vastly with the developer's experience and skills. The closer your hardware is to another hardware which is already supported, the less work has to be done. If someone does not have suitable experience and skills to work efficiently on coreboot then of course it does not matter that only a little bit of work needs to be done. There have been many posts to the mailing list by initially inexperienced people who have tried to learn. It shows very quickly, sometimes already in the first email, if the person is able to make some progress or not, and once it is clear that there is progress (a good way is to push unfinished commits into gerrit!) then the more experienced community members usually always help out. > I own a Gigabyte ga-990xa-ud3 board [1], based on > Northbridge: AMD 990X > Southbridge: AMD SB950 > SuperIO: ITE IT8720F > BIOS: Macronix flash chip "MX25L3205" Look at the mainboards in the coreboot git tree which have similar configuration, and study how they have been implemented. Note that 890 and 990 are one and the same. 990 is strictly a marketing alias for mainboard vendors who wish to communicate upwards compatibility with newer CPUs which may not be supported by all 890 mainboards - but which *are* supported by the chipset. > By the way, what can be read from the original BIOS image? Nothing useful besides the VGA BIOS. The factory BIOS is proprietary code which can not be re-used in coreboot. > Are there any tools for this? Sure, google bios_extract > I've thought also of a following approach: would it be possible for > author added support for a AMD 8xx/9xx based board to publish the > output of tools, mentioned by Anton (flashrom, lspci -vv..., > superiotool), so that one could compare this input with the ready > code to see, what data is still missing and be able to ask for it? There is nearly zero correlation between the output of those tools and coreboot support. Please don't waste time on sending the output, and please try to update any and every resource that you find which requests such output, to explain the situation more intelligently. In particular, coreboot support can not be created using only the output of any tool. Porting coreboot to a new board takes hard work, studying (incomplete) documentation, testing, and a lot of trial and error. Even with thorough testing it is very easy to overlook some cases. It is absolutely not a suitable challenge for random Linux users, but maybe you would find it fun! Kind regards //Peter

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coreboot August 2012