coreboot August 2012

coreboot@coreboot.org

30 participants
321 discussions

Re: [coreboot] Support for laptop Samsung X360
by Marc Jones 11 Aug '12

11 Aug '12

On Sun, Aug 5, 2012 at 12:46 PM, <sambesselink(a)planet.nl> wrote: > Hi all, > > I got interested in coreboot and started reading coreboot.org. I gathered > some information and am wondering what you guys think of the chances of > getting to run coreboot on my laptop. > > Brand: Samsung > Type: NP-X360-AA03NL > CPU: Intel Core2 Duo SU9300 > Northbridge: Intel GS45ME > Southbridge: Intel ICH9M-E > SuperIO: SMSC FDC37N972 > EC: unknown (how do I find this?) > Flash chip: MX25L1605 > Flash size, type: 2048kB, SPI > > Running flashrom allowed me to find the flash info. It didn't throw any > problems (besides moaning that it's a laptop). > > I can also provide the dmidecode.log, ectool.log etc and the rom.bin I read > out if you would like me to. > > Thanks in advance for your help. > > Sam > Hi Sam, Welcome. I think that you will find that to be a very challenging project. I recommended becoming more familiar with coreboot. Try building and debugging on qemu. Prepare a way to recover your laptop when you flash something that doesn't boot. Study the output of your logs and learn about how your machine is put together. Regards, Marc > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot -- http://se-eng.com

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Patch merged into coreboot/master: 72ac49f gitconfig: upate commit-msg if newer one is available
by gerrit＠coreboot.org 10 Aug '12

10 Aug '12

the following patch was just integrated into master: commit 72ac49fe923783aeddb71c376270adba13469b87 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Aug 10 15:44:02 2012 +0800 gitconfig: upate commit-msg if newer one is available Change-Id: Iea010bf6f456a5ce5d8906821c95a7de4b577085 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Aug 10 08:29:06 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Aug 10 20:19:46 2012, giving +2 See http://review.coreboot.org/1429 for details. -gerrit

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New patch to review for coreboot: b264e86 Rename IORESOURCE_UMA_FB to IORESOURCE_UNCACHEABLE
by Kyösti Mälkki 10 Aug '12

10 Aug '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1431 -gerrit commit b264e861c9d5af4f0667769d651d7986456421d0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Aug 10 13:28:00 2012 +0300 Rename IORESOURCE_UMA_FB to IORESOURCE_UNCACHEABLE Previously UMA_FB had a special use as a workaround for AMD TOPMEM setup. With the workaround removed, this can now be treated as a generic flag to force an uncached MTRR setup. Change-Id: I6243a662f7ce012842e1d9f908699018d60a3280 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/x86/mtrr/mtrr.c | 3 +-- src/include/device/device.h | 2 +- src/include/device/resource.h | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index a061b54..9417a49 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -354,8 +354,7 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res) basek = resk(res->base); sizek = resk(res->size); - if (res->flags & IORESOURCE_UMA_FB) { - /* FIXME: could I use Write-Combining for Frame Buffer ? */ + if (res->flags & IORESOURCE_UNCACHEABLE) { state->reg = range_to_mtrr(state->reg, basek, sizek, 0, MTRR_TYPE_UNCACHEABLE, state->address_bits, state->above4gb); return; diff --git a/src/include/device/device.h b/src/include/device/device.h index 772b737..c711c7a 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -195,7 +195,7 @@ void fixed_mem_resource(device_t dev, unsigned long index, fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_IGNORE_MTRR) #define uma_resource(dev, idx, basek, sizek) \ - fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_UMA_FB) + fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_UNCACHEABLE) #define mmio_resource(dev, idx, basek, sizek) \ fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_IGNORE_MTRR) diff --git a/src/include/device/resource.h b/src/include/device/resource.h index ddedc2f..057b898 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -21,7 +21,7 @@ * to the bus below. */ #define IORESOURCE_BRIDGE 0x00080000 /* The IO resource has a bus below it. */ -#define IORESOURCE_UMA_FB 0x00100000 /* UMA framebuffer */ +#define IORESOURCE_UNCACHEABLE 0x00100000 /* The resource creates an explicit un-cached MTRR hole. */ #define IORESOURCE_IGNORE_MTRR 0x00200000 /* The resource does not affect MTRR setup. */ #define IORESOURCE_RESERVE 0x10000000 /* The resource needs to be reserved in the coreboot table */

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New patch to review for coreboot: 2781b84 util: Add utility to read EPHY config on VX900
by Alexandru Gagniuc 10 Aug '12

10 Aug '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1430 -gerrit commit 2781b84aeb42563f898348ba7ed7278422ea2ccc Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Aug 10 03:55:42 2012 -0500 util: Add utility to read EPHY config on VX900 Seems there is bo tool in our arsenal that does anything related. See util/viatools/vx900_ephy/README for all relevant details. Change-Id: Icbd39eaf7c7da5568732d77dbf2aed135f835754 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- util/viatools/vx900_ephy/Makefile | 35 +++++++++++ util/viatools/vx900_ephy/README | 9 +++ util/viatools/vx900_ephy/vx900_ephy.c | 106 +++++++++++++++++++++++++++++++++ 3 files changed, 150 insertions(+), 0 deletions(-) diff --git a/util/viatools/vx900_ephy/Makefile b/util/viatools/vx900_ephy/Makefile new file mode 100644 index 0000000..1bdb4d5 --- /dev/null +++ b/util/viatools/vx900_ephy/Makefile @@ -0,0 +1,35 @@ + ## + ## This file is part of the vx900_ephy utlity. + ## + ## + ## Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + ## + ## This program is free software: you can redistribute it and/or modify + ## it under the terms of the GNU General Public License as published by + ## the Free Software Foundation, either version 2 of the License, or + ## (at your option) any later version. + ## + ## This program is distributed in the hope that it will be useful, + ## but WITHOUT ANY WARRANTY; without even the implied warranty of + ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + ## GNU General Public License for more details. + ## + ## You should have received a copy of the GNU General Public License + ## along with this program. If not, see <http://www.gnu.org/licenses/>. + ## + +CC=gcc + +SRCS = vx900_ephy.c +OBJS = $(sort ${SRCS:.c=.o}) + +all: vx900_ephy + +vx900_ephy: $(OBJS) + $(CC) $< -o $@ -lpci + +%.o: %.c + $(CC) -c $< -o $@ + +clean: + rm -f $(OBJS) \ No newline at end of file diff --git a/util/viatools/vx900_ephy/README b/util/viatools/vx900_ephy/README new file mode 100644 index 0000000..70d7d9f --- /dev/null +++ b/util/viatools/vx900_ephy/README @@ -0,0 +1,9 @@ + +On the VX900 chipset, the SATA physical layer is controllable by index/value +pairs in the PCI config space. Getting the EPHY config (as VIA calls it) is thus +not achievable by a simple lspci -xx. + +The EPHY config is needed to get the SATA links running properly. The default +values disable the driving resistors. While the SATA link may appear to work +initially, the chipset indicates a PHY error occurs. This tool reads the EPHY +config from a VX900 chipset. diff --git a/util/viatools/vx900_ephy/vx900_ephy.c b/util/viatools/vx900_ephy/vx900_ephy.c new file mode 100644 index 0000000..913f2fd --- /dev/null +++ b/util/viatools/vx900_ephy/vx900_ephy.c @@ -0,0 +1,106 @@ +/* + * This file is part of the vx900_ephy utlity. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <pci/pci.h> +#include <stddef.h> +#include <stdio.h> + +#define VX900_SATA_DOM 0 +#define VX900_SATA_BUS 0 +#define VX900_SATA_DEV 0x0f +#define VX900_SATA_FUNC 0 + +#define VX900_SATA_DEV_ID 0x9001 +#define VX900_SATA_VEND_ID 0x1106 + +typedef struct pci_dev *device_t; + +typedef u8 sata_phy_config[64]; + +static u32 sata_phy_read32(device_t dev, u8 index) +{ + /* The SATA PHY control registers are accessed by a funny index/value + * scheme. Each byte (0,1,2,3) has its own 4-bit index */ + index = (index >> 2) & 0xf; + u16 i16 = index | (index<<4) | (index<<8)| (index<<12); + /* The index */ + pci_write_word(dev, 0x68, i16); + /* The value */ + return pci_read_long(dev, 0x64); + +} + +static void vx900_sata_read_phy_config(device_t dev, sata_phy_config cfg) +{ + size_t i; + u32* data = (u32*)cfg; + for(i = 0; i < (sizeof(sata_phy_config) ) >> 2; i++) { + data[i] = sata_phy_read32(dev, i<<2); + } +} + +int main() +{ + sata_phy_config ephy; + struct pci_access *pci_lord; + device_t dev; + + printf(" vx900_ephy tool:\n"); + printf(" Copyright (C) 2012 Alexandru Gagniuc\n"); + printf("======================================\n"); + + /* libpci mambo jumbo we need to do, but don't care about */ + pci_lord = pci_alloc(); + pci_init(pci_lord); + pci_scan_bus(pci_lord); + + /* We write to the PCI config, so stop here if it's the wrong device */ + dev = pci_get_dev(pci_lord, VX900_SATA_DOM, VX900_SATA_BUS, + VX900_SATA_DEV, VX900_SATA_FUNC); + + pci_fill_info(dev, PCI_FILL_IDENT | PCI_FILL_BASES | PCI_FILL_CLASS); + + if( (VX900_SATA_VEND_ID != dev->vendor_id) || + (VX900_SATA_DEV_ID != dev->device_id) ) + { + printf("VX900 SATA controller not found\n"); + return -1; + + } + /* Get all the info in one pass */ + vx900_sata_read_phy_config(dev, ephy); + + /* Put it on the terminal for the user to read and be done with it */ + printf("SATA PHY config:\n"); + int i; + for (i = 0; i < sizeof(sata_phy_config); i++) { + if ((i & 0x0f) == 0) { + printf("%.2x :", i); + } + if( (i & 0x0f) == 0x08 ) + printf("| "); + printf("%.2x ", ephy[i]); + if ((i & 0x0f) == 0x0f) { + printf("\n"); + } + } + + printf("Compare that with the coreboot debug output, and see if the" + " EPHY values need adjustment for your mainboard.\n"); +} \ No newline at end of file

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User interface on coreboot
by Lap Ngo Doan 10 Aug '12

10 Aug '12

Hi all, As you may know, when we enter to BIOS, we can use the keyboard to change some settings such as : enable/disable something, change boot devices priority ....It is kind of user interface on BIOS. In the coreboot website, they said "*coreboot* is a Free Software project aimed at *replacing the proprietary**BIOS* <http://wikipedia.org/wiki/BIOS> (firmware) found in most computers..." If we want to add some interactions with hardware like BIOS firmware provided us (use keyboard to enable/disable some options....), how could we do it with coreboot? Thank you!

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Patch set updated for coreboot: 72ac49f gitconfig: upate commit-msg if newer one is available
by Zheng Bao 10 Aug '12

10 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1429 -gerrit commit 72ac49fe923783aeddb71c376270adba13469b87 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Aug 10 15:44:02 2012 +0800 gitconfig: upate commit-msg if newer one is available Change-Id: Iea010bf6f456a5ce5d8906821c95a7de4b577085 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- Makefile.inc | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 083d423..4c2bb4c 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -291,7 +291,13 @@ lint lint-stable: rm -f $$LINTLOG gitconfig: - for hook in commit-msg pre-commit; do if ! [ -x .git/hooks/$$hook ]; then cp util/gitconfig/$$hook .git/hooks/$$hook; chmod +x .git/hooks/$$hook; fi; done + for hook in commit-msg pre-commit ; do \ + if [ util/gitconfig/$$hook -nt .git/hooks/$$hook -o \ + ! -x .git/hooks/$$hook ]; then \ + cp util/gitconfig/$$hook .git/hooks/$$hook; \ + chmod +x .git/hooks/$$hook; \ + fi; \ + done (git config --global user.name >/dev/null && git config --global user.email >/dev/null) || (printf 'Please configure your name and email in git:\n\n git config --global user.name "Your Name Comes Here"\n git config --global user.email your.email(a)example.com\n'; exit 1) crossgcc: clean-for-update

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Patch merged into coreboot/master: 0c6f759 Replicate TOP_MEM and TOP_MEM2 from BSP to AP CPU
by gerrit＠coreboot.org 09 Aug '12

09 Aug '12

the following patch was just integrated into master: commit 0c6f7597304deef5f14a59d00d3c5d6bd97db9a9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Aug 5 12:12:05 2012 +0300 Replicate TOP_MEM and TOP_MEM2 from BSP to AP CPU The search loop for UMA resource was only used to check for the highest RAM address below 4GB. The cached values from BSP CPU can now be used for the replication. Change-Id: I5244ffa6f8a93f5ff5aaf8a71bd006b0f9cd518a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Aug 9 20:00:30 2012, giving +1 Reviewed-By: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> at Thu Aug 9 20:01:12 2012, giving +2 See http://review.coreboot.org/1388 for details. -gerrit

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Patch set updated for coreboot: 0c6f759 Replicate TOP_MEM and TOP_MEM2 from BSP to AP CPU
by Alexandru Gagniuc 09 Aug '12

09 Aug '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1388 -gerrit commit 0c6f7597304deef5f14a59d00d3c5d6bd97db9a9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Aug 5 12:12:05 2012 +0300 Replicate TOP_MEM and TOP_MEM2 from BSP to AP CPU The search loop for UMA resource was only used to check for the highest RAM address below 4GB. The cached values from BSP CPU can now be used for the replication. Change-Id: I5244ffa6f8a93f5ff5aaf8a71bd006b0f9cd518a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/mtrr/amd_mtrr.c | 49 ++++++++++++++++++------------------------ 1 files changed, 21 insertions(+), 28 deletions(-) diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 9349ad4..bff6702 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -102,20 +102,6 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc } -static void uma_fb_resource(void *gp, struct device *dev, struct resource *res) -{ - struct mem_state *state = gp; - unsigned long topk; - - topk = resk(res->base + res->size); - if (state->tom2k < topk) { - state->tom2k = topk; - } - if ((topk < 4*1024*1024) && (state->tomk < topk)) { - state->tomk = topk; - } -} - /* These will likely move to some device node or cbmem. */ static uint64_t amd_topmem = 0; static uint64_t amd_topmem2 = 0; @@ -154,6 +140,25 @@ void setup_bsp_ramtop(void) amd_topmem2 = (uint64_t) msr2.hi<<32 | msr2.lo; } +static void setup_ap_ramtop(void) +{ + msr_t msr; + uint64_t v; + + v = bsp_topmem(); + if (!v) + return; + + msr.hi = v >> 32; + msr.lo = (uint32_t) v; + wrmsr(TOP_MEM, msr); + + v = bsp_topmem2(); + msr.hi = v >> 32; + msr.lo = (uint32_t) v; + wrmsr(TOP_MEM2, msr); +} + void amd_setup_mtrrs(void) { unsigned long address_bits; @@ -185,9 +190,6 @@ void amd_setup_mtrrs(void) state.tomk = state.tom2k = 0; search_global_resources( - IORESOURCE_MEM | IORESOURCE_UMA_FB, IORESOURCE_MEM | IORESOURCE_UMA_FB, - uma_fb_resource, &state); - search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, set_fixed_mtrr_resource, &state); @@ -195,20 +197,11 @@ void amd_setup_mtrrs(void) disable_cache(); - /* Round state.tomk up to the next greater size that will fit in TOP_MEM */ - state.tomk = (state.tomk + TOP_MEM_MASK_KB) & ~TOP_MEM_MASK_KB; - msr.hi = state.tomk >> 22; - msr.lo = state.tomk << 10; - wrmsr(TOP_MEM, msr); + setup_ap_ramtop(); /* if DRAM above 4GB: set SYSCFG_MSR_TOM2En and SYSCFG_MSR_TOM2WB */ sys_cfg.lo &= ~(SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB); - if(state.tom2k > (4*1024*1024)) { - /* Round state.tomk up to the next greater size that will fit in TOP_MEM2 */ - state.tom2k = (state.tom2k + TOP_MEM_MASK_KB) & ~TOP_MEM_MASK_KB; - msr.hi = state.tom2k >> 22; - msr.lo = state.tom2k << 10; - wrmsr(TOP_MEM2, msr); + if (bsp_topmem2() > (uint64_t)1<<32) { sys_cfg.lo |= SYSCFG_MSR_TOM2En; if(has_tom2wb) sys_cfg.lo |= SYSCFG_MSR_TOM2WB;

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Patch merged into coreboot/master: 4d5ba2c AMD northbridge: copy TOP_MEM and TOP_MEM2 for distribution
by gerrit＠coreboot.org 09 Aug '12

09 Aug '12

the following patch was just integrated into master: commit 4d5ba2cf1ae8384b2c504b80093286843312d899 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Aug 5 12:11:40 2012 +0300 AMD northbridge: copy TOP_MEM and TOP_MEM2 for distribution Take a copy of BSP CPU's TOP_MEM and TOP_MEM2 MSRs to be distributed to AP CPUs and factor out the debugging info from setup_uma_memory(). Change-Id: I1acb4eaa3fe118aee223df1ebff997289f5d3a56 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Sun Aug 5 13:19:30 2012, giving +1 Reviewed-By: Zheng Bao <zheng.bao(a)amd.com> at Wed Aug 8 12:11:42 2012, giving +1 Reviewed-By: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> at Thu Aug 9 19:15:32 2012, giving +2 See http://review.coreboot.org/1387 for details. -gerrit

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Patch merged into coreboot/master: 9307327 Sandybridge: Fix integer overrun in romstage udelay()
by gerrit＠coreboot.org 09 Aug '12

09 Aug '12

the following patch was just integrated into master: commit 93073277c12512d1e39b491d969b776d27ed85b1 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jul 25 16:15:25 2012 -0700 Sandybridge: Fix integer overrun in romstage udelay() This was broken, fixing according to related patch for i945 Change-Id: I925cd205ee5beb918181740a7b981a4209688ac6 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Thu Aug 9 03:26:35 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Aug 9 17:01:55 2012, giving +2 See http://review.coreboot.org/1412 for details. -gerrit

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coreboot August 2012