the following patch was just integrated into master:
commit 4412fec06da358325839fcc79b0d834d43d3778b
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Tue Aug 7 21:17:33 2012 -0500
gitignore: Ignore KDE backup files
KDE editors love to create tons of backup files every time a file is
edited. This makes it very hard to get useful information from git status
and very easy to commit the wrong stuff. Add those to the gitignore list.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Change-Id: I2fbb907f21d85d6994caa8bbe32c4e9814b5f4b4
Build-Tested: build bot (Jenkins) at Wed Aug 8 05:07:27 2012, giving +1
Reviewed-By: Peter Stuge <peter(a)stuge.se> at Wed Aug 8 04:59:39 2012, giving +2
See http://review.coreboot.org/1423 for details.
-gerrit
Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1400
-gerrit
commit bbec26a97bf876309b04d60a8622320b8798ee9d
Author: zbao <fishbaozi(a)gmail.com>
Date: Wed Aug 8 12:33:16 2012 +0800
AMD S3: Add a document about S3 on AMD platform
See the document. Need review. Everything should be in Authentic
English.
Change-Id: Idc528b8c6b0d5afe08fc4f4387b7bff30698f677
Signed-off-by: Zheng Bao <zheng.bao(a)amd.com>
Signed-off-by: zbao <fishbaozi(a)gmail.com>
---
documentation/AMD-S3.txt | 105 ++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 105 insertions(+), 0 deletions(-)
diff --git a/documentation/AMD-S3.txt b/documentation/AMD-S3.txt
new file mode 100644
index 0000000..3a84f3a
--- /dev/null
+++ b/documentation/AMD-S3.txt
@@ -0,0 +1,105 @@
+ _____ ____ _____ ______ ____ ____ ____ _______
+ / ____/ __ \| __ \| ____| _ \ / __ \ / __ \__ __|
+ | | | | | | |__) | |__ | |_) | | | | | | | | |
+ | | | | | | _ /| __| | _ <| | | | | | | | |
+ | |___| |__| | | \ \| |____| |_) | |__| | |__| | | |
+ \_____\____/|_| \_\______|____/ \____/ \____/ |_|
+
+ __ __ _____ _____ ____
+ /\ | \/ | __ \ / ____| |___ \
+ / \ | \ / | | | | | (___ __) |
+ / /\ \ | |\/| | | | | \___ \ |__ <
+ / ____ \| | | | |__| | ____) | ___) |
+ /_/ \_\_| |_|_____/ |_____/ |____/
+
+
+ S3 in Coreboot (V 1.1)
+----------------------------------------
+ Zheng Bao
+ <zheng.bao(a)amd.com>
+ <fishbaozi(a)gmail.com>
+
+Introduction
+============
+This document is about how the feature S3 is implemented on coreboot,
+specificly on AMD platform. This topic deals with ACPI spec, hardware,
+BIOS, OS. We try to help coreboot users to realize their own S3.
+
+S3 in a nutshell
+================
+The S3 sleeping state is a low wake latency sleeping state where all
+system context is lost except system memory. [1]. S3 is a ACPI
+definition.
+To enter S3, write 3 in SLP_TYPx and set the SLP_EN bit (See ACPI
+registers). But if you do that, board can not resume at where it
+sleeps, because you don't save the context. More often than not, we
+make the board go into S3 by the tools which OSes provide. For
+windows, click Start->sleep. For linux, some distribution provide a
+tools called pm-suspend, which can make the system goto S3. If
+pm-suspend is not available, we can run "echo mem > /sys/power/state",
+but this way may not save all the needed context.
+In S3 state, the power is off. So when the power button is pressed,
+BIOS runs as it does in cold boot. If BIOS didn't detect whether
+board boots or resumes, it would go the same way as boot. It is not
+what we expect. BIOS detects the SLP_TYPx. If it is 3, it means BIOS
+are waking up.
+BIOS is responsible for restore the machine state as it is before
+sleep. It needs restore the memory controller, not overwriting memory
+which is not marked as reserved. For the peripheral which loses its
+registers, BIOS needs to write the original value.
+When everything is done, BIOS needs to find out the wakeup vector
+provided by OSes and jump there. OSes also have work to do. We can go
+to linux kernel or some other open source projects to find out how they
+handle S3 resume.
+
+ACPI registers
+==============
+ACPI specification defines a group of registers. OSes handle all these
+registers to read and write status to all the platform.
+On AMD platform, these registers are provided by southbridge. For
+example, Hudson uses PMIO 60:6F to define ACPI registers.
+OSes don't have any specific driver to know where these registers
+are. BIOS has the responsibility to allocated the IO resources and
+write all these address to FADT, a ACPI defined table.
+
+Memory Layout
+=============
+Restoring memory is the most important job done by BIOS. When the
+power is off, the memory is maintained by standby power. BIOS need to
+make sure that when flow goes to OS, everything in memory should be
+the same as it was.
+
+The chip vendor will provide a way, or code, to wake up the memory
+from sleeping. In AGESA 2008 arch, it is called AmdInitResume.
+
+The BIOS itself needs some memory to run. Either, BIOS marks the erea
+as reserved in e820, or BIOS saves the content into reserved space.
+
+Here is the address Map for S3 Resume. Assumingly the total memory is 1GB.
+00000000 --- 00100000 BIOS Reserved area.
+00100000 --- 00200000 Free
+00200000 --- 01000000 Coreboot ramstage area.
+01000000 --- 2e160000 Free
+2e160000 --- 2e170000 ACPI table
+2e170000 --- 2ef70000 OSRAM
+2ef70000 --- 2efe0000 Stack in highmem
+2efe0000 --- 2f000000 heap in highmem
+2f000000 TOM
+
+AMD requirements in S3
+======================
+Chip vendor like AMD will provide bunch of routines to restore the
+board.[2]
+ * AmdS3Save: It is called in cold boot, save required register into
+ non-volatile storage. Currently, we use SPI flash to store the data.
+ * AmdInitResume: Restore the memory controller.
+ * AmdS3LateRestore: Called after AmdInitResume, restore other
+ register that memory.
+ * (SouthBridge)InitS3EarlyRestore, (SouthBridge)InitS3LateRestore:
+ Provided by Southbridge vendor code. Early is called before PCI
+ enumeration, and Late is called after that.
+
+Reference
+=========
+[1] ACPI40a, http://www.acpi.info/spec40a.htm
+[2] Coreboot Vendorcode, {top}/src/vendorcode/amd/agesa/{family}/Proc/Common/
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1423
-gerrit
commit 4412fec06da358325839fcc79b0d834d43d3778b
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Tue Aug 7 21:17:33 2012 -0500
gitignore: Ignore KDE backup files
KDE editors love to create tons of backup files every time a file is
edited. This makes it very hard to get useful information from git status
and very easy to commit the wrong stuff. Add those to the gitignore list.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Change-Id: I2fbb907f21d85d6994caa8bbe32c4e9814b5f4b4
---
.gitignore | 9 +++++++++
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/.gitignore b/.gitignore
index 8e259c7..ea10be7 100644
--- a/.gitignore
+++ b/.gitignore
@@ -35,6 +35,15 @@ util/crossgcc/w32api-*/
*.\#
*.swp
*.bin
+
+#
+# KDE editors create lots of backup files whenever
+# a file is edited, so just ignore them
+*~
+*.kate-swp
+# Ignore Kdevelop project file
+.kdev4
+
util/ectool/ectool
util/inteltool/.dependencies
util/inteltool/inteltool
the following patch was just integrated into master:
commit 46d9b54674c65d28d8b0c55828d580d823f76c64
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Thu Aug 2 09:48:38 2012 +0300
Drop HAVE_MAINBOARD_RESOURCES
These existed to provide a hook to add reserved memory regions
in the coreboot memory table. Reserved memory are now
added as resources.
Change-Id: I9f83df33845cfa6973b018a51cf9444dbf0f8667
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Build-Tested: build bot (Jenkins) at Tue Aug 7 07:26:10 2012, giving +1
Reviewed-By: Peter Stuge <peter(a)stuge.se> at Wed Aug 8 03:44:51 2012, giving +2
See http://review.coreboot.org/1414 for details.
-gerrit
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1257
-gerrit
commit dcf1f3f3fc687c98a1c188a9a849cd558e39a524
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Tue Aug 7 19:38:32 2012 -0500
VIA Nano: Add support for VIA Nano CPUs
Add code to do the following for the VIA Nano CPUs
- Update microcode
- Set maximum frequency
- Initialize power states
- Set up cache
Attempting to change the voltage or frequency of the CPU without
applying the microcode update will hang the CPU, so we only do
transitions if we can verify the microcode has been updated.
The microcode is updated directly from CBFS. No microcode is
included in ramstage. The microcode is not included in this
commit.
To get the microcode, run bios_extract on the manufacturer supplied
BIOS, and look for the file marked "P6 Microcode". Include this
file in CBFS.
You can have the build system include this file automatically by
selecting Expert Mode, then look under
'Chipset' -> 'Include CPU microcode in CBFS' ->
Include external microcode file (check)
'Path and filename of CPU microcode' should contain the location of
the microcode file previously extracted.
Change-Id: I586aaca5715e047b42ef901d66772ace0e6b655e
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/cpu/via/Kconfig | 1 +
src/cpu/via/Makefile.inc | 6 +-
src/cpu/via/nano/Kconfig | 41 ++++++++
src/cpu/via/nano/Makefile.inc | 33 ++++++
src/cpu/via/nano/nano_init.c | 204 +++++++++++++++++++++++++++++++++++++++
src/cpu/via/nano/update_ucode.c | 150 ++++++++++++++++++++++++++++
src/cpu/via/nano/update_ucode.h | 73 ++++++++++++++
7 files changed, 505 insertions(+), 3 deletions(-)
diff --git a/src/cpu/via/Kconfig b/src/cpu/via/Kconfig
index 570d408..5c38c91 100644
--- a/src/cpu/via/Kconfig
+++ b/src/cpu/via/Kconfig
@@ -1,2 +1,3 @@
source src/cpu/via/c3/Kconfig
source src/cpu/via/c7/Kconfig
+source src/cpu/via/nano/Kconfig
diff --git a/src/cpu/via/Makefile.inc b/src/cpu/via/Makefile.inc
index 2616111..f1e198d 100644
--- a/src/cpu/via/Makefile.inc
+++ b/src/cpu/via/Makefile.inc
@@ -1,3 +1,3 @@
-subdirs-$(CONFIG_CPU_VIA_C7) += c7
-subdirs-$(CONFIG_CPU_VIA_C3) += c3
-
+subdirs-$(CONFIG_CPU_VIA_C7) += c7
+subdirs-$(CONFIG_CPU_VIA_C3) += c3
+subdirs-$(CONFIG_CPU_VIA_NANO) += nano
diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig
new file mode 100644
index 0000000..3b1c213
--- /dev/null
+++ b/src/cpu/via/nano/Kconfig
@@ -0,0 +1,41 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program. If not, see <http://www.gnu.org/licenses/>.
+##
+
+config CPU_VIA_NANO
+ bool
+
+if CPU_VIA_NANO
+
+config CPU_SPECIFIC_OPTIONS
+ def_bool y
+ select UDELAY_TSC
+ select MMX
+ select SSE2
+ select CACHE_AS_RAM
+ select CPU_MICROCODE_IN_CBFS
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xffe00000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x8000
+
+endif # CPU_VIA_NANO
diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc
new file mode 100644
index 0000000..6b0c1e9
--- /dev/null
+++ b/src/cpu/via/nano/Makefile.inc
@@ -0,0 +1,33 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program. If not, see <http://www.gnu.org/licenses/>.
+##
+
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+
+driver-y += nano_init.c
+ramstage-y += update_ucode.c
+
+# We need to hear from VIA to get permission to include this file in the
+# official coreboot repository. Until then, we leave this commented out
+# cpu-microcode-y += nano_ucode_blob.c
+
+cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc
diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c
new file mode 100644
index 0000000..417119f
--- /dev/null
+++ b/src/cpu/via/nano/nano_init.c
@@ -0,0 +1,204 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "update_ucode.h"
+#include <console/console.h>
+#include <device/device.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/cache.h>
+#include <delay.h>
+
+#define MODEL_NANO 0x2
+#define MODEL_NANO_3000_B0 0x8
+#define MODEL_NANO_3000_B2 0xa
+
+#define MSR_IA32_PERF_STATUS 0x00000198
+#define MSR_IA32_PERF_CTL 0x00000199
+#define MSR_IA32_MISC_ENABLE 0x000001a0
+#define NANO_MYSTERIOUS_MSR 0x120e
+
+static void nano_finish_fid_vid_transition(void)
+{
+
+ msr_t msr;
+ /* Wait until the power transition ends */
+ int cnt = 0;
+ do {
+ udelay(16);
+ msr = rdmsr(MSR_IA32_PERF_STATUS);
+ cnt++;
+ if (cnt > 128) {
+ printk(BIOS_WARNING,
+ "Error while updating multiplier and voltage\n");
+ break;
+ }
+ } while (msr.lo & ((1 << 16) | (1 << 17)));
+
+ /* Print the new FID and Voltage */
+ u8 cur_vid = (msr.lo >> 0) & 0xff;
+ u8 cur_fid = (msr.lo >> 8) & 0xff;
+ printk(BIOS_INFO, "New CPU multiplier: %dx\n", cur_fid);
+ printk(BIOS_INFO, "New Voltage ID : %dx\n", cur_vid);
+}
+
+static void nano_set_max_fid_vid(void)
+{
+ msr_t msr;
+ /* Get voltage and frequency info */
+ msr = rdmsr(MSR_IA32_PERF_STATUS);
+ u8 min_fid = (msr.hi >> 24);
+ u8 max_fid = (msr.hi >> 8) & 0xff;
+ u8 min_vid = (msr.hi >> 16) & 0xff;
+ u8 max_vid = (msr.hi >> 0) & 0xff;
+ u8 cur_vid = (msr.lo >> 0) & 0xff;
+ u8 cur_fid = (msr.lo >> 8) & 0xff;
+
+ printk(BIOS_INFO, "CPU multiplier: %dx (min %dx; max %dx)\n",
+ cur_fid, min_fid, max_fid);
+ printk(BIOS_INFO, "Voltage ID : %dx (min %dx; max %dx)\n",
+ cur_vid, min_vid, max_vid);
+
+ if( (cur_fid != max_fid) || (cur_vid != max_vid) ) {
+ /* Set highest frequency and VID */
+ msr.lo = msr.hi;
+ msr.hi = 0;
+ wrmsr(MSR_IA32_PERF_CTL, msr);
+ /* Wait for the transition to complete, otherwise, the CPU
+ * might reset itself repeatedly */
+ nano_finish_fid_vid_transition();
+ }
+ /* As a side note, if we didn't update the microcode by this point, the
+ * second PLL will not lock correctly. The clock will still be provided
+ * by the first PLL, and execution will continue normally, ___until___
+ * the CPU switches PLL. Once that happens we will no longer have a
+ * working clock source, and the CPU will hang
+ * Moral of the story: update the microcode, or don't change FID
+ * This check is handled before calling nano_power() */
+}
+
+static void nano_power(void)
+{
+ msr_t msr;
+ /* Enable Powersaver */
+ msr = rdmsr(MSR_IA32_MISC_ENABLE);
+ msr.lo |= (1 << 16);
+ wrmsr(MSR_IA32_MISC_ENABLE, msr);
+
+ /* Enable 6 bit or 7-bit VRM support
+ * This MSR is not documented by VIA docs, other than setting these
+ * bits */
+ msr = rdmsr(NANO_MYSTERIOUS_MSR);
+ msr.lo |= ( (1<<7) | (1<<4) );
+ /* FIXME: Do we have a 6-bit or 7-bit VRM?
+ * set bit [5] for 7-bit, or don't set it for 6 bit VRM
+ * This will probably require a Kconfig option
+ * My board has a 7-bit VRM, so I can't test the 6-bit VRM stuff */
+ msr.lo |= (1<<5);
+ wrmsr(NANO_MYSTERIOUS_MSR, msr);
+
+ /* Set the maximum frequency and voltage */
+ nano_set_max_fid_vid();
+
+ /* Enable TM3 */
+ msr = rdmsr(MSR_IA32_MISC_ENABLE);
+ msr.lo |= ( (1<<3) | (1<<13) );
+ wrmsr(MSR_IA32_MISC_ENABLE, msr);
+
+ u8 stepping = ( cpuid_eax(0x1) ) &0xf;
+ if(stepping >= MODEL_NANO_3000_B0) {
+ /* Hello Nano 3000. The Terminator needs a CPU upgrade */
+ /* Enable C1e, C2e, C3e, and C4e states */
+ msr = rdmsr(MSR_IA32_MISC_ENABLE);
+ msr.lo |= ( (1<<25) | (1<<26) | (1<<31)); /* C1e, C2e, C3e */
+ msr.hi |= (1<<0); /* C4e */
+ wrmsr(MSR_IA32_MISC_ENABLE, msr);
+ }
+
+ /* Lock on Powersaver */
+ msr = rdmsr(MSR_IA32_MISC_ENABLE);
+ msr.lo |= (1<<20);
+ wrmsr(MSR_IA32_MISC_ENABLE, msr);
+}
+
+static void nano_init(device_t dev)
+{
+ struct cpuinfo_x86 c;
+
+ get_fms(&c, dev->device);
+
+ /* We didn't test this on the Nano 1000/2000 series, so warn the user */
+ if(c.x86_mask < MODEL_NANO_3000_B0) {
+ printk(BIOS_EMERG, "WARNING: This CPU has not been tested. "
+ "Please report any issues encountered. \n");
+ }
+ switch (c.x86_mask) {
+ case MODEL_NANO:
+ printk(BIOS_INFO, "VIA Nano");
+ break;
+ case MODEL_NANO_3000_B0:
+ printk(BIOS_INFO, "VIA Nano 3000 rev B0");
+ break;
+ case MODEL_NANO_3000_B2:
+ printk(BIOS_INFO, "VIA Nano 3000 rev B2");
+ break;
+ default:
+ printk(BIOS_EMERG, "Stepping not recognized: %x\n", c.x86_mask);
+ }
+ printk(BIOS_INFO, "\n");
+
+ /* We only read microcode from CBFS. If we don't have any microcode in
+ * CBFS, we'll just get back with 0 updates. User choice FTW. */
+ unsigned int n_updates = nano_update_ucode();
+
+ if(n_updates != 0){
+ nano_power();
+ } else {
+ /* Changing the frequency or voltage without first updating the
+ * microcode will hang the CPU, so just don't do it */
+ printk(BIOS_EMERG, "WARNING: CPU Microcode not updated.\n"
+ " Will not change frequency, as this may hang the CPU.\n");
+ }
+
+ /* Turn on cache */
+ x86_enable_cache();
+ /* Set up Memory Type Range Registers */
+ x86_setup_mtrrs();
+ x86_mtrr_check();
+ /* Enable the local cpu apics */
+ setup_lapic();
+}
+
+static struct device_operations cpu_dev_ops = {
+ .init = nano_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+ {X86_VENDOR_CENTAUR, 0x06f2}, // VIA NANO 1000/2000 Series
+ {X86_VENDOR_CENTAUR, 0x06f8}, // VIA NANO 3000 rev B0
+ {X86_VENDOR_CENTAUR, 0x06fa}, // VIA NANO 3000 rev B2
+ {0, 0},
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+ .ops = &cpu_dev_ops,
+ .id_table = cpu_table,
+};
diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c
new file mode 100644
index 0000000..8f7ee22
--- /dev/null
+++ b/src/cpu/via/nano/update_ucode.c
@@ -0,0 +1,150 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "update_ucode.h"
+#include <cpu/x86/msr.h>
+#include <console/console.h>
+#include <stddef.h>
+#include <cpu/cpu.h>
+#include <arch/cpu.h>
+#include <cbfs.h>
+
+static ucode_update_status nano_apply_ucode(const nano_ucode_header *ucode)
+{
+ printk(BIOS_SPEW, "Attempting to apply microcode update\n");
+
+ msr_t msr;
+ /* Address of ucode block goes in msr.lo for 32-bit mode
+ * Now remember, we need to pass the address of the actual microcode,
+ * not the header. The header is just there to help us. */
+ msr.lo = (unsigned int)(&(ucode->ucode_start));
+ msr.hi = 0;
+ wrmsr(MSR_IA32_BIOS_UPDT_TRIG, msr);
+
+ /* Let's see if we updated succesfully */
+ msr = rdmsr(MSR_UCODE_UPDATE_STATUS);
+
+ return msr.lo & 0x07;
+}
+
+static void nano_print_ucode_info(const nano_ucode_header *ucode)
+{
+ printk(BIOS_SPEW, "Microcode update information:\n");
+ printk(BIOS_SPEW, "Name: %8s\n", ucode->name );
+ printk(BIOS_SPEW, "Date: %u/%u/%u\n", ucode->month,
+ ucode->day, ucode->year );
+}
+
+static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode)
+{
+ /* We must have a valid signature */
+ if(ucode->signature != NANO_UCODE_SIGNATURE)
+ return NANO_UCODE_SIGNATURE_ERROR;
+ /* The size of the head must be exactly 12 double words */
+ if( (ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE)
+ return NANO_UCODE_WRONG_SIZE;
+
+ /* How about a checksum ? Checksum must be 0
+ * Two's complement done over the entire file, including the header */
+ int i;
+ u32 check = 0;
+ u32 *raw = (void*) ucode;
+ for(i = 0 ; i < ((ucode->total_size) >> 2); i++) {
+ check += raw[i];
+ }
+ if(check != 0)
+ return NANO_UCODE_CHECKSUM_FAIL;
+ /* Made it here huh? Then it looks valid to us.
+ * If there's anything else wrong, the CPU will reject the update */
+ return NANO_UCODE_VALID;
+}
+
+static void nano_print_ucode_status(ucode_update_status stat)
+{
+ switch(stat)
+ {
+ case UCODE_UPDATE_SUCCESS:
+ printk(BIOS_INFO, "Microcode update succesful.\n");
+ break;
+ case UCODE_UPDATE_FAIL:
+ printk(BIOS_ALERT, "Microcode update failed, bad environment."
+ "Update was not applied.\n");
+ break;
+ case UCODE_UPDATE_WRONG_CPU:
+ printk(BIOS_ALERT, "Update not applicable to this CPU.\n");
+ break;
+ case UCODE_INVALID_UPDATE_BLOCK:
+ printk(BIOS_ALERT, "Microcode block invalid."
+ "Update was not applied.\n");
+ break;
+ default:
+ printk(BIOS_ALERT, "Unknown status. No update applied.\n");
+ }
+}
+
+unsigned int nano_update_ucode(void)
+{
+ size_t i;
+ unsigned int n_updates = 0;
+ const struct cbfs_file *cbfs_ucode;
+ u32 fms = cpuid_eax(0x1);
+
+ cbfs_ucode = cbfs_find("cpu_microcode_blob.bin");
+ /* Oops, did you forget to include the microcode ? */
+ if(cbfs_ucode == NULL) {
+ printk(BIOS_ALERT, "WARNING: No microcode file found in CBFS. "
+ "Aborting microcode updates\n");
+ return 0;
+ }
+
+ /* Considering we are running with eXecute-In-Place (XIP), there's no
+ * need to worry that accessing data from ROM will slow us down.
+ * Microcode data should be aligned to a 4-byte boundary, but CBFS
+ * already does that for us (Do you, CBFS?) */
+ const u32 *ucode_data = CBFS_SUBHEADER(cbfs_ucode);
+ const u32 ucode_len = ntohl(cbfs_ucode->len);
+
+ /* We might do a lot of loops searching for the microcode updates, but
+ * keep in mind, nano_ucode_is_valid searches for the signature before
+ * doing anything else. */
+ for( i = 0; i < (ucode_len >> 2); /* don't increment i here */ )
+ {
+ ucode_update_status stat;
+ const nano_ucode_header * ucode = (void *)(&ucode_data[i]);
+ if(nano_ucode_is_valid(ucode) != NANO_UCODE_VALID) {
+ i++;
+ continue;
+ }
+ /* Since we have a valid microcode, there's no need to search
+ * in this region, so we restart our search at the end of this
+ * microcode */
+ i += (ucode->total_size >> 2);
+ /* Is the microcode compatible with our CPU? */
+ if(ucode->applicable_fms != fms) continue;
+ /* For our most curious users */
+ nano_print_ucode_info(ucode);
+ /* The meat of the pie */
+ stat = nano_apply_ucode(ucode);
+ /* The user might want to know how the update went */
+ nano_print_ucode_status(stat);
+ if(stat == UCODE_UPDATE_SUCCESS) n_updates++;
+ }
+
+ return n_updates;
+}
diff --git a/src/cpu/via/nano/update_ucode.h b/src/cpu/via/nano/update_ucode.h
new file mode 100644
index 0000000..6a22d18
--- /dev/null
+++ b/src/cpu/via/nano/update_ucode.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __UPDATE_UCODE_H
+#define __UPDATE_UCODE_H
+
+#include <console/console.h>
+#include <cpu/cpu.h>
+
+#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079
+#define MSR_IA32_BIOS_SIGN_ID 0x0000008b
+#define MSR_UCODE_UPDATE_STATUS 0x00001205
+
+#define NANO_UCODE_SIGNATURE 0x53415252
+#define NANO_UCODE_HEADER_SIZE 0x30
+
+/* These are values returned by the CPU after we attempt microcode updates.
+ * We care what these values are exactly, so we define them to be sure */
+typedef enum {
+ UCODE_UPDATE_NOT_ATTEMPTED = 0x0,
+ UCODE_UPDATE_SUCCESS = 0x1,
+ UCODE_UPDATE_FAIL = 0x2,
+ UCODE_UPDATE_WRONG_CPU = 0x3,
+ UCODE_INVALID_UPDATE_BLOCK = 0x4,
+} ucode_update_status;
+
+
+typedef enum {
+ NANO_UCODE_VALID = 0, /* We only care that valid == 0 */
+ NANO_UCODE_SIGNATURE_ERROR,
+ NANO_UCODE_WRONG_SIZE,
+ NANO_UCODE_CHECKSUM_FAIL,
+} ucode_validity;
+
+typedef struct {
+ u32 signature; /* NANO_UCODE_SIGNATURE */
+ u32 update_revision; /* Revision of the update header */
+ u16 year; /* Year of patch release */
+ u8 day; /* Day of patch release */
+ u8 month; /* Month of patch release */
+ u32 applicable_fms; /* Fam/model/stepping to which ucode applies */
+ u32 checksum; /* Two's complement checksum of ucode+header */
+ u32 loader_revision; /* Revision of hardware ucode update loader*/
+ u32 rfu_1; /* Reservod for future use */
+ u32 payload_size; /* Size of the ucode payload only */
+ u32 total_size; /* Size of the ucode, including header */
+ char name[8]; /* ASCII string of ucode filename */
+ u32 rfu_2; /* Reservod for future use */
+ /* First double-word of the ucode payload
+ * Its address represents the beginning of the ucode update we need to
+ * send to the CPU */
+ u32 ucode_start;
+
+} nano_ucode_header;
+
+unsigned int nano_update_ucode(void);
+
+#endif /* __UPDATE_UCODE_H */
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1245
-gerrit
commit 2196e18d95e9e2bc86b1fb6dd7ffa36d72f6d5cc
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Fri Jul 20 00:11:21 2012 -0500
buildsystem: Make CPU microcode updating more configurable
This patch aims to improve the microcode in CBFS handling that was
brought by the last patches from Stefan and the Chromium team.
Choices in Kconfig
- 1) Generate microcode from tree (default)
- 2) Include external microcode file
- 3) Do not put microcode in CBFS
The idea is to give the user full control over including non-free
blobs in the final ROM image.
MICROCODE_INCLUDE_PATH Kconfig variable is eliminated. Microcode
is handled by a special class, cpu_microcode, as such:
cpu_microcode-y += microcode_file.c
MICROCODE_IN_CBFS should, in the future, be eliminated. Right now it is
needed by intel microcode updating. Once all intel cpus are converted to
cbfs updating, this variable can go away.
These files are then compiled and assembled into a binary CBFS file.
The advantage of doing it this way versus the current method is that
1) The rule is CPU-agnostic
2) Gives user more control over if and how to include microcode blobs
3) The rules for building the microcode binary are kept in
src/cpu/Makefile.inc, and thus would not clobber the other makefiles,
which are already overloaded and very difficult to navigate.
Change-Id: I38d0c9851691aa112e93031860e94895857ebb76
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
Makefile.inc | 2 +-
src/arch/x86/Makefile.inc | 28 ++++-----
src/cpu/Kconfig | 88 ++++++++++++++++++++++++++-
src/cpu/Makefile.inc | 37 ++++++++++++
src/cpu/intel/microcode/Makefile.inc | 20 ++-----
src/cpu/intel/microcode/microcode.c | 8 +-
src/cpu/intel/microcode/microcode_blob.c | 22 -------
src/cpu/intel/model_206ax/Kconfig | 3 +-
src/cpu/intel/model_206ax/Makefile.inc | 2 +
src/cpu/intel/model_206ax/microcode_blob.c | 22 +++++++
src/include/cpu/intel/microcode.h | 2 +-
11 files changed, 169 insertions(+), 65 deletions(-)
diff --git a/Makefile.inc b/Makefile.inc
index 083d423..d06a24d 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -59,7 +59,7 @@ subdirs-y += site-local
#######################################################################
# Add source classes and their build options
-classes-y := ramstage romstage driver smm
+classes-y := ramstage romstage driver smm cpu_microcode
romstage-c-ccopts:=-D__PRE_RAM__
romstage-S-ccopts:=-D__PRE_RAM__
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 306f239..3b27fe3 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -1,6 +1,8 @@
+################################################################################
##
## This file is part of the coreboot project.
##
+## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
## Copyright (C) 2009-2010 coresystems GmbH
## Copyright (C) 2009 Ronald G. Minnich
##
@@ -17,8 +19,8 @@
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
+################################################################################
-#######################################################################
# Take care of subdirectories
subdirs-y += boot
# subdirs-y += init
@@ -34,13 +36,7 @@ cmos_layout.bin-type = 0x01aa
OPTION_TABLE_H:=$(obj)/option_table.h
endif
-ifeq ($(CONFIG_MICROCODE_IN_CBFS),y)
-cbfs-files-y += microcode_blob.bin
-microcode_blob.bin-file = $(obj)/microcode_blob.bin
-microcode_blob.bin-type = 0x53
-endif
-
-#######################################################################
+################################################################################
# Build the final rom image
COREBOOT_ROM_DEPENDENCIES:=
ifeq ($(CONFIG_PAYLOAD_ELF),y)
@@ -123,7 +119,7 @@ cbfs-files-$(CONFIG_BOOTSPLASH) += bootsplash.jpg
bootsplash.jpg-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE))
bootsplash.jpg-type := bootsplash
-#######################################################################
+################################################################################
# i386 specific tools
NVRAMTOOL:=$(objutil)/nvramtool/nvramtool
@@ -135,7 +131,7 @@ $(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.l
@printf " OPTION $(subst $(obj)/,,$(@))\n"
$(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -L $@
-#######################################################################
+################################################################################
# Common recipes for all stages
$(objcbfs)/%.bin: $(objcbfs)/%.elf
@@ -150,7 +146,7 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug
$(OBJCOPY) --add-gnu-debuglink=$< $@.tmp
mv $@.tmp $@
-#######################################################################
+################################################################################
# Build the coreboot_ram (stage 2)
$(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld
@@ -174,7 +170,7 @@ $(objgenerated)/ramstage.a: $$(ramstage-objs)
rm -f $@
$(AR) cr $@ $^
-#######################################################################
+################################################################################
# Ramstage for AP CPU (AMD K8, obsolete?)
$(objcbfs)/coreboot_ap.debug: $(objgenerated)/coreboot_ap.o $(src)/arch/x86/init/ldscript_apc.lb
@@ -185,7 +181,7 @@ $(objgenerated)/coreboot_ap.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@
-#######################################################################
+################################################################################
# done
crt0s = $(src)/arch/x86/init/prologue.inc
@@ -264,7 +260,7 @@ ifeq ($(CONFIG_HAVE_BUS_CONFIG),y)
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c
endif
-#######################################################################
+################################################################################
# Build the final rom image
$(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL)
@@ -274,7 +270,7 @@ $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL
$(CONFIG_CBFS_PREFIX)/romstage x $(shell cat $(objcbfs)/base_xip.txt)
mv $@.tmp $@
-#######################################################################
+################################################################################
# Build the bootblock
bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb
@@ -331,7 +327,7 @@ else
$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $<
endif
-#######################################################################
+################################################################################
# Build the romstage
$(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index baf686e..1ed721f 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -62,10 +62,90 @@ config SSE2
streaming SIMD instructions. Some parts of coreboot can be built
with more efficient code if SSE2 instructions are available.
-config MICROCODE_IN_CBFS
- bool "Look for microcode in CBFS"
+endif # ARCH_X86
+
+config CPU_MICROCODE_IN_CBFS
+ bool
default n
+
+choice
+ prompt "Include CPU microcode in CBFS"
+ default CPU_MICROCODE_CBFS_GENERATE if CPU_MICROCODE_IN_CBFS
+ default CPU_MICROCODE_CBFS_NONE if !CPU_MICROCODE_IN_CBFS
+
+config CPU_MICROCODE_CBFS_GENERATE
+ bool "Generate from tree"
help
- Load microcode updates from CBFS instead of compiling them in.
+ Select this option if you want microcode updates to be assembled when
+ building coreboot and included in the final image as a separate CBFS
+ file. Microcode will not be hard-coded into ramstage.
-endif # ARCH_X86
+ The microcode file and may be removed from the ROM image at a later
+ time with cbfstool, if desired.
+
+ If unsure, select this option.
+
+config CPU_MICROCODE_CBFS_EXTERNAL
+ bool "Include external microcode file"
+ help
+ Select this option if you want to include an external file containing
+ the CPU microcode. This will be included as a separate file in CBFS.
+ A word of caution: only select this option if you are sure the
+ microcode that you have is newer than the microcode shipping with
+ coreboot.
+
+ The microcode file and may be removed from the ROM image at a later
+ time with cbfstool, if desired.
+
+ If unsure, select "Generate from tree"
+
+config CPU_MICROCODE_FILE
+ string "Path and filename of CPU microcode"
+ depends on CPU_MICROCODE_CBFS_EXTERNAL
+ default "cpu_microcode.bin"
+ help
+ The path and filename of the file containing the CPU microcode.
+
+config CPU_MICROCODE_CBFS_NONE
+ bool "Do not include microcode updates"
+ help
+ Select this option if you do not want CPU microcode included in CBFS.
+ Note that for some CPUs, the microcode is hard-coded into the source
+ tree and is not loaded from CBFS. In this case, microcode will still
+ be updated. There is a push to move all microcode to CBFS, but this
+ change is not implemented for all CPUs.
+
+ This option currently applies to:
+ - Intel SandyBridge/IvyBridge
+ - VIA Nano
+
+ Microcode may be added to the ROM image at a later time with cbfstool,
+ if desired.
+
+ If unsure, select "Generate from tree"
+
+ The GOOD:
+ Microcode updates intend to solve issues that have been discovered
+ after CPU production. The expected effect is that systems work as
+ intended with the updated microcode, but we have also seen cases where
+ issues were solved by not applying microcode updates.
+
+ The BAD:
+ Note that some operating system include these same microcode patches,
+ so you may need to also disable microcode updates in your operating
+ system for this option to have an effect.
+
+ The UGLY:
+ A word of CAUTION: some CPUs depend on microcode updates to function
+ correctly. Not updating the microcode may leave the CPU operating at
+ less than optimal performance, or may cause outright hangups.
+ There are CPUs where coreboot cannot properly initialize the CPU
+ without microcode updates
+ For example, if running with the factory microcode, some Intel
+ SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs
+ will hang when changing the frequency.
+
+ Make sure you have a way of flashing the ROM externally before
+ selecting this option.
+
+endchoice
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 57273cf..938a8df 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -1,3 +1,40 @@
+################################################################################
+## Subdirectories
+################################################################################
subdirs-y += amd
subdirs-y += intel
subdirs-y += via
+
+################################################################################
+## Rules for building the microcode blob in CBFS
+################################################################################
+
+ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE), y)
+
+cbfs-files-y += cpu_microcode_blob.bin
+
+cpu_microcode_blob.bin-type = 0x53
+
+# External microcode file, or are we generating one ?
+ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y)
+cpu_microcode_blob.bin-file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE))
+else
+cpu_microcode_blob.bin-file = $(obj)/cpu_microcode_blob.bin
+endif
+
+# In case we have more than one "source" (cough) files containing microcode, we
+# Link them together in one large blob, so that we get all the microcode updates
+# in one file. This makes it easier for objcopy in the final step.
+# The --entry=0 is just here to suppress the LD warning. It does not affect the
+# final microcode file.
+$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs)
+ @printf " LD $(subst $(obj)/,,$(@))\n"
+ $(LD) -static --entry=0 $< -o $@
+
+# We have a lot of useless data in the large blob, and we are only interested in
+# the data section, so we only copy that part to the final microcode file
+$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
+ @printf " MICROCODE $(subst $(obj)/,,$(@))\n"
+ $(OBJCOPY) -j .data -O binary $< $@
+
+endif
diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc
index f4d0102..22655c9 100644
--- a/src/cpu/intel/microcode/Makefile.inc
+++ b/src/cpu/intel/microcode/Makefile.inc
@@ -1,15 +1,5 @@
-ramstage-y += microcode.c
-
-
-ifeq ($(CONFIG_MICROCODE_IN_CBFS),y)
-
-SRC_PATH = src/cpu/intel/microcode
-FLAGS = -I $(CONFIG_MICROCODE_INCLUDE_PATH) -include $(obj)/config.h
-$(obj)/microcode_blob.o: $(SRC_PATH)/microcode_blob.c
- $(CC) $(FLAGS) -MMD -c -o $@ $<
-
-$(obj)/microcode_blob.bin: $(obj)/microcode_blob.o
- objcopy -j .data -O binary $< $@
-
--include $(obj)/microcode_blob.d
-endif
+################################################################################
+## One small file with the awesome super-power of updating the cpu microcode
+## directly from CBFS. You have been WARNED!!!
+################################################################################
+ramstage-y += microcode.c
\ No newline at end of file
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index e84bad9..a4471ca 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -28,7 +28,7 @@
#include <cpu/x86/msr.h>
#include <cpu/intel/microcode.h>
-#if CONFIG_MICROCODE_IN_CBFS
+#if CONFIG_CPU_MICROCODE_IN_CBFS
#ifdef __PRE_RAM__
#include <arch/cbfs.h>
#else
@@ -77,7 +77,7 @@ static inline u32 read_microcode_rev(void)
return msr.hi;
}
-#if CONFIG_MICROCODE_IN_CBFS
+#if CONFIG_CPU_MICROCODE_IN_CBFS
static
#endif
void intel_update_microcode(const void *microcode_updates)
@@ -144,9 +144,9 @@ void intel_update_microcode(const void *microcode_updates)
}
}
-#if CONFIG_MICROCODE_IN_CBFS
+#if CONFIG_CPU_MICROCODE_IN_CBFS
-#define MICROCODE_CBFS_FILE "microcode_blob.bin"
+#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin"
void intel_update_microcode_from_cbfs(void)
{
diff --git a/src/cpu/intel/microcode/microcode_blob.c b/src/cpu/intel/microcode/microcode_blob.c
deleted file mode 100644
index 69238a9..0000000
--- a/src/cpu/intel/microcode/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-unsigned microcode[] = {
-#include <microcode_blob.h>
-};
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index 9cc6edd..15cbd17 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -12,8 +12,7 @@ config CPU_SPECIFIC_OPTIONS
select SSE2
select UDELAY_LAPIC
select SMM_TSEG
- select MICROCODE_IN_CBFS
- #select AP_IN_SIPI_WAIT
+ select CPU_MICROCODE_IN_CBFS
config BOOTBLOCK_CPU_INIT
string
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index e9b8e6d..6ab4840 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -5,4 +5,6 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+
cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c
new file mode 100644
index 0000000..c2538e8
--- /dev/null
+++ b/src/cpu/intel/model_206ax/microcode_blob.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+unsigned microcode[] = {
+#include "microcode_blob.h"
+};
diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h
index 289e919..e9c13f9 100644
--- a/src/include/cpu/intel/microcode.h
+++ b/src/include/cpu/intel/microcode.h
@@ -21,7 +21,7 @@
#define __CPU__INTEL__MICROCODE__
#ifndef __PRE_RAM__
-#if CONFIG_MICROCODE_IN_CBFS
+#if CONFIG_CPU_MICROCODE_IN_CBFS
void intel_update_microcode_from_cbfs(void);
#else
void intel_update_microcode(const void *microcode_updates);
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1257
-gerrit
commit d2c757aa4ce339b1f8dc510a3f6c4e01ea9cb402
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Fri Jul 20 18:17:01 2012 -0500
VIA Nano: Add support for VIA Nano CPUs
Add code to do the following for the VIA Nano CPUs
- Update microcode
- Set maximum frequency
- Initialize power states
- Set up cache
Attempting to change the voltage or frequency of the CPU without
applying the microcode update will hang the CPU, so we only do
transitions if we can verify the microcode has been updated.
The microcode is updated directly from CBFS. No microcode is
included in ramstage. The microcode is not included in this
commit.
To get the microcode, run bios_extract on the manufacturer supplied
BIOS, and look for the file marked "P6 Microcode". Include this
file in CBFS.
You can have the build system include this file automatically by
selecting Expert Mode, then look under
'Chipset' -> 'Include CPU microcode in CBFS' ->
Include external microcode file (check)
'Path and filename of CPU microcode' should contain the location of
the microcode file previously extracted.
Change-Id: I586aaca5715e047b42ef901d66772ace0e6b655e
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/cpu/via/Kconfig | 1 +
src/cpu/via/Makefile.inc | 6 +-
src/cpu/via/nano/Kconfig | 41 ++++++++
src/cpu/via/nano/Makefile.inc | 33 ++++++
src/cpu/via/nano/nano_init.c | 204 +++++++++++++++++++++++++++++++++++++++
src/cpu/via/nano/update_ucode.c | 150 ++++++++++++++++++++++++++++
src/cpu/via/nano/update_ucode.h | 73 ++++++++++++++
7 files changed, 505 insertions(+), 3 deletions(-)
diff --git a/src/cpu/via/Kconfig b/src/cpu/via/Kconfig
index 570d408..5c38c91 100644
--- a/src/cpu/via/Kconfig
+++ b/src/cpu/via/Kconfig
@@ -1,2 +1,3 @@
source src/cpu/via/c3/Kconfig
source src/cpu/via/c7/Kconfig
+source src/cpu/via/nano/Kconfig
diff --git a/src/cpu/via/Makefile.inc b/src/cpu/via/Makefile.inc
index 2616111..f1e198d 100644
--- a/src/cpu/via/Makefile.inc
+++ b/src/cpu/via/Makefile.inc
@@ -1,3 +1,3 @@
-subdirs-$(CONFIG_CPU_VIA_C7) += c7
-subdirs-$(CONFIG_CPU_VIA_C3) += c3
-
+subdirs-$(CONFIG_CPU_VIA_C7) += c7
+subdirs-$(CONFIG_CPU_VIA_C3) += c3
+subdirs-$(CONFIG_CPU_VIA_NANO) += nano
diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig
new file mode 100644
index 0000000..3b1c213
--- /dev/null
+++ b/src/cpu/via/nano/Kconfig
@@ -0,0 +1,41 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program. If not, see <http://www.gnu.org/licenses/>.
+##
+
+config CPU_VIA_NANO
+ bool
+
+if CPU_VIA_NANO
+
+config CPU_SPECIFIC_OPTIONS
+ def_bool y
+ select UDELAY_TSC
+ select MMX
+ select SSE2
+ select CACHE_AS_RAM
+ select CPU_MICROCODE_IN_CBFS
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xffe00000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x8000
+
+endif # CPU_VIA_NANO
diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc
new file mode 100644
index 0000000..6b0c1e9
--- /dev/null
+++ b/src/cpu/via/nano/Makefile.inc
@@ -0,0 +1,33 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program. If not, see <http://www.gnu.org/licenses/>.
+##
+
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+
+driver-y += nano_init.c
+ramstage-y += update_ucode.c
+
+# We need to hear from VIA to get permission to include this file in the
+# official coreboot repository. Until then, we leave this commented out
+# cpu-microcode-y += nano_ucode_blob.c
+
+cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc
diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c
new file mode 100644
index 0000000..417119f
--- /dev/null
+++ b/src/cpu/via/nano/nano_init.c
@@ -0,0 +1,204 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "update_ucode.h"
+#include <console/console.h>
+#include <device/device.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/cache.h>
+#include <delay.h>
+
+#define MODEL_NANO 0x2
+#define MODEL_NANO_3000_B0 0x8
+#define MODEL_NANO_3000_B2 0xa
+
+#define MSR_IA32_PERF_STATUS 0x00000198
+#define MSR_IA32_PERF_CTL 0x00000199
+#define MSR_IA32_MISC_ENABLE 0x000001a0
+#define NANO_MYSTERIOUS_MSR 0x120e
+
+static void nano_finish_fid_vid_transition(void)
+{
+
+ msr_t msr;
+ /* Wait until the power transition ends */
+ int cnt = 0;
+ do {
+ udelay(16);
+ msr = rdmsr(MSR_IA32_PERF_STATUS);
+ cnt++;
+ if (cnt > 128) {
+ printk(BIOS_WARNING,
+ "Error while updating multiplier and voltage\n");
+ break;
+ }
+ } while (msr.lo & ((1 << 16) | (1 << 17)));
+
+ /* Print the new FID and Voltage */
+ u8 cur_vid = (msr.lo >> 0) & 0xff;
+ u8 cur_fid = (msr.lo >> 8) & 0xff;
+ printk(BIOS_INFO, "New CPU multiplier: %dx\n", cur_fid);
+ printk(BIOS_INFO, "New Voltage ID : %dx\n", cur_vid);
+}
+
+static void nano_set_max_fid_vid(void)
+{
+ msr_t msr;
+ /* Get voltage and frequency info */
+ msr = rdmsr(MSR_IA32_PERF_STATUS);
+ u8 min_fid = (msr.hi >> 24);
+ u8 max_fid = (msr.hi >> 8) & 0xff;
+ u8 min_vid = (msr.hi >> 16) & 0xff;
+ u8 max_vid = (msr.hi >> 0) & 0xff;
+ u8 cur_vid = (msr.lo >> 0) & 0xff;
+ u8 cur_fid = (msr.lo >> 8) & 0xff;
+
+ printk(BIOS_INFO, "CPU multiplier: %dx (min %dx; max %dx)\n",
+ cur_fid, min_fid, max_fid);
+ printk(BIOS_INFO, "Voltage ID : %dx (min %dx; max %dx)\n",
+ cur_vid, min_vid, max_vid);
+
+ if( (cur_fid != max_fid) || (cur_vid != max_vid) ) {
+ /* Set highest frequency and VID */
+ msr.lo = msr.hi;
+ msr.hi = 0;
+ wrmsr(MSR_IA32_PERF_CTL, msr);
+ /* Wait for the transition to complete, otherwise, the CPU
+ * might reset itself repeatedly */
+ nano_finish_fid_vid_transition();
+ }
+ /* As a side note, if we didn't update the microcode by this point, the
+ * second PLL will not lock correctly. The clock will still be provided
+ * by the first PLL, and execution will continue normally, ___until___
+ * the CPU switches PLL. Once that happens we will no longer have a
+ * working clock source, and the CPU will hang
+ * Moral of the story: update the microcode, or don't change FID
+ * This check is handled before calling nano_power() */
+}
+
+static void nano_power(void)
+{
+ msr_t msr;
+ /* Enable Powersaver */
+ msr = rdmsr(MSR_IA32_MISC_ENABLE);
+ msr.lo |= (1 << 16);
+ wrmsr(MSR_IA32_MISC_ENABLE, msr);
+
+ /* Enable 6 bit or 7-bit VRM support
+ * This MSR is not documented by VIA docs, other than setting these
+ * bits */
+ msr = rdmsr(NANO_MYSTERIOUS_MSR);
+ msr.lo |= ( (1<<7) | (1<<4) );
+ /* FIXME: Do we have a 6-bit or 7-bit VRM?
+ * set bit [5] for 7-bit, or don't set it for 6 bit VRM
+ * This will probably require a Kconfig option
+ * My board has a 7-bit VRM, so I can't test the 6-bit VRM stuff */
+ msr.lo |= (1<<5);
+ wrmsr(NANO_MYSTERIOUS_MSR, msr);
+
+ /* Set the maximum frequency and voltage */
+ nano_set_max_fid_vid();
+
+ /* Enable TM3 */
+ msr = rdmsr(MSR_IA32_MISC_ENABLE);
+ msr.lo |= ( (1<<3) | (1<<13) );
+ wrmsr(MSR_IA32_MISC_ENABLE, msr);
+
+ u8 stepping = ( cpuid_eax(0x1) ) &0xf;
+ if(stepping >= MODEL_NANO_3000_B0) {
+ /* Hello Nano 3000. The Terminator needs a CPU upgrade */
+ /* Enable C1e, C2e, C3e, and C4e states */
+ msr = rdmsr(MSR_IA32_MISC_ENABLE);
+ msr.lo |= ( (1<<25) | (1<<26) | (1<<31)); /* C1e, C2e, C3e */
+ msr.hi |= (1<<0); /* C4e */
+ wrmsr(MSR_IA32_MISC_ENABLE, msr);
+ }
+
+ /* Lock on Powersaver */
+ msr = rdmsr(MSR_IA32_MISC_ENABLE);
+ msr.lo |= (1<<20);
+ wrmsr(MSR_IA32_MISC_ENABLE, msr);
+}
+
+static void nano_init(device_t dev)
+{
+ struct cpuinfo_x86 c;
+
+ get_fms(&c, dev->device);
+
+ /* We didn't test this on the Nano 1000/2000 series, so warn the user */
+ if(c.x86_mask < MODEL_NANO_3000_B0) {
+ printk(BIOS_EMERG, "WARNING: This CPU has not been tested. "
+ "Please report any issues encountered. \n");
+ }
+ switch (c.x86_mask) {
+ case MODEL_NANO:
+ printk(BIOS_INFO, "VIA Nano");
+ break;
+ case MODEL_NANO_3000_B0:
+ printk(BIOS_INFO, "VIA Nano 3000 rev B0");
+ break;
+ case MODEL_NANO_3000_B2:
+ printk(BIOS_INFO, "VIA Nano 3000 rev B2");
+ break;
+ default:
+ printk(BIOS_EMERG, "Stepping not recognized: %x\n", c.x86_mask);
+ }
+ printk(BIOS_INFO, "\n");
+
+ /* We only read microcode from CBFS. If we don't have any microcode in
+ * CBFS, we'll just get back with 0 updates. User choice FTW. */
+ unsigned int n_updates = nano_update_ucode();
+
+ if(n_updates != 0){
+ nano_power();
+ } else {
+ /* Changing the frequency or voltage without first updating the
+ * microcode will hang the CPU, so just don't do it */
+ printk(BIOS_EMERG, "WARNING: CPU Microcode not updated.\n"
+ " Will not change frequency, as this may hang the CPU.\n");
+ }
+
+ /* Turn on cache */
+ x86_enable_cache();
+ /* Set up Memory Type Range Registers */
+ x86_setup_mtrrs();
+ x86_mtrr_check();
+ /* Enable the local cpu apics */
+ setup_lapic();
+}
+
+static struct device_operations cpu_dev_ops = {
+ .init = nano_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+ {X86_VENDOR_CENTAUR, 0x06f2}, // VIA NANO 1000/2000 Series
+ {X86_VENDOR_CENTAUR, 0x06f8}, // VIA NANO 3000 rev B0
+ {X86_VENDOR_CENTAUR, 0x06fa}, // VIA NANO 3000 rev B2
+ {0, 0},
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+ .ops = &cpu_dev_ops,
+ .id_table = cpu_table,
+};
diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c
new file mode 100644
index 0000000..8f7ee22
--- /dev/null
+++ b/src/cpu/via/nano/update_ucode.c
@@ -0,0 +1,150 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "update_ucode.h"
+#include <cpu/x86/msr.h>
+#include <console/console.h>
+#include <stddef.h>
+#include <cpu/cpu.h>
+#include <arch/cpu.h>
+#include <cbfs.h>
+
+static ucode_update_status nano_apply_ucode(const nano_ucode_header *ucode)
+{
+ printk(BIOS_SPEW, "Attempting to apply microcode update\n");
+
+ msr_t msr;
+ /* Address of ucode block goes in msr.lo for 32-bit mode
+ * Now remember, we need to pass the address of the actual microcode,
+ * not the header. The header is just there to help us. */
+ msr.lo = (unsigned int)(&(ucode->ucode_start));
+ msr.hi = 0;
+ wrmsr(MSR_IA32_BIOS_UPDT_TRIG, msr);
+
+ /* Let's see if we updated succesfully */
+ msr = rdmsr(MSR_UCODE_UPDATE_STATUS);
+
+ return msr.lo & 0x07;
+}
+
+static void nano_print_ucode_info(const nano_ucode_header *ucode)
+{
+ printk(BIOS_SPEW, "Microcode update information:\n");
+ printk(BIOS_SPEW, "Name: %8s\n", ucode->name );
+ printk(BIOS_SPEW, "Date: %u/%u/%u\n", ucode->month,
+ ucode->day, ucode->year );
+}
+
+static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode)
+{
+ /* We must have a valid signature */
+ if(ucode->signature != NANO_UCODE_SIGNATURE)
+ return NANO_UCODE_SIGNATURE_ERROR;
+ /* The size of the head must be exactly 12 double words */
+ if( (ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE)
+ return NANO_UCODE_WRONG_SIZE;
+
+ /* How about a checksum ? Checksum must be 0
+ * Two's complement done over the entire file, including the header */
+ int i;
+ u32 check = 0;
+ u32 *raw = (void*) ucode;
+ for(i = 0 ; i < ((ucode->total_size) >> 2); i++) {
+ check += raw[i];
+ }
+ if(check != 0)
+ return NANO_UCODE_CHECKSUM_FAIL;
+ /* Made it here huh? Then it looks valid to us.
+ * If there's anything else wrong, the CPU will reject the update */
+ return NANO_UCODE_VALID;
+}
+
+static void nano_print_ucode_status(ucode_update_status stat)
+{
+ switch(stat)
+ {
+ case UCODE_UPDATE_SUCCESS:
+ printk(BIOS_INFO, "Microcode update succesful.\n");
+ break;
+ case UCODE_UPDATE_FAIL:
+ printk(BIOS_ALERT, "Microcode update failed, bad environment."
+ "Update was not applied.\n");
+ break;
+ case UCODE_UPDATE_WRONG_CPU:
+ printk(BIOS_ALERT, "Update not applicable to this CPU.\n");
+ break;
+ case UCODE_INVALID_UPDATE_BLOCK:
+ printk(BIOS_ALERT, "Microcode block invalid."
+ "Update was not applied.\n");
+ break;
+ default:
+ printk(BIOS_ALERT, "Unknown status. No update applied.\n");
+ }
+}
+
+unsigned int nano_update_ucode(void)
+{
+ size_t i;
+ unsigned int n_updates = 0;
+ const struct cbfs_file *cbfs_ucode;
+ u32 fms = cpuid_eax(0x1);
+
+ cbfs_ucode = cbfs_find("cpu_microcode_blob.bin");
+ /* Oops, did you forget to include the microcode ? */
+ if(cbfs_ucode == NULL) {
+ printk(BIOS_ALERT, "WARNING: No microcode file found in CBFS. "
+ "Aborting microcode updates\n");
+ return 0;
+ }
+
+ /* Considering we are running with eXecute-In-Place (XIP), there's no
+ * need to worry that accessing data from ROM will slow us down.
+ * Microcode data should be aligned to a 4-byte boundary, but CBFS
+ * already does that for us (Do you, CBFS?) */
+ const u32 *ucode_data = CBFS_SUBHEADER(cbfs_ucode);
+ const u32 ucode_len = ntohl(cbfs_ucode->len);
+
+ /* We might do a lot of loops searching for the microcode updates, but
+ * keep in mind, nano_ucode_is_valid searches for the signature before
+ * doing anything else. */
+ for( i = 0; i < (ucode_len >> 2); /* don't increment i here */ )
+ {
+ ucode_update_status stat;
+ const nano_ucode_header * ucode = (void *)(&ucode_data[i]);
+ if(nano_ucode_is_valid(ucode) != NANO_UCODE_VALID) {
+ i++;
+ continue;
+ }
+ /* Since we have a valid microcode, there's no need to search
+ * in this region, so we restart our search at the end of this
+ * microcode */
+ i += (ucode->total_size >> 2);
+ /* Is the microcode compatible with our CPU? */
+ if(ucode->applicable_fms != fms) continue;
+ /* For our most curious users */
+ nano_print_ucode_info(ucode);
+ /* The meat of the pie */
+ stat = nano_apply_ucode(ucode);
+ /* The user might want to know how the update went */
+ nano_print_ucode_status(stat);
+ if(stat == UCODE_UPDATE_SUCCESS) n_updates++;
+ }
+
+ return n_updates;
+}
diff --git a/src/cpu/via/nano/update_ucode.h b/src/cpu/via/nano/update_ucode.h
new file mode 100644
index 0000000..14063fa
--- /dev/null
+++ b/src/cpu/via/nano/update_ucode.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __UPDATE_UCODE_H
+#define __UPDATE_UCODE_H
+
+#include <console/console.h>
+#include <cpu/cpu.h>
+
+#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079
+#define MSR_IA32_BIOS_SIGN_ID 0x0000008b
+#define MSR_UCODE_UPDATE_STATUS 0x00001205
+
+#define NANO_UCODE_SIGNATURE 0x53415252
+#define NANO_UCODE_HEADER_SIZE 0x30
+
+/* These are values returned by the CPU after we attempt microcode updates.
+ * We care what these values are exactly, so we define them to be sure */
+typedef enum {
+ UCODE_UPDATE_NOT_ATTEMPTED = 0x0,
+ UCODE_UPDATE_SUCCESS = 0x1,
+ UCODE_UPDATE_FAIL = 0x2,
+ UCODE_UPDATE_WRONG_CPU = 0x3,
+ UCODE_INVALID_UPDATE_BLOCK = 0x4,
+} ucode_update_status;
+
+
+typedef enum ucode_validity_enum {
+ NANO_UCODE_VALID = 0, /* We only care that valid == 0 */
+ NANO_UCODE_SIGNATURE_ERROR,
+ NANO_UCODE_WRONG_SIZE,
+ NANO_UCODE_CHECKSUM_FAIL,
+} ucode_validity;
+
+typedef struct {
+ u32 signature; /* NANO_UCODE_SIGNATURE */
+ u32 update_revision; /* Revision of the update header */
+ u16 year; /* Year of patch release */
+ u8 day; /* Day of patch release */
+ u8 month; /* Month of patch release */
+ u32 applicable_fms; /* Fam/model/stepping to which ucode applies */
+ u32 checksum; /* Two's complement checksum of ucode+header */
+ u32 loader_revision; /* Revision of hardware ucode update loader*/
+ u32 rfu_1; /* Reservod for future use */
+ u32 payload_size; /* Size of the ucode payload only */
+ u32 total_size; /* Size of the ucode, including header */
+ char name[8]; /* ASCII string of ucode filename */
+ u32 rfu_2; /* Reservod for future use */
+ /* First double-word of the ucode payload
+ * Its address represents the beginning of the ucode update we need to
+ * send to the CPU */
+ u32 ucode_start;
+
+} nano_ucode_header;
+
+unsigned int nano_update_ucode(void);
+
+#endif /* __UPDATE_UCODE_H */